From nobody Tue Oct 7 05:44:09 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 55A75258CF2; Mon, 14 Jul 2025 14:59:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752505178; cv=none; b=N0McramoUpGy/KSXoMwPsmrOIimmZbGcXTwWgqjTJdvDjJxzttp1qWor60lexHugQOlUyb2Tak39pGmEU9jBDWXg2ZP9a91CBGdYuTVvS7Qw11A0CkCT4RAVXeQh38EYgfW6lE9ulrwpOBoSwYJYufewqG9VphIsA/15LHBO1hQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752505178; c=relaxed/simple; bh=zdIA1OrZ3QwuE1iTyT9RAIBjGDyxK+dHldknrTLLHLA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=C2lKphpp/zAsdwTMueY5fy7VxWNAq8/u6GFD1W5D5mVwdnDSWgPDU4LwyALm/7G5VQbosnjoUiaWDjka8Tur7l/l9G9Tk5XYK2iGQiGok/nrq/BlKMh9XM8b1541lCXpYppXFI9siL2yyeHlQ8q3mwDlgKRAR0H5gc89BfxdFiw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=k6obcYIq; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="k6obcYIq" Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 56E9rYvw004879; Mon, 14 Jul 2025 14:59:23 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= UxWZKZdiJDX0DMRAQWw1ZpYiBrf/IfhPklk9LZUV/sw=; b=k6obcYIq8QPiPF6D 1Glu3uLOaLiBFhXPFKMdpnAi9yusHq3lzS2Osgp88/eFtR5EGr93I7nxt1/up0Wb ilpNWHh3BVUY4017Lixt92wvO1DtOJFIBynfBc1hC5ZuKL4q4RPM8WJ6XVWU73gh 7j6m/SqcbgKzyS1jkWy/g0LpvtrEMo+5kskudy1gAE7ie9l67UjzQ/CoFhLuvVVp 01JzkGjUySrfYWSRVaE5DGByVYHfGnCwMMjsavMWGvkko8NS2AsTIjTRq8He0akd iJfTDhgXmFarHE/lKcSlJkDC3g73SCxvvefiVSkKxLOg7bO3bixKoTS+wQ/iwSLM pP7KQQ== Received: from nasanppmta01.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 47ufxaw19d-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 14 Jul 2025 14:59:23 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 56EExMVU010472 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 14 Jul 2025 14:59:22 GMT Received: from nsssdc-sh01-lnx.ap.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Mon, 14 Jul 2025 07:59:20 -0700 From: Luo Jie Date: Mon, 14 Jul 2025 22:58:56 +0800 Subject: [PATCH net-next v2 2/3] net: phy: qcom: qca808x: Support PHY counter Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250714-qcom_phy_counter-v2-2-94dde9d9769f@quicinc.com> References: <20250714-qcom_phy_counter-v2-0-94dde9d9769f@quicinc.com> In-Reply-To: <20250714-qcom_phy_counter-v2-0-94dde9d9769f@quicinc.com> To: Andrew Lunn , Heiner Kallweit , Russell King , "David S. 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Additionally, add PHY counter operations and integrate shared functions. Signed-off-by: Luo Jie --- drivers/net/phy/qcom/qca808x.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/drivers/net/phy/qcom/qca808x.c b/drivers/net/phy/qcom/qca808x.c index 6de16c0eaa08..8eb51b1a006c 100644 --- a/drivers/net/phy/qcom/qca808x.c +++ b/drivers/net/phy/qcom/qca808x.c @@ -93,6 +93,7 @@ MODULE_LICENSE("GPL"); =20 struct qca808x_priv { int led_polarity_mode; + struct qcom_phy_hw_stats hw_stats; }; =20 static int qca808x_phy_fast_retrain_config(struct phy_device *phydev) @@ -243,6 +244,10 @@ static int qca808x_config_init(struct phy_device *phyd= ev) =20 qca808x_fill_possible_interfaces(phydev); =20 + ret =3D qcom_phy_counter_config(phydev); + if (ret) + return ret; + /* Configure adc threshold as 100mv for the link 10M */ return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_ADC_THRESHOLD, QCA808X_ADC_THRESHOLD_MASK, @@ -622,6 +627,22 @@ static int qca808x_led_polarity_set(struct phy_device = *phydev, int index, active_low ? 0 : QCA808X_LED_ACTIVE_HIGH); } =20 +static int qca808x_update_stats(struct phy_device *phydev) +{ + struct qca808x_priv *priv =3D phydev->priv; + + return qcom_phy_update_stats(phydev, &priv->hw_stats); +} + +static void qca808x_get_phy_stats(struct phy_device *phydev, + struct ethtool_eth_phy_stats *eth_stats, + struct ethtool_phy_stats *stats) +{ + struct qca808x_priv *priv =3D phydev->priv; + + qcom_phy_get_stats(stats, priv->hw_stats); +} + static struct phy_driver qca808x_driver[] =3D { { /* Qualcomm QCA8081 */ @@ -651,6 +672,8 @@ static struct phy_driver qca808x_driver[] =3D { .led_hw_control_set =3D qca808x_led_hw_control_set, .led_hw_control_get =3D qca808x_led_hw_control_get, .led_polarity_set =3D qca808x_led_polarity_set, + .update_stats =3D qca808x_update_stats, + .get_phy_stats =3D qca808x_get_phy_stats, }, }; =20 module_phy_driver(qca808x_driver); --=20 2.34.1