From nobody Tue Oct 7 05:33:22 2025 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DE9AF25487A; Mon, 14 Jul 2025 14:09:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.112 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752502142; cv=pass; b=XtK1Ad6GCk+6IXkaBO2uHQ535TPk/FE3I1SB0rJwL51v8wh9S2ZP4Hx0wH0B6bRrNR+afw4NwSi7cVq4oMnLq7IShu2qJE/7L9Q28xG5FTM7zwyoi4ppPhr1NddJnJizB+HTau36P4ozoXaV7RUfGEery79ATGLIn7ixP1OdzVs= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752502142; c=relaxed/simple; bh=DyE00FQQcVIJDfFG/s7v2hZ5Ny7wTLLb2HbgheaPhuw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=uXTQDoNJxTbZ7MOhgHqf7W7t120RAAOdStzbdNnFOqU+tbGncYRcl7MN30RBP+PE/yzT2ZWpMeMgd6ZErv6NXYHUp89B4slI8/tSpJtcw/y+99NWtOL6riw2v5yudIN0olodLqh/qrKbDPIGJtTH2D9U2HkNh4en4aQVC3+NrsE= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (1024-bit key) header.d=collabora.com header.i=nicolas.frattaroli@collabora.com header.b=PbtmtBnt; arc=pass smtp.client-ip=136.143.188.112 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=collabora.com header.i=nicolas.frattaroli@collabora.com header.b="PbtmtBnt" ARC-Seal: i=1; a=rsa-sha256; t=1752502115; cv=none; d=zohomail.com; s=zohoarc; b=g5b0fQ33w0mBOU0W69Sj9WQvn1mS0dem8B7L44jg3B0cqmc75fBWy/Apgznc5AULhxa0IMUw2VJJ/rQ5YvNKyYUPFhdgqlfki9jyJ2jcN5r4x0w6Ba+3Nr+Xse8H554yk31QgJzm1XX0ssHwSAWRwVCU4PxjgK3aGit9F7+noMU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752502115; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=jEhtdpIHUaCWWVMpS6h9pG+ezJ1H5i0vcgbppdJiInc=; b=MyQmGqZyz39lksZtS/Rv5fGxxSrcdBKMr4uyl0zpH5moirTKdhI9RyWgVKGztkul+880QOMXalVE7+baVp8aKiAb7tRjCjLak1hPFhNdILTTSnviBHQF2/wMHB16kUpJcyXgAOZRFEjHKxGyGtZAzmOXciWm/zdUlgpAcqgLpu4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=collabora.com; spf=pass smtp.mailfrom=nicolas.frattaroli@collabora.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1752502115; s=zohomail; d=collabora.com; i=nicolas.frattaroli@collabora.com; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=jEhtdpIHUaCWWVMpS6h9pG+ezJ1H5i0vcgbppdJiInc=; b=PbtmtBntlL3qEeoZnc13L9h2LJwkX8NOAljQurTH0yI+4sO2+BExYtRoVJ7tmiDW SHjI5emM34tv21NGWl+weUUqS31/AMBRlwPhFj7Ebjodau1AvN/kMZC1kqn9LUbrna3 Vmog7vCirb5T0H2G8qTzmrp/6nZJnRRQrRBHum/o= Received: by mx.zohomail.com with SMTPS id 1752502113853539.0996011954999; Mon, 14 Jul 2025 07:08:33 -0700 (PDT) From: Nicolas Frattaroli Date: Mon, 14 Jul 2025 16:08:14 +0200 Subject: [PATCH v2 1/4] dt-bindings: cpufreq: Add mediatek,mt8196-cpufreq-hw binding Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250714-mt8196-cpufreq-v2-1-cc85e78855c7@collabora.com> References: <20250714-mt8196-cpufreq-v2-0-cc85e78855c7@collabora.com> In-Reply-To: <20250714-mt8196-cpufreq-v2-0-cc85e78855c7@collabora.com> To: "Rafael J. Wysocki" , Viresh Kumar , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno Cc: kernel@collabora.com, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Nicolas Frattaroli X-Mailer: b4 0.14.2 The MediaTek MT8196 SoC has new cpufreq hardware, with added memory register ranges to control Dynamic-Voltage-Frequency-Scaling. The DVFS hardware is controlled through a set of registers referred to as "FDVFS"; one is a location from which a magic number is read to ensure DVFS should be used, the other is a region to set the desired target frequency that DVFS should aim towards for each performance domain. Instead of working around the old binding and its already established meanings for the reg items, add a new binding. The FDVFS register memory regions are at the beginning, which allows us to easily expand this binding for future SoCs which may have more than 3 performance domains. Signed-off-by: Nicolas Frattaroli --- .../cpufreq/mediatek,mt8196-cpufreq-hw.yaml | 86 ++++++++++++++++++= ++++ 1 file changed, 86 insertions(+) diff --git a/Documentation/devicetree/bindings/cpufreq/mediatek,mt8196-cpuf= req-hw.yaml b/Documentation/devicetree/bindings/cpufreq/mediatek,mt8196-cpu= freq-hw.yaml new file mode 100644 index 0000000000000000000000000000000000000000..26bf21e05888646b4d1bdac95bf= ba0f36e037ffd --- /dev/null +++ b/Documentation/devicetree/bindings/cpufreq/mediatek,mt8196-cpufreq-hw.= yaml @@ -0,0 +1,86 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/cpufreq/mediatek,mt8196-cpufreq-hw.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek CPUFreq for MT8196 and related SoCs + +maintainers: + - Nicolas Frattaroli + +description: + MT8196 uses CPUFreq management hardware that supports dynamic voltage + frequency scaling (dvfs), and can support several performance domains. + +properties: + compatible: + const: mediatek,mt8196-cpufreq-hw + + reg: + items: + - description: FDVFS magic number register region + - description: FDVFS control register region + - description: OPP tables and control for performance domain 0 + - description: OPP tables and control for performance domain 1 + - description: OPP tables and control for performance domain 2 + + "#performance-domain-cells": + description: + Number of cells in a performance domain specifier. Must be 1. + const: 1 + +required: + - compatible + - reg + - "#performance-domain-cells" + +additionalProperties: false + +examples: + - | + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu0: cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a720"; + enable-method =3D "psci"; + performance-domains =3D <&performance 0>; + reg =3D <0x000>; + }; + + /* ... */ + + cpu6: cpu@600 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-x4"; + enable-method =3D "psci"; + performance-domains =3D <&performance 1>; + reg =3D <0x600>; + }; + + cpu7: cpu@700 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-x925"; + enable-method =3D "psci"; + performance-domains =3D <&performance 2>; + reg =3D <0x700>; + }; + }; + + /* ... */ + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + performance: performance-controller@c2c2034 { + compatible =3D "mediatek,mt8196-cpufreq-hw"; + reg =3D <0 0xc2c2034 0 0x4>, <0 0xc220400 0 0x20>, + <0 0xc2c0f20 0 0x120>, <0 0xc2c1040 0 0x120>, + <0 0xc2c1160 0 0x120>; + #performance-domain-cells =3D <1>; + }; + }; --=20 2.50.1 From nobody Tue Oct 7 05:33:22 2025 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E0100256C73; Mon, 14 Jul 2025 14:09:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.112 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752502145; cv=pass; b=sKvI5/Jw6MbDqcx4OL+EhuIQwNtaAZfLRhaYKDj7u9otKKeQ+vWm0pKoWIA9dZ2zYjKXESkscs6mj5EMGcjiqDtXGSn7ft51jlJ8xImydqunAmJva2tIVvuRbPV1xKhgQTBPKYCfd8rJfkrNSv30Cp2ViKbVeScovbTU7DkZ5H8= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752502145; c=relaxed/simple; bh=iiE856a8qrn9eSAZP9zr22J4JnHQvG6Myo0VZp/y/FA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=f2gNg2X2i+OFDnzE/Pq7TCBko8kxUUcvo1p+d+TbXrIhZq7EB2iGhRXK16ZHGBJJ16HFATvEXSBCiL9wJYgHV2EVskCmQKw7QGpfLznyklhsIDeeLnbeF2h+gscO+uHHvT0VvioMU/uXF/9LvL7sk3LInHSp8EMLUmyXvIH6Fo4= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (1024-bit key) header.d=collabora.com header.i=nicolas.frattaroli@collabora.com header.b=J3yoWZvM; arc=pass smtp.client-ip=136.143.188.112 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=collabora.com header.i=nicolas.frattaroli@collabora.com header.b="J3yoWZvM" ARC-Seal: i=1; a=rsa-sha256; t=1752502119; cv=none; d=zohomail.com; s=zohoarc; b=P8UDvgsVwVciUQt96dTQIa29Smi8epcHkilTE2jhIgd25ttH4jxGxPNoo13IiFXfyBA/N3vcvjoopzouIj4G8Ren6bSpvtsQfm61MBPg/v86KAVYD8rapcbrTi2/kkkxbm6OS0Se2RqUMwzb5jNhrQYtfZDwpkWrUw9+ae8uAcI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752502119; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=zwvjge2GeqaMg396NhQCN7JdiOQJJjUcM4eCQwiwFj0=; b=Q3bGZySeLOjOLGbTE28edXMK/4B1OWTFsS6Rta9+IGG+mevcQDAEjnjJ7RggU3CAnI9oRVs/WItK/boZdd3K6Ojcq3coYcZoHzgis1sUBjH6nV3N1Hrp13rM9thy+D7zWS4xnx328vLPfFpI77NetCi5H8n/gtgFMgObaEnkkbY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=collabora.com; spf=pass smtp.mailfrom=nicolas.frattaroli@collabora.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1752502119; s=zohomail; d=collabora.com; i=nicolas.frattaroli@collabora.com; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=zwvjge2GeqaMg396NhQCN7JdiOQJJjUcM4eCQwiwFj0=; b=J3yoWZvM9Jb01k3qPIHdkpDSGi1HcXftJdv58jzN7Dy2B2xViu4dNzDrbt0aDNnT wlAEaVrvrJzGBk4UrK3EbJOtXDKTiqv2Lk7wczEEvay2HN6JdTDf4cjz+63KcGwhfXM Y4BVqMxykVj1u9yYaKqYay79QxhRa7R+6SF+fQyE= Received: by mx.zohomail.com with SMTPS id 1752502117056801.62164174365; Mon, 14 Jul 2025 07:08:37 -0700 (PDT) From: Nicolas Frattaroli Date: Mon, 14 Jul 2025 16:08:15 +0200 Subject: [PATCH v2 2/4] cpufreq: mediatek-hw: Refactor match data into struct Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250714-mt8196-cpufreq-v2-2-cc85e78855c7@collabora.com> References: <20250714-mt8196-cpufreq-v2-0-cc85e78855c7@collabora.com> In-Reply-To: <20250714-mt8196-cpufreq-v2-0-cc85e78855c7@collabora.com> To: "Rafael J. Wysocki" , Viresh Kumar , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno Cc: kernel@collabora.com, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Nicolas Frattaroli X-Mailer: b4 0.14.2 While the driver could get away with having the per-compatible match data just be an array of the reg offsets, the only thing it used it for right now, this doesn't really allow it to be extended in any meaningful way if some other per-variant information needs to be communicated. Refactor the code to make the DT match data a struct, which currently only contains a single member: the reg offsets. This will allow this struct to be extended with other members for other hardware variants. Signed-off-by: Nicolas Frattaroli Reviewed-by: AngeloGioacchino Del Regno --- drivers/cpufreq/mediatek-cpufreq-hw.c | 28 ++++++++++++++++++---------- 1 file changed, 18 insertions(+), 10 deletions(-) diff --git a/drivers/cpufreq/mediatek-cpufreq-hw.c b/drivers/cpufreq/mediat= ek-cpufreq-hw.c index 74f1b4c796e4cc9ebccf50dd4e165a1eba03136a..b2aba1842226c7d24a8b9599ea6= 2408cac9f803c 100644 --- a/drivers/cpufreq/mediatek-cpufreq-hw.c +++ b/drivers/cpufreq/mediatek-cpufreq-hw.c @@ -41,15 +41,22 @@ struct mtk_cpufreq_data { struct resource *res; void __iomem *base; int nr_opp; + const struct mtk_cpufreq_variant *variant; }; =20 -static const u16 cpufreq_mtk_offsets[REG_ARRAY_SIZE] =3D { - [REG_FREQ_LUT_TABLE] =3D 0x0, - [REG_FREQ_ENABLE] =3D 0x84, - [REG_FREQ_PERF_STATE] =3D 0x88, - [REG_FREQ_HW_STATE] =3D 0x8c, - [REG_EM_POWER_TBL] =3D 0x90, - [REG_FREQ_LATENCY] =3D 0x110, +struct mtk_cpufreq_variant { + const u16 reg_offsets[REG_ARRAY_SIZE]; +}; + +static const struct mtk_cpufreq_variant cpufreq_mtk_base_variant =3D { + .reg_offsets =3D { + [REG_FREQ_LUT_TABLE] =3D 0x0, + [REG_FREQ_ENABLE] =3D 0x84, + [REG_FREQ_PERF_STATE] =3D 0x88, + [REG_FREQ_HW_STATE] =3D 0x8c, + [REG_EM_POWER_TBL] =3D 0x90, + [REG_FREQ_LATENCY] =3D 0x110, + }, }; =20 static int __maybe_unused @@ -157,7 +164,7 @@ static int mtk_cpu_create_freq_table(struct platform_de= vice *pdev, =20 static int mtk_cpu_resources_init(struct platform_device *pdev, struct cpufreq_policy *policy, - const u16 *offsets) + const struct mtk_cpufreq_variant *variant) { struct mtk_cpufreq_data *data; struct device *dev =3D &pdev->dev; @@ -200,9 +207,10 @@ static int mtk_cpu_resources_init(struct platform_devi= ce *pdev, =20 data->base =3D base; data->res =3D res; + data->variant =3D variant; =20 for (i =3D REG_FREQ_LUT_TABLE; i < REG_ARRAY_SIZE; i++) - data->reg_bases[i] =3D base + offsets[i]; + data->reg_bases[i] =3D base + variant->reg_offsets[i]; =20 ret =3D mtk_cpu_create_freq_table(pdev, data); if (ret) { @@ -336,7 +344,7 @@ static void mtk_cpufreq_hw_driver_remove(struct platfor= m_device *pdev) } =20 static const struct of_device_id mtk_cpufreq_hw_match[] =3D { - { .compatible =3D "mediatek,cpufreq-hw", .data =3D &cpufreq_mtk_offsets }, + { .compatible =3D "mediatek,cpufreq-hw", .data =3D &cpufreq_mtk_base_vari= ant }, {} }; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250714-mt8196-cpufreq-v2-3-cc85e78855c7@collabora.com> References: <20250714-mt8196-cpufreq-v2-0-cc85e78855c7@collabora.com> In-Reply-To: <20250714-mt8196-cpufreq-v2-0-cc85e78855c7@collabora.com> To: "Rafael J. Wysocki" , Viresh Kumar , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno Cc: kernel@collabora.com, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Nicolas Frattaroli X-Mailer: b4 0.14.2 As it stood, the mediatek cpufreq driver could get away with never really having a private driver instance struct. This is because all data was stored in the per-domain structs. However, this complicates matters when actual per-instance data like the variant struct is introduced. Instead of having a pointer to it for every domain, have a pointer to a global "priv" struct that can be extended over time, and rename the "data" struct to "domain" to distinguish its purpose better. Signed-off-by: Nicolas Frattaroli Reviewed-by: AngeloGioacchino Del Regno --- drivers/cpufreq/mediatek-cpufreq-hw.c | 42 ++++++++++++++++++++++---------= ---- 1 file changed, 27 insertions(+), 15 deletions(-) diff --git a/drivers/cpufreq/mediatek-cpufreq-hw.c b/drivers/cpufreq/mediat= ek-cpufreq-hw.c index b2aba1842226c7d24a8b9599ea62408cac9f803c..53611077d0d9a2d9865cf771568= ab71abc0e6fbd 100644 --- a/drivers/cpufreq/mediatek-cpufreq-hw.c +++ b/drivers/cpufreq/mediatek-cpufreq-hw.c @@ -35,13 +35,17 @@ enum { REG_ARRAY_SIZE, }; =20 -struct mtk_cpufreq_data { +struct mtk_cpufreq_priv { + const struct mtk_cpufreq_variant *variant; +}; + +struct mtk_cpufreq_domain { + struct mtk_cpufreq_priv *parent; struct cpufreq_frequency_table *table; void __iomem *reg_bases[REG_ARRAY_SIZE]; struct resource *res; void __iomem *base; int nr_opp; - const struct mtk_cpufreq_variant *variant; }; =20 struct mtk_cpufreq_variant { @@ -63,7 +67,7 @@ static int __maybe_unused mtk_cpufreq_get_cpu_power(struct device *cpu_dev, unsigned long *uW, unsigned long *KHz) { - struct mtk_cpufreq_data *data; + struct mtk_cpufreq_domain *data; struct cpufreq_policy *policy; int i; =20 @@ -90,7 +94,7 @@ mtk_cpufreq_get_cpu_power(struct device *cpu_dev, unsigne= d long *uW, static int mtk_cpufreq_hw_target_index(struct cpufreq_policy *policy, unsigned int index) { - struct mtk_cpufreq_data *data =3D policy->driver_data; + struct mtk_cpufreq_domain *data =3D policy->driver_data; =20 writel_relaxed(index, data->reg_bases[REG_FREQ_PERF_STATE]); =20 @@ -99,7 +103,7 @@ static int mtk_cpufreq_hw_target_index(struct cpufreq_po= licy *policy, =20 static unsigned int mtk_cpufreq_hw_get(unsigned int cpu) { - struct mtk_cpufreq_data *data; + struct mtk_cpufreq_domain *data; struct cpufreq_policy *policy; unsigned int index; =20 @@ -118,7 +122,7 @@ static unsigned int mtk_cpufreq_hw_get(unsigned int cpu) static unsigned int mtk_cpufreq_hw_fast_switch(struct cpufreq_policy *poli= cy, unsigned int target_freq) { - struct mtk_cpufreq_data *data =3D policy->driver_data; + struct mtk_cpufreq_domain *data =3D policy->driver_data; unsigned int index; =20 index =3D cpufreq_table_find_index_dl(policy, target_freq, false); @@ -129,7 +133,7 @@ static unsigned int mtk_cpufreq_hw_fast_switch(struct c= pufreq_policy *policy, } =20 static int mtk_cpu_create_freq_table(struct platform_device *pdev, - struct mtk_cpufreq_data *data) + struct mtk_cpufreq_domain *data) { struct device *dev =3D &pdev->dev; u32 temp, i, freq, prev_freq =3D 0; @@ -164,9 +168,9 @@ static int mtk_cpu_create_freq_table(struct platform_de= vice *pdev, =20 static int mtk_cpu_resources_init(struct platform_device *pdev, struct cpufreq_policy *policy, - const struct mtk_cpufreq_variant *variant) + struct mtk_cpufreq_priv *priv) { - struct mtk_cpufreq_data *data; + struct mtk_cpufreq_domain *data; struct device *dev =3D &pdev->dev; struct resource *res; struct of_phandle_args args; @@ -187,6 +191,8 @@ static int mtk_cpu_resources_init(struct platform_devic= e *pdev, index =3D args.args[0]; of_node_put(args.np); =20 + data->parent =3D priv; + res =3D platform_get_resource(pdev, IORESOURCE_MEM, index); if (!res) { dev_err(dev, "failed to get mem resource %d\n", index); @@ -207,10 +213,9 @@ static int mtk_cpu_resources_init(struct platform_devi= ce *pdev, =20 data->base =3D base; data->res =3D res; - data->variant =3D variant; =20 for (i =3D REG_FREQ_LUT_TABLE; i < REG_ARRAY_SIZE; i++) - data->reg_bases[i] =3D base + variant->reg_offsets[i]; + data->reg_bases[i] =3D base + priv->variant->reg_offsets[i]; =20 ret =3D mtk_cpu_create_freq_table(pdev, data); if (ret) { @@ -231,7 +236,7 @@ static int mtk_cpufreq_hw_cpu_init(struct cpufreq_polic= y *policy) { struct platform_device *pdev =3D cpufreq_get_driver_data(); int sig, pwr_hw =3D CPUFREQ_HW_STATUS | SVS_HW_STATUS; - struct mtk_cpufreq_data *data; + struct mtk_cpufreq_domain *data; unsigned int latency; int ret; =20 @@ -270,7 +275,7 @@ static int mtk_cpufreq_hw_cpu_init(struct cpufreq_polic= y *policy) =20 static void mtk_cpufreq_hw_cpu_exit(struct cpufreq_policy *policy) { - struct mtk_cpufreq_data *data =3D policy->driver_data; + struct mtk_cpufreq_domain *data =3D policy->driver_data; struct resource *res =3D data->res; void __iomem *base =3D data->base; =20 @@ -283,7 +288,7 @@ static void mtk_cpufreq_hw_cpu_exit(struct cpufreq_poli= cy *policy) static void mtk_cpufreq_register_em(struct cpufreq_policy *policy) { struct em_data_callback em_cb =3D EM_DATA_CB(mtk_cpufreq_get_cpu_power); - struct mtk_cpufreq_data *data =3D policy->driver_data; + struct mtk_cpufreq_domain *data =3D policy->driver_data; =20 em_dev_register_perf_domain(get_cpu_device(policy->cpu), data->nr_opp, &em_cb, policy->cpus, true); @@ -305,6 +310,7 @@ static struct cpufreq_driver cpufreq_mtk_hw_driver =3D { =20 static int mtk_cpufreq_hw_driver_probe(struct platform_device *pdev) { + struct mtk_cpufreq_priv *priv; const void *data; int ret, cpu; struct device *cpu_dev; @@ -328,7 +334,13 @@ static int mtk_cpufreq_hw_driver_probe(struct platform= _device *pdev) if (!data) return -EINVAL; =20 - platform_set_drvdata(pdev, (void *) data); + priv =3D devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->variant =3D data; + + platform_set_drvdata(pdev, priv); cpufreq_mtk_hw_driver.driver_data =3D pdev; =20 ret =3D cpufreq_register_driver(&cpufreq_mtk_hw_driver); --=20 2.50.1 From nobody Tue Oct 7 05:33:22 2025 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 15152255F24; Mon, 14 Jul 2025 14:09:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.112 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752502149; cv=pass; b=hGF3mUWkSda8o2tY3QmB7H4/wx0NhjpAot7nRi1EKLy3ueM/Qj/NIlRfTYp4jVtLZtE3vLaal1ftmsQqTBwgspXWMXdIeV6mgPUcx9zp2jzFmDRR6hr9pZcpDzwhEEBbwuZY3phSKD6Ssba0RV2B/Prhg0vNkAcFStTjD7gACho= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752502149; c=relaxed/simple; bh=nhkuw18hHnTBS0LfnX5V2oCgCQ8MK3eUg/O46/Tmjfw=; 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Mon, 14 Jul 2025 07:08:45 -0700 (PDT) From: Nicolas Frattaroli Date: Mon, 14 Jul 2025 16:08:17 +0200 Subject: [PATCH v2 4/4] cpufreq: mediatek-hw: Add support for MT8196 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250714-mt8196-cpufreq-v2-4-cc85e78855c7@collabora.com> References: <20250714-mt8196-cpufreq-v2-0-cc85e78855c7@collabora.com> In-Reply-To: <20250714-mt8196-cpufreq-v2-0-cc85e78855c7@collabora.com> To: "Rafael J. Wysocki" , Viresh Kumar , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno Cc: kernel@collabora.com, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Nicolas Frattaroli X-Mailer: b4 0.14.2 The MT8196 SoC uses DVFS to set a desired target frequency for each CPU core. It also uses slightly different register offsets. Add support for it, which necessitates reworking how the mmio regs are acquired, as mt8196 has the fdvfs config register and the fdvfs registers as two reg items before the performance domains. I've verified with both `sysbench cpu run` and `head -c 10G \ /dev/urandom | pigz -p 8 -c - | pv -ba > /dev/null` that we don't just get a higher reported clock frequency, but that the observed performance also increases, by a factor of 2.64 in an 8 thread sysbench test. Signed-off-by: Nicolas Frattaroli --- drivers/cpufreq/mediatek-cpufreq-hw.c | 75 +++++++++++++++++++++++++++++++= ++-- 1 file changed, 72 insertions(+), 3 deletions(-) diff --git a/drivers/cpufreq/mediatek-cpufreq-hw.c b/drivers/cpufreq/mediat= ek-cpufreq-hw.c index 53611077d0d9a2d9865cf771568ab71abc0e6fbd..de6b2b8f6600f23148a7a24cafe= ae339903ba119 100644 --- a/drivers/cpufreq/mediatek-cpufreq-hw.c +++ b/drivers/cpufreq/mediatek-cpufreq-hw.c @@ -24,6 +24,8 @@ #define POLL_USEC 1000 #define TIMEOUT_USEC 300000 =20 +#define MT8196_FDVFS_MAGIC 0xABCD0001UL + enum { REG_FREQ_LUT_TABLE, REG_FREQ_ENABLE, @@ -36,7 +38,10 @@ enum { }; =20 struct mtk_cpufreq_priv { + struct device *dev; const struct mtk_cpufreq_variant *variant; + void __iomem *fdvfs_config; + void __iomem *fdvfs; }; =20 struct mtk_cpufreq_domain { @@ -49,7 +54,10 @@ struct mtk_cpufreq_domain { }; =20 struct mtk_cpufreq_variant { + int (*init)(struct mtk_cpufreq_priv *priv); const u16 reg_offsets[REG_ARRAY_SIZE]; + const unsigned int fdvfs_fdiv; + const unsigned int domain_offset; }; =20 static const struct mtk_cpufreq_variant cpufreq_mtk_base_variant =3D { @@ -63,6 +71,37 @@ static const struct mtk_cpufreq_variant cpufreq_mtk_base= _variant =3D { }, }; =20 +static int mtk_cpufreq_hw_mt8196_init(struct mtk_cpufreq_priv *priv) +{ + priv->fdvfs_config =3D devm_of_iomap(priv->dev, priv->dev->of_node, 0, NU= LL); + if (IS_ERR_OR_NULL(priv->fdvfs_config)) + return dev_err_probe(priv->dev, PTR_ERR(priv->fdvfs_config), + "failed to get fdvfs-config iomem\n"); + + if (readl_relaxed(priv->fdvfs_config) =3D=3D MT8196_FDVFS_MAGIC) { + priv->fdvfs =3D devm_of_iomap(priv->dev, priv->dev->of_node, 1, NULL); + if (IS_ERR_OR_NULL(priv->fdvfs)) + return dev_err_probe(priv->dev, PTR_ERR(priv->fdvfs), + "failed to get fdvfs iomem\n"); + } + + return 0; +} + +static const struct mtk_cpufreq_variant cpufreq_mtk_mt8196_variant =3D { + .init =3D mtk_cpufreq_hw_mt8196_init, + .reg_offsets =3D { + [REG_FREQ_LUT_TABLE] =3D 0x0, + [REG_FREQ_ENABLE] =3D 0x84, + [REG_FREQ_PERF_STATE] =3D 0x88, + [REG_FREQ_HW_STATE] =3D 0x8c, + [REG_EM_POWER_TBL] =3D 0x90, + [REG_FREQ_LATENCY] =3D 0x114, + }, + .fdvfs_fdiv =3D 26000, + .domain_offset =3D 2, +}; + static int __maybe_unused mtk_cpufreq_get_cpu_power(struct device *cpu_dev, unsigned long *uW, unsigned long *KHz) @@ -91,12 +130,31 @@ mtk_cpufreq_get_cpu_power(struct device *cpu_dev, unsi= gned long *uW, return 0; } =20 +static void mtk_cpufreq_hw_fdvfs_switch(unsigned int target_freq, + struct cpufreq_policy *policy) +{ + struct mtk_cpufreq_domain *data =3D policy->driver_data; + struct mtk_cpufreq_priv *priv =3D data->parent; + unsigned int cpu; + + target_freq =3D DIV_ROUND_UP(target_freq, priv->variant->fdvfs_fdiv); + for_each_cpu(cpu, policy->real_cpus) { + writel_relaxed(target_freq, priv->fdvfs + cpu * 4); + } +} + static int mtk_cpufreq_hw_target_index(struct cpufreq_policy *policy, unsigned int index) { struct mtk_cpufreq_domain *data =3D policy->driver_data; + unsigned int target_freq; =20 - writel_relaxed(index, data->reg_bases[REG_FREQ_PERF_STATE]); + if (data->parent->fdvfs) { + target_freq =3D policy->freq_table[index].frequency; + mtk_cpufreq_hw_fdvfs_switch(target_freq, policy); + } else { + writel_relaxed(index, data->reg_bases[REG_FREQ_PERF_STATE]); + } =20 return 0; } @@ -127,7 +185,10 @@ static unsigned int mtk_cpufreq_hw_fast_switch(struct = cpufreq_policy *policy, =20 index =3D cpufreq_table_find_index_dl(policy, target_freq, false); =20 - writel_relaxed(index, data->reg_bases[REG_FREQ_PERF_STATE]); + if (data->parent->fdvfs) + mtk_cpufreq_hw_fdvfs_switch(target_freq, policy); + else + writel_relaxed(index, data->reg_bases[REG_FREQ_PERF_STATE]); =20 return policy->freq_table[index].frequency; } @@ -188,7 +249,7 @@ static int mtk_cpu_resources_init(struct platform_devic= e *pdev, if (ret < 0) return ret; =20 - index =3D args.args[0]; + index =3D args.args[0] + priv->variant->domain_offset; of_node_put(args.np); =20 data->parent =3D priv; @@ -339,6 +400,13 @@ static int mtk_cpufreq_hw_driver_probe(struct platform= _device *pdev) return -ENOMEM; =20 priv->variant =3D data; + priv->dev =3D &pdev->dev; + + if (priv->variant->init) { + ret =3D priv->variant->init(priv); + if (ret) + return ret; + } =20 platform_set_drvdata(pdev, priv); cpufreq_mtk_hw_driver.driver_data =3D pdev; @@ -357,6 +425,7 @@ static void mtk_cpufreq_hw_driver_remove(struct platfor= m_device *pdev) =20 static const struct of_device_id mtk_cpufreq_hw_match[] =3D { { .compatible =3D "mediatek,cpufreq-hw", .data =3D &cpufreq_mtk_base_vari= ant }, + { .compatible =3D "mediatek,mt8196-cpufreq-hw", .data =3D &cpufreq_mtk_mt= 8196_variant }, {} }; MODULE_DEVICE_TABLE(of, mtk_cpufreq_hw_match); --=20 2.50.1