From nobody Tue Oct 7 07:07:37 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1820E27FD5A for ; Sun, 13 Jul 2025 15:53:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752422023; cv=none; b=MGzouHtTlRm2GVy9eCODXUvXCrVfpT0UwSC1od6nmXOShGq5EHZBEQze6QOWnAcjp0IGHSgYfbjb9WHLPIMwod4/FiuqQQSuqsUE+bdQtQkVBb8GaKOeA+OgvDVIBEAw+CZtFSf3yEDdcdGQ6yrlzRMmbBlOrkc7I2sGCApxlQw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752422023; c=relaxed/simple; bh=Cqc5//1m2maOwm2HqoVNQT8UubcKcYojQ6LRXW5C2TI=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=a3Qe3reu5Zwx1TICovq6DeEKM4m62t0kYQlyDvyLNVpya8UeCBB69MEQmPkYjgcIk7tJ7DqsPaIQYM/7aIq6GkCOW+HKhvl0ZEQuXTeilTzfMBlVVQCwjjVnQzd6+ba2EK/0KyuIS1szruEwNfjYLiWYTpTjb+FqvZuhg+gn3gY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=PsaBkIjQ; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="PsaBkIjQ" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 123D0C4CEF8; Sun, 13 Jul 2025 15:53:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1752422022; bh=Cqc5//1m2maOwm2HqoVNQT8UubcKcYojQ6LRXW5C2TI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=PsaBkIjQX1uFTFpJYFGZRixiM3tZmDdbQfTKFjZmIM9VHFqsH5BK4oPlBlCwRqyzX 6dARtro6O+SqxdJc7+9plVD2xztnB0AkXF1vB/PjDnPEsAILqfRhsqLjapj86AHnuy hrH4HndSrptzCbWz3MYt9LH/ibB5Zj1Xr2/MfTCDcHOFjOsSBlA+rNTCL1aPy6Knkc Y0rPiwojcA6Kd5CkPSolQe0NWs+8/s7UWUYvitMiijVeZDgtXU8A+IrtzhujUJ+8Em hssztG/cAp5axo6983MpuIqKYDNw2ZyDNryzXXllyxszzY2Lmjb/QN6Ev5jBArXebX VA8fWQj6EKlJg== From: guoren@kernel.org To: palmer@dabbelt.com, guoren@kernel.org, conor@kernel.org, alexghiti@rivosinc.com, paul.walmsley@sifive.com, bjorn@rivosinc.com, eobras@redhat.com, corbet@lwn.net, peterlin@andestech.com, rabenda.cn@gmail.com Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH V2 1/2] riscv: Move vendor errata definitions to new header Date: Sun, 13 Jul 2025 11:53:20 -0400 Message-Id: <20250713155321.2064856-2-guoren@kernel.org> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20250713155321.2064856-1-guoren@kernel.org> References: <20250713155321.2064856-1-guoren@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: "Guo Ren (Alibaba DAMO Academy)" Move vendor errata definitions into errata_list_vendors.h. Signed-off-by: Guo Ren (Alibaba DAMO Academy) Reviewed-by: Alexandre Ghiti Tested-by: Han Gao --- arch/riscv/include/asm/errata_list.h | 19 +--------------- arch/riscv/include/asm/errata_list_vendors.h | 24 ++++++++++++++++++++ 2 files changed, 25 insertions(+), 18 deletions(-) create mode 100644 arch/riscv/include/asm/errata_list_vendors.h diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/= errata_list.h index 6e426ed7919a..18c9f7ee9b7c 100644 --- a/arch/riscv/include/asm/errata_list.h +++ b/arch/riscv/include/asm/errata_list.h @@ -10,24 +10,7 @@ #include #include #include - -#ifdef CONFIG_ERRATA_ANDES -#define ERRATA_ANDES_NO_IOCP 0 -#define ERRATA_ANDES_NUMBER 1 -#endif - -#ifdef CONFIG_ERRATA_SIFIVE -#define ERRATA_SIFIVE_CIP_453 0 -#define ERRATA_SIFIVE_CIP_1200 1 -#define ERRATA_SIFIVE_NUMBER 2 -#endif - -#ifdef CONFIG_ERRATA_THEAD -#define ERRATA_THEAD_MAE 0 -#define ERRATA_THEAD_PMU 1 -#define ERRATA_THEAD_GHOSTWRITE 2 -#define ERRATA_THEAD_NUMBER 3 -#endif +#include =20 #ifdef __ASSEMBLY__ =20 diff --git a/arch/riscv/include/asm/errata_list_vendors.h b/arch/riscv/incl= ude/asm/errata_list_vendors.h new file mode 100644 index 000000000000..a37d1558f39f --- /dev/null +++ b/arch/riscv/include/asm/errata_list_vendors.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef ASM_ERRATA_LIST_VENDORS_H +#define ASM_ERRATA_LIST_VENDORS_H + +#ifdef CONFIG_ERRATA_ANDES +#define ERRATA_ANDES_NO_IOCP 0 +#define ERRATA_ANDES_NUMBER 1 +#endif + +#ifdef CONFIG_ERRATA_SIFIVE +#define ERRATA_SIFIVE_CIP_453 0 +#define ERRATA_SIFIVE_CIP_1200 1 +#define ERRATA_SIFIVE_NUMBER 2 +#endif + +#ifdef CONFIG_ERRATA_THEAD +#define ERRATA_THEAD_MAE 0 +#define ERRATA_THEAD_PMU 1 +#define ERRATA_THEAD_GHOSTWRITE 2 +#define ERRATA_THEAD_NUMBER 3 +#endif + +#endif --=20 2.40.1 From nobody Tue Oct 7 07:07:37 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 58C4D27BF85 for ; Sun, 13 Jul 2025 15:53:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752422027; cv=none; b=Tq8WKIRjxkOcbGEKnwRnyFaD8t20iQHZWL5c+oswvHOze3KX9UKRuLUi4LzTPiwcdcQfzuFmSRUne/pGipwGr1JJn9rBWoGL8bBxkYvpEW/Ox6ZVOWmgDFFe/LXQH1KUapZXLHxhuOtJwFfDGyKR++ykeE+Pd83DwgzF8vZkrg8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752422027; c=relaxed/simple; bh=9geRZ31fxaYw/yk4/HITajfRAlDS5YuBdqtQl+JU1fE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=kjni4rl6JUgb/EhIfh9/KuaLaH+JAhidy9p6wPMACi6d1LeT6W6PaKUP7n2qxTtMMpTmKTMcc/S73bxp6qBp1S1+UFrdp3SGEWqxNrZ6/qFIZiSHDz2J2Ir4RKcfzdK1C6fc7FLJZ1TLK8BldOh0s9f9SUbrzpbFe4qaeOMYl+M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=UyhhETjq; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="UyhhETjq" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 18671C4CEE3; Sun, 13 Jul 2025 15:53:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1752422025; bh=9geRZ31fxaYw/yk4/HITajfRAlDS5YuBdqtQl+JU1fE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=UyhhETjqL05f0Kjxwza8JvNubtgewIZl5kYXjs8nG/WIzfnx61E4ySkjF/25X8+lw 1TnUD8L0JWKiwpL1qWUgAlz4+Vdz/FhXU8iPAi0nETY9wBC5CG0ROSlb4J39kNnpEi +PxPin2NbhCZLCOePkFNXR/wnnLVvRgLa8dKkpFSLkRGZC4RvzznMAPjBZvHSlR7pQ BDUjsDQWn2uesG1/3JPxu6F0Atnc1vvaJ8oMzTP6RlVsm14I7TLEynqfG2qkqPt7Sm ljAN3B6xXo4Lmg97EbiXzJ7Gv763RgLa3KlSOn265EVAHmqg9awDOgVwIrSeP7SEtS U1DImWKoZFFvA== From: guoren@kernel.org To: palmer@dabbelt.com, guoren@kernel.org, conor@kernel.org, alexghiti@rivosinc.com, paul.walmsley@sifive.com, bjorn@rivosinc.com, eobras@redhat.com, corbet@lwn.net, peterlin@andestech.com, rabenda.cn@gmail.com Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Leonardo Bras Subject: [PATCH V2 2/2] riscv: errata: Add ERRATA_THEAD_WRITE_ONCE fixup Date: Sun, 13 Jul 2025 11:53:21 -0400 Message-Id: <20250713155321.2064856-3-guoren@kernel.org> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20250713155321.2064856-1-guoren@kernel.org> References: <20250713155321.2064856-1-guoren@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: "Guo Ren (Alibaba DAMO Academy)" The early version of XuanTie C910 core has a store merge buffer delay problem. The store merge buffer could improve the store queue performance by merging multi-store requests, but when there are not continued store requests, the prior single store request would be waiting in the store queue for a long time. That would cause significant problems for communication between multi-cores. This problem was found on sg2042 & th1520 platforms with the qspinlock lock torture test. So appending a fence w.o could immediately flush the store merge buffer and let other cores see the write result. This will apply the WRITE_ONCE errata to handle the non-standard behavior via appending a fence w.o instruction for WRITE_ONCE(). This problem is only observed on the sg2042 hardware platform by running the lock_torture test program for half an hour. The problem was not found in the user space application, because interrupt can break the livelock. Reviewed-by: Leonardo Bras Signed-off-by: Guo Ren (Alibaba DAMO Academy) Reviewed-by: Alexandre Ghiti Tested-by: Han Gao --- arch/riscv/Kconfig.errata | 17 ++++++++++ arch/riscv/errata/thead/errata.c | 20 ++++++++++++ arch/riscv/include/asm/errata_list_vendors.h | 3 +- arch/riscv/include/asm/rwonce.h | 34 ++++++++++++++++++++ include/asm-generic/rwonce.h | 2 ++ 5 files changed, 75 insertions(+), 1 deletion(-) create mode 100644 arch/riscv/include/asm/rwonce.h diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata index e318119d570d..d2c982ba5373 100644 --- a/arch/riscv/Kconfig.errata +++ b/arch/riscv/Kconfig.errata @@ -130,4 +130,21 @@ config ERRATA_THEAD_GHOSTWRITE =20 If you don't know what to do here, say "Y". =20 +config ERRATA_THEAD_WRITE_ONCE + bool "Apply T-Head WRITE_ONCE errata" + depends on ERRATA_THEAD + default y + help + The early version of T-Head C9xx cores of sg2042 & th1520 have a store + merge buffer delay problem. The store merge buffer could improve the + store queue performance by merging multi-store requests, but when there + are no continued store requests, the prior single store request would be + waiting in the store queue for a long time. That would cause signifi- + cant problems for communication between multi-cores. Appending a + fence w.o could immediately flush the store merge buffer and let other + cores see the write result. + + This will apply the WRITE_ONCE errata to handle the non-standard beh- + avior via appending a fence w.o instruction for WRITE_ONCE(). + endmenu # "CPU errata selection" diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/err= ata.c index 0b942183f708..fbe46f2fa8fb 100644 --- a/arch/riscv/errata/thead/errata.c +++ b/arch/riscv/errata/thead/errata.c @@ -168,6 +168,23 @@ static bool errata_probe_ghostwrite(unsigned int stage, return true; } =20 +static bool errata_probe_write_once(unsigned int stage, + unsigned long arch_id, unsigned long impid) +{ + if (!IS_ENABLED(CONFIG_ERRATA_THEAD_WRITE_ONCE)) + return false; + + /* target-c9xx cores report arch_id and impid as 0 */ + if (arch_id !=3D 0 || impid !=3D 0) + return false; + + if (stage =3D=3D RISCV_ALTERNATIVES_BOOT || + stage =3D=3D RISCV_ALTERNATIVES_MODULE) + return true; + + return false; +} + static u32 thead_errata_probe(unsigned int stage, unsigned long archid, unsigned long impid) { @@ -183,6 +200,9 @@ static u32 thead_errata_probe(unsigned int stage, =20 errata_probe_ghostwrite(stage, archid, impid); =20 + if (errata_probe_write_once(stage, archid, impid)) + cpu_req_errata |=3D BIT(ERRATA_THEAD_WRITE_ONCE); + return cpu_req_errata; } =20 diff --git a/arch/riscv/include/asm/errata_list_vendors.h b/arch/riscv/incl= ude/asm/errata_list_vendors.h index a37d1558f39f..a7473cb8874d 100644 --- a/arch/riscv/include/asm/errata_list_vendors.h +++ b/arch/riscv/include/asm/errata_list_vendors.h @@ -18,7 +18,8 @@ #define ERRATA_THEAD_MAE 0 #define ERRATA_THEAD_PMU 1 #define ERRATA_THEAD_GHOSTWRITE 2 -#define ERRATA_THEAD_NUMBER 3 +#define ERRATA_THEAD_WRITE_ONCE 3 +#define ERRATA_THEAD_NUMBER 4 #endif =20 #endif diff --git a/arch/riscv/include/asm/rwonce.h b/arch/riscv/include/asm/rwonc= e.h new file mode 100644 index 000000000000..081793d4d772 --- /dev/null +++ b/arch/riscv/include/asm/rwonce.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef __ASM_RWONCE_H +#define __ASM_RWONCE_H + +#include +#include +#include +#include + +#if defined(CONFIG_ERRATA_THEAD_WRITE_ONCE) && !defined(NO_ALTERNATIVE) + +#define write_once_fence() \ +do { \ + asm volatile(ALTERNATIVE( \ + "nop", \ + "fence w, o", \ + THEAD_VENDOR_ID, \ + ERRATA_THEAD_WRITE_ONCE, \ + CONFIG_ERRATA_THEAD_WRITE_ONCE) \ + : : : "memory"); \ +} while (0) + +#define __WRITE_ONCE(x, val) \ +do { \ + *(volatile typeof(x) *)&(x) =3D (val); \ + write_once_fence(); \ +} while (0) + +#endif /* defined(CONFIG_ERRATA_THEAD_WRITE_ONCE) && !defined(NO_ALTERNATI= VE) */ + +#include + +#endif /* __ASM_RWONCE_H */ diff --git a/include/asm-generic/rwonce.h b/include/asm-generic/rwonce.h index 52b969c7cef9..4e2d941f15a1 100644 --- a/include/asm-generic/rwonce.h +++ b/include/asm-generic/rwonce.h @@ -50,10 +50,12 @@ __READ_ONCE(x); \ }) =20 +#ifndef __WRITE_ONCE #define __WRITE_ONCE(x, val) \ do { \ *(volatile typeof(x) *)&(x) =3D (val); \ } while (0) +#endif =20 #define WRITE_ONCE(x, val) \ do { \ --=20 2.40.1