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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Jul 2025 05:08:09.4794 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 58bac77e-3405-4cf6-627a-08ddc1cb4296 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000971E5.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB7113 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Clear ECC error and counter registers during initialization/ probe to avoid reporting stale errors that may have occurred before EDAC registration. Key changes - Introduced a unified `get_ecc_state()` function that handles ECC state de= tection and register clearing for both Zynq and ZynqMP platforms. - Removed platform-specific `get_ecc_state` function pointers from the plat= form data structures. - Added a new `platform` enum field to `synps_platform_data` to identify the target hardware platform. Signed-off-by: Shubhrajyoti Datta --- Changes in v2: - Update the commit message - Add the zynq reset changes - remove the function pointer - Use a plat field instead of the quirk drivers/edac/synopsys_edac.c | 96 +++++++++++++++++------------------- 1 file changed, 45 insertions(+), 51 deletions(-) diff --git a/drivers/edac/synopsys_edac.c b/drivers/edac/synopsys_edac.c index 5ed32a3299c4..a0d101aa15f7 100644 --- a/drivers/edac/synopsys_edac.c +++ b/drivers/edac/synopsys_edac.c @@ -332,20 +332,26 @@ struct synps_edac_priv { #endif }; =20 +enum synps_platform_type { + ZYNQ, + ZYNQMP, + SYNPS, +}; + /** * struct synps_platform_data - synps platform data structure. + * @platform: Identifies the target hardware platform * @get_error_info: Get EDAC error info. * @get_mtype: Get mtype. * @get_dtype: Get dtype. - * @get_ecc_state: Get ECC state. * @get_mem_info: Get EDAC memory info * @quirks: To differentiate IPs. */ struct synps_platform_data { + enum synps_platform_type platform; int (*get_error_info)(struct synps_edac_priv *priv); enum mem_type (*get_mtype)(const void __iomem *base); enum dev_type (*get_dtype)(const void __iomem *base); - bool (*get_ecc_state)(void __iomem *base); #ifdef CONFIG_EDAC_DEBUG u64 (*get_mem_info)(struct synps_edac_priv *priv); #endif @@ -720,51 +726,38 @@ static enum dev_type zynqmp_get_dtype(const void __io= mem *base) return dt; } =20 -/** - * zynq_get_ecc_state - Return the controller ECC enable/disable status. - * @base: DDR memory controller base address. - * - * Get the ECC enable/disable status of the controller. - * - * Return: true if enabled, otherwise false. - */ -static bool zynq_get_ecc_state(void __iomem *base) +static bool get_ecc_state(struct synps_edac_priv *priv) { + u32 ecctype, clearval; enum dev_type dt; - u32 ecctype; - - dt =3D zynq_get_dtype(base); - if (dt =3D=3D DEV_UNKNOWN) - return false; =20 - ecctype =3D readl(base + SCRUB_OFST) & SCRUB_MODE_MASK; - if ((ecctype =3D=3D SCRUB_MODE_SECDED) && (dt =3D=3D DEV_X2)) - return true; - - return false; -} - -/** - * zynqmp_get_ecc_state - Return the controller ECC enable/disable status. - * @base: DDR memory controller base address. - * - * Get the ECC enable/disable status for the controller. - * - * Return: a ECC status boolean i.e true/false - enabled/disabled. - */ -static bool zynqmp_get_ecc_state(void __iomem *base) -{ - enum dev_type dt; - u32 ecctype; - - dt =3D zynqmp_get_dtype(base); - if (dt =3D=3D DEV_UNKNOWN) - return false; - - ecctype =3D readl(base + ECC_CFG0_OFST) & SCRUB_MODE_MASK; - if ((ecctype =3D=3D SCRUB_MODE_SECDED) && - ((dt =3D=3D DEV_X2) || (dt =3D=3D DEV_X4) || (dt =3D=3D DEV_X8))) - return true; + if (priv->p_data->platform =3D=3D ZYNQ) { + dt =3D zynq_get_dtype(priv->baseaddr); + if (dt =3D=3D DEV_UNKNOWN) + return false; + + ecctype =3D readl(priv->baseaddr + SCRUB_OFST) & SCRUB_MODE_MASK; + if (ecctype =3D=3D SCRUB_MODE_SECDED && dt =3D=3D DEV_X2) { + clearval =3D ECC_CTRL_CLR_CE_ERR | ECC_CTRL_CLR_UE_ERR; + writel(clearval, priv->baseaddr + ECC_CTRL_OFST); + writel(0x0, priv->baseaddr + ECC_CTRL_OFST); + return true; + } + } else { + dt =3D zynqmp_get_dtype(priv->baseaddr); + if (dt =3D=3D DEV_UNKNOWN) + return false; + + ecctype =3D readl(priv->baseaddr + ECC_CFG0_OFST) & SCRUB_MODE_MASK; + if (ecctype =3D=3D SCRUB_MODE_SECDED && + (dt =3D=3D DEV_X2 || dt =3D=3D DEV_X4 || dt =3D=3D DEV_X8)) { + clearval =3D readl(priv->baseaddr + ECC_CLR_OFST) | + ECC_CTRL_CLR_CE_ERR | ECC_CTRL_CLR_CE_ERRCNT | + ECC_CTRL_CLR_UE_ERR | ECC_CTRL_CLR_UE_ERRCNT; + writel(clearval, priv->baseaddr + ECC_CLR_OFST); + return true; + } + } =20 return false; } @@ -934,18 +927,18 @@ static int setup_irq(struct mem_ctl_info *mci, } =20 static const struct synps_platform_data zynq_edac_def =3D { + .platform =3D ZYNQ, .get_error_info =3D zynq_get_error_info, .get_mtype =3D zynq_get_mtype, .get_dtype =3D zynq_get_dtype, - .get_ecc_state =3D zynq_get_ecc_state, .quirks =3D 0, }; =20 static const struct synps_platform_data zynqmp_edac_def =3D { + .platform =3D ZYNQMP, .get_error_info =3D zynqmp_get_error_info, .get_mtype =3D zynqmp_get_mtype, .get_dtype =3D zynqmp_get_dtype, - .get_ecc_state =3D zynqmp_get_ecc_state, #ifdef CONFIG_EDAC_DEBUG .get_mem_info =3D zynqmp_get_mem_info, #endif @@ -957,10 +950,10 @@ static const struct synps_platform_data zynqmp_edac_d= ef =3D { }; =20 static const struct synps_platform_data synopsys_edac_def =3D { + .platform =3D SYNPS, .get_error_info =3D zynqmp_get_error_info, .get_mtype =3D zynqmp_get_mtype, .get_dtype =3D zynqmp_get_dtype, - .get_ecc_state =3D zynqmp_get_ecc_state, .quirks =3D (DDR_ECC_INTR_SUPPORT | DDR_ECC_INTR_SELF_CLEAR #ifdef CONFIG_EDAC_DEBUG | DDR_ECC_DATA_POISON_SUPPORT @@ -1390,10 +1383,6 @@ static int mc_probe(struct platform_device *pdev) if (!p_data) return -ENODEV; =20 - if (!p_data->get_ecc_state(baseaddr)) { - edac_printk(KERN_INFO, EDAC_MC, "ECC not enabled\n"); - return -ENXIO; - } =20 layers[0].type =3D EDAC_MC_LAYER_CHIP_SELECT; layers[0].size =3D SYNPS_EDAC_NR_CSROWS; @@ -1413,6 +1402,11 @@ static int mc_probe(struct platform_device *pdev) priv =3D mci->pvt_info; priv->baseaddr =3D baseaddr; priv->p_data =3D p_data; + if (!get_ecc_state(priv)) { + edac_printk(KERN_INFO, EDAC_MC, "ECC not enabled\n"); + goto free_edac_mc; + } + spin_lock_init(&priv->reglock); =20 mc_init(mci, pdev); --=20 2.17.1