From nobody Tue Oct 7 07:06:06 2025 Received: from mail-wr1-f42.google.com (mail-wr1-f42.google.com [209.85.221.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2B05F1EA7E1 for ; Sun, 13 Jul 2025 08:06:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.42 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752393967; cv=none; b=nNwuqa2r/twnfxLHBCuWmHFGG+2qDkaxa9RvdxE9HB1bxZgFsKtT5zc4KOQl4dcbflJIgZlOIDVCd+rmmjm7qEG5d5ey7wDzLTMdvn+IkdWabNauQRIuLuMlQHk7Ahei8urjrpiUZ9q9Tek1XSC0BKFgPzOJBaaXOO6cb0JqbB4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752393967; c=relaxed/simple; bh=VI60lC4ZmfORZyuxHBRWFEsQsFQCradJNwP6TkMJAbg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=eFfZ8G55bAGF5ADVBp9fTdVHP4xkXB6KnD62uxjj1aWhYNQeenVWltl9YpP3xgekC+cCB7T5fWm9gu2QHrYAkJzd+T0vglnVqnkIGbcekmPa+uRzFClMP02h7l7e4mWTilUw7jENPuZm1tuJrzmLneRj/x8Wu1EefsKHEBnQ7Ao= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=fairphone.com; spf=pass smtp.mailfrom=fairphone.com; dkim=pass (2048-bit key) header.d=fairphone.com header.i=@fairphone.com header.b=fVzT5wL9; arc=none smtp.client-ip=209.85.221.42 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=fairphone.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=fairphone.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=fairphone.com header.i=@fairphone.com header.b="fVzT5wL9" Received: by mail-wr1-f42.google.com with SMTP id ffacd0b85a97d-3a57ae5cb17so1952621f8f.0 for ; Sun, 13 Jul 2025 01:06:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fairphone.com; s=fair; t=1752393963; x=1752998763; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=te4MJTBpVgJuhtRjxJH2s+xCNlwZ781R0MdiUCdRknI=; b=fVzT5wL9nacXW/zSdVnPdDbwPO56ZOrrEUVOpNbIAb1f7W1u2/y2rWwm8bEANvkoxp ozKpvIlwiIZ3WDVOOaZftzntoOQcYVO+BxYocNbPHLzFNo87Z7baIwvuLutQ29cq1CdI xZE/PnHpaqHl4HJZyY99lA4aO46wIJyRAvO5X7okujkVvV7TeZOGZsn2irG1Bkr7jJ2I FwvM+PpZiuHXcZ7rv/XYmi/2aI0xd5ekluMPu+EUSKl6sM+3E7+LpRJ9YM9MG914dduD 0P3QH25ryNPcyxK7NyZOOQq0mWLywPEMIG0CwEYP4SgPSe6VKzQ0gc6TghnP61zNSw6Z zWqw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1752393963; x=1752998763; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=te4MJTBpVgJuhtRjxJH2s+xCNlwZ781R0MdiUCdRknI=; b=Z3A+eNCpsHGj6ObKPRO3KirV8rJXEAb6GRZPs5F2GBE9nhvfV3zCe8caEWkHD51bdf lF4ETiwyosiw16N98CFuIHZ5vyhasDzmMZdo8I/DAGs5s5Vjt72nm52Cllm2ewBLcrHL HZcz0LBo09KhPSu3Bl8uPEq2Lrlx9HrysfKJTcEXfdef9/Y1uPy9oA9gNxJrR03+Xiy0 hRDEjKyf1/t98qvLFWjFxRuCMMyzo1NahrlMKjns0FfSVSN2dIZ5g4bDF2GNis1i0KDE t1fuy7vS6UjzdAlAVuaHotWUsa8DCwFWV0xQepbi6O+3kh9eq4+vdbHOFI78bGJDiWqm R3fg== X-Forwarded-Encrypted: i=1; AJvYcCWUJ7Fwu2E4tSyc8+mNgj1vpRgq+XpotufkWjevJhOpzORu6i1AP4DyoRu3meXFzkASt/0beUM/ZulzK6I=@vger.kernel.org X-Gm-Message-State: AOJu0Yx4HanUhe+QWpU3tcb+JpdwDjlzEFPLhiM24OTXKx8hUeWpwtoC F5n+i/91fnJ882Ulhrpp4sja9foeQGjky0E2zhc5kjPFe2w8xtVcsYynMU/LdJ7tYyo= X-Gm-Gg: ASbGncueOklHDEJwVtdteJCBHAtsN024KXgcMiCwHYbQjmCGz3dyAZGJgxzGOEux9Ue 45+URDcjMMPeKVmb+lpO3K8a6n+tUuOJf9O5iCWh+xFCS9AWkHyhmlLTgmMuVBLKpGhCGL+W83K Kgxs6riuNJIV1hlIttZLdTsk06RjH4Mr9zaUkchphbhUxx2B5Ea9lPzYzYmg59SBraD5hdgY0aQ 3nrL9VkrsKKmso9AyyHjZHwt/M4+6xX0KNvhoqvYpGAnxqK0rHFjs4F32NwTeEUeLDB6dgZXI8o ikdsntyk5jyBqXMs/fE46gb1PBB2qFp5biYqSaP80zH+awatvHU2rNkKOSJiiLBBdAZQyctfdOE DFpd+ymg7GjPzW8CsTb4ra98ymRJAzN7J0dhCgYshSHwYiZA= X-Google-Smtp-Source: AGHT+IG58Q0+c/JdRpYP9OwThz11aodR+FjCZWHpjNmU/o1HqomzxkC9Hl2w1xFzYfqgnbsp0pIfUg== X-Received: by 2002:a5d:5f41:0:b0:3aa:c9a8:a387 with SMTP id ffacd0b85a97d-3b5f181bf12mr8730107f8f.0.1752393963493; Sun, 13 Jul 2025 01:06:03 -0700 (PDT) Received: from [192.168.224.50] ([213.208.155.167]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3b5e8dc22a8sm9386608f8f.34.2025.07.13.01.05.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Jul 2025 01:06:03 -0700 (PDT) From: Luca Weiss Date: Sun, 13 Jul 2025 10:05:23 +0200 Subject: [PATCH v2 01/15] dt-bindings: arm-smmu: document the support on Milos Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250713-sm7635-fp6-initial-v2-1-e8f9a789505b@fairphone.com> References: <20250713-sm7635-fp6-initial-v2-0-e8f9a789505b@fairphone.com> In-Reply-To: <20250713-sm7635-fp6-initial-v2-0-e8f9a789505b@fairphone.com> To: Will Deacon , Robin Murphy , Joerg Roedel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , "Rafael J. Wysocki" , Viresh Kumar , Manivannan Sadhasivam , Herbert Xu , "David S. Miller" , Vinod Koul , Bjorn Andersson , Konrad Dybcio , Robert Marko , Das Srinagesh , Thomas Gleixner , Jassi Brar , Amit Kucheria , Thara Gopinath , Daniel Lezcano , Zhang Rui , Lukasz Luba , Ulf Hansson Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-crypto@vger.kernel.org, dmaengine@vger.kernel.org, linux-mmc@vger.kernel.org, Luca Weiss X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1752393945; l=1456; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=VI60lC4ZmfORZyuxHBRWFEsQsFQCradJNwP6TkMJAbg=; b=ysFcsREoBvX5mgay6H6zBC7kn964wfsE1peB4S1deXzOSQgOF/awLFfvR6VFGhwUAq6oh+c+L jGE9XkkTsEYCtwhnmfdvMrCBbHaWxNcEmIJjlZVGZSlmOWt5qi/15fU X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= Add compatible for smmu representing support on the Milos SoC. Signed-off-by: Luca Weiss Acked-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Docume= ntation/devicetree/bindings/iommu/arm,smmu.yaml index 7b9d5507d6ccd6b845a57eeae59fe80ba75cc652..66d5a5ff78fa5dbb86db72db754= c23b8cc8f188a 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml @@ -35,6 +35,7 @@ properties: - description: Qcom SoCs implementing "qcom,smmu-500" and "arm,mmu-5= 00" items: - enum: + - qcom,milos-smmu-500 - qcom,qcm2290-smmu-500 - qcom,qcs615-smmu-500 - qcom,qcs8300-smmu-500 @@ -88,6 +89,7 @@ properties: - description: Qcom Adreno GPUs implementing "qcom,smmu-500" and "ar= m,mmu-500" items: - enum: + - qcom,milos-smmu-500 - qcom,qcm2290-smmu-500 - qcom,qcs615-smmu-500 - qcom,qcs8300-smmu-500 @@ -534,6 +536,7 @@ allOf: compatible: items: - enum: + - qcom,milos-smmu-500 - qcom,sar2130p-smmu-500 - qcom,sm8550-smmu-500 - qcom,sm8650-smmu-500 --=20 2.50.1 From nobody Tue Oct 7 07:06:06 2025 Received: from mail-wr1-f47.google.com (mail-wr1-f47.google.com [209.85.221.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A31B31E51EB for ; Sun, 13 Jul 2025 08:06:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752393976; cv=none; b=eJ8a4gGi/MYm+yOFSBeR8lC3etYD41T7jFbSyHF5tfCFtkGfTDg9i/+H4AiMvNmepl5m1hdp3g1LcNSiTvD5L/Otf6NqG//GYJRKxPgRYjxefC6rW5rm4SIAI0QTdPM5WoG8Qzt1D/RQuwxWXhoNU01hiOSNnEd5PTATKHm/vE0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752393976; c=relaxed/simple; bh=nbSwp5ROysMSTLKLxq6Pg7q3VCWJ3MFGpodgkXirdrk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=bHYUcFfiXvhkt2uWoBRA6rFLA86pv3BL7CGMyNTeUn8oRKSLH7QUb5ivD2SEBlmLlxxDnefsBDdQn6tJZ1Gr8aCRwUlvMvx4UqZcNa4xbY5A3RXOC2O8fs5ZUDn6zBfIphNXcHzvN/3g6NBBEUymKk/G+TaOIQ2eVa0i70yDitA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=fairphone.com; spf=pass smtp.mailfrom=fairphone.com; dkim=pass (2048-bit key) header.d=fairphone.com header.i=@fairphone.com header.b=dNQVvhcd; arc=none smtp.client-ip=209.85.221.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=fairphone.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=fairphone.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=fairphone.com header.i=@fairphone.com header.b="dNQVvhcd" Received: by mail-wr1-f47.google.com with SMTP id ffacd0b85a97d-3a548a73ff2so2929764f8f.0 for ; Sun, 13 Jul 2025 01:06:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fairphone.com; s=fair; t=1752393973; x=1752998773; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=qjkVBqGocvldr3+5pDfPNG/mAD5wl5azsqsATuuDVzU=; b=dNQVvhcdTYxNi3jJkFCbONfvWJSR48ZWbzFhlfnHutB0yhV4nnuzWie5e9/sSx5gO4 yRG98lDnyRgOVGpWyF49y0eafQ8YTyw8E40wm9stpMKN8weoLvkpKXqpFz7H8Oazydx2 DYFaBGHuk+Vr71FCru6Zp0xdhW38gA9jxQT2j/Frer0BceEoAhMs+GWZEcOyWLsHLUfJ 4dpCPhiTvE8JS7IsNDu6rEkJc3INlzYLHte04NsgINqP4pYa1y5yZkC1q1UZS7ctiLEb efbK1ULXRMtX1b5pnvZLqv3tArnOhhIVhxUSFkvUFfZdGPrZ6cAZ7wlA6eimmirKibc5 ZDsw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1752393973; x=1752998773; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qjkVBqGocvldr3+5pDfPNG/mAD5wl5azsqsATuuDVzU=; b=lNQA/WbBv8PmXIRtxX0h8QXYToUQAGsnpleG8+kfhbqXaphZvrWVnRz3+wgjm3/NBU x6LRu4k0cKPdkgEfeNz2gFtBc/F+z8n4pIM4LiDkzxcla3DHphurQA26bpcUf3opUYmh wUG2pA05/B7JgMZP5HgTpkFYMO8AB+j7lYyrdbreROD3hhA8sqxx15yaG8uXsCjUzgLv VVzEqbu9NzHGahbQY8veuN7yW8cXqwzzgCfoAFO9qtLZUdP/cx+/DAqXtkNYMBfG1b8t I4HT7Zxc+cQfkkUK9lETlwAbU0+Oq2xVwvCUWWXRSkqSKfpUh1lG/iyG+fA5a6NfuoCm NaNA== X-Forwarded-Encrypted: i=1; AJvYcCWw/6rgPwfOBf0eAVPOXgQ2tm47u5YSzifkx4kzOUTT9/4V3+KIIp1VBSG5RkxhHV3fv+Z6DNb54LgTlz0=@vger.kernel.org X-Gm-Message-State: AOJu0YxtH98giYIewhqITOF/3SM+qqcacPOxrll+iO/mUTLPClXabWOx QkIAF/ZVWL3HGXFEm8dCBpRVBiGnFYvkuGzS4zftmyBprGRSzBzd6zp+5ofoVuTn8gM= X-Gm-Gg: ASbGnctusejiLjOZTuAqj8nqQXRQvwlDZkF/2O/LxPkY1pPGYzPHecBdpjeuEt2mhLB s61WYy2n9IVEM7CDvDnzDU2pnKvwlDnKDXH/IpJLr7Gdo/tkyybjAdsVxWRA4l4CQlgsZhcxTUA rV9eW26c6yr6jG4YuU3SlQJ+NWBfFncmjqy7XlWLMOpBndFBtx3lyOadsNRnn+wlVZUGk7Ye8OE lZ8aADKfAY4kM0gClzZj/gWjG4XRz9lQX+132HGYo4LV5VDaveBcTEtb8w6srp8s2n81q2JGEPs 3Tk4oJ5o8fYHO46akIci5RL5bVL7V1Xzsz9cWWaj0IuGPVpMHVAd19e76U7Nv/5tw3T2n88af+C 3eEn4l5ysY8qKiyTO6j6HtOCqooCby14gc6YL X-Google-Smtp-Source: AGHT+IE7aiBW0y1UJWTkFw2jo19wh2kKOFls92CeELkcuzfmOFh/b4a0X3Mbc9B6RVDds+HgM7Z+rg== X-Received: by 2002:a05:6000:4613:b0:3a5:2923:8006 with SMTP id ffacd0b85a97d-3b5f186ed15mr7662034f8f.25.1752393973014; Sun, 13 Jul 2025 01:06:13 -0700 (PDT) Received: from [192.168.224.50] ([213.208.155.167]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3b5e8dc22a8sm9386608f8f.34.2025.07.13.01.06.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Jul 2025 01:06:12 -0700 (PDT) From: Luca Weiss Date: Sun, 13 Jul 2025 10:05:24 +0200 Subject: [PATCH v2 02/15] dt-bindings: cpufreq: qcom-hw: document Milos CPUFREQ Hardware Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250713-sm7635-fp6-initial-v2-2-e8f9a789505b@fairphone.com> References: <20250713-sm7635-fp6-initial-v2-0-e8f9a789505b@fairphone.com> In-Reply-To: <20250713-sm7635-fp6-initial-v2-0-e8f9a789505b@fairphone.com> To: Will Deacon , Robin Murphy , Joerg Roedel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , "Rafael J. Wysocki" , Viresh Kumar , Manivannan Sadhasivam , Herbert Xu , "David S. Miller" , Vinod Koul , Bjorn Andersson , Konrad Dybcio , Robert Marko , Das Srinagesh , Thomas Gleixner , Jassi Brar , Amit Kucheria , Thara Gopinath , Daniel Lezcano , Zhang Rui , Lukasz Luba , Ulf Hansson Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-crypto@vger.kernel.org, dmaengine@vger.kernel.org, linux-mmc@vger.kernel.org, Luca Weiss X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1752393945; l=1165; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=nbSwp5ROysMSTLKLxq6Pg7q3VCWJ3MFGpodgkXirdrk=; b=URo7Ywj7eQLjWeGSKpTNmv79uc7iAPWio/PyLw17wxDECtuAiz2Bu3PfwHvwHO3pZ1RhCb5ag VyL+DFxfUJDDy0DR7snG/iq810fQKBhCUA6IIAt4osJpIsLJpCqxh/T X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= Document the CPUFREQ Hardware on the Milos SoC. Signed-off-by: Luca Weiss Acked-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml= b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml index e0242bed33420a39b8a8cff4229ba9eee994ca30..4fcadba87fbb90f960201aa0763= f1a22c0f0f9b5 100644 --- a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml @@ -34,6 +34,7 @@ properties: - description: v2 of CPUFREQ HW (EPSS) items: - enum: + - qcom,milos-cpufreq-epss - qcom,qcs8300-cpufreq-epss - qcom,qdu1000-cpufreq-epss - qcom,sa8255p-cpufreq-epss @@ -167,6 +168,7 @@ allOf: compatible: contains: enum: + - qcom,milos-cpufreq-epss - qcom,qcs8300-cpufreq-epss - qcom,sc7280-cpufreq-epss - qcom,sm8250-cpufreq-epss --=20 2.50.1 From nobody Tue Oct 7 07:06:06 2025 Received: from mail-wm1-f50.google.com (mail-wm1-f50.google.com [209.85.128.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1A7381E3DD7 for ; Sun, 13 Jul 2025 08:06:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.50 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752393987; cv=none; b=A5DBq4F31E9oMxtph2M62mJ+bsCdBRQ1+oVQ2qxIFWmCIqh1FFX5oH5YyZ80MfNBv4NlkNNz0YlXZWGqrKkiUVHM0ZQZNlf8tS316H9uZ7DN+62sSwDXyiMrhAfKgRC/yTaSocjBGTNcuKDmLIh9BrWaQYlrhWa971PWolk2CZc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752393987; c=relaxed/simple; bh=lXJt/yDsoHDSuPe8QmNNkzF3KEBLxNVR5QCRJEM7U6s=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=kmIoZUsg3kBV4ft+nu2ChkaAReYR0661U4mIKeodNjf/iKWcREv7dkXkrYc6m5hH1W76FduP9bYmCPE6ZjjHCAWJNTjU9tUE7SLIRrMJnLxGWgx56985yJy42hFLlN7rE1IbPDoFq7cDmJzDtmgynzH4GlRR83KelQ1NrSuMfkE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=fairphone.com; spf=pass smtp.mailfrom=fairphone.com; dkim=pass (2048-bit key) header.d=fairphone.com header.i=@fairphone.com header.b=KAjsyGaq; arc=none smtp.client-ip=209.85.128.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=fairphone.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=fairphone.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=fairphone.com header.i=@fairphone.com header.b="KAjsyGaq" Received: by mail-wm1-f50.google.com with SMTP id 5b1f17b1804b1-4538bc52a8dso23335615e9.2 for ; Sun, 13 Jul 2025 01:06:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fairphone.com; s=fair; t=1752393983; x=1752998783; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=Q3MxjLEtpRVyTZFb++atMk5EZAHm1SNpE6rDNgKP3WM=; b=KAjsyGaqy53gMzniftyt3noWtbYuECU6ma8NVW+SKilgvESX+YXzSkuG+wogG3DutB LfXLV5bstJbPDK1gpiu/mlGvIkhWHcbOeGQoct6jnaDl34mE5OjwaBzXIWiB3ijFhLRG huAIRoVaxscaMc99OXH9ytq4Jm51Zab4rZm2OUkr/kfEIh6yico8aKiDDTPv4e5XafPf PY0M9Zg58mWPOsZeBCJUKfgqDx5u5n+LpunXEgKWDV48egVYIx+9gT85/k8NeT5k3Jao gSmEuhXSr65KhWo8cszu1diFaHZyRGfMCWGeUBVlo2SE+9kJl4y5Y7TQnO00YZrFYGzq srMA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1752393983; x=1752998783; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Q3MxjLEtpRVyTZFb++atMk5EZAHm1SNpE6rDNgKP3WM=; b=rgb9s5VSjeHkn9aswR62+M6w5iiCIuwv5v4H0np7fffSnhEy+7OQdr84wmZlXld3h9 21kbidghSgOBBwUS5HyO9ARSFcHc/+nbgLOwzavGDNkzotNh9pqUHVwpCu2tth8yWfs5 bOt1wpxRDQWCh3ehX/Hp1oNWDVQzpBcVxBjBeU5LpiOjyWeT9gB5KPvHic3hMbU3kw+K prdTuYFTiIjg7hHw1UUA2XGs+gUug3JTMbnucz54oN8B19an9X8kvfykwiOTIaThuely yuDAfz35qHWuPIrGKYuwBn0ocYk/JQBZtDSgfWH9Hzh67510T1EzqpL1lGyGWeXbhhX+ Djsg== X-Forwarded-Encrypted: i=1; AJvYcCUcrqL0avRkXk0qrXqG2cO0eTI/120LmeYFAH6jd4gybJQ43eLhzORAc7DDfr/EKv1ocfQ6GRcHd3GZ8G4=@vger.kernel.org X-Gm-Message-State: AOJu0YynRr9/J7fcD1uCnkWQpnAjgVrRa46x2oJ0RBJ2z/UjSaEM5v5E +QH2AmjSZa/iQDptcGfygdrxJ7AtGQH4XXk49P5WOJ7aO6v7YL+BFE1cS1YZ4nzhVNKiXACMwGV HTALg X-Gm-Gg: ASbGncvNugfvAo4CLtC0N2aIpLYqQdnyceOqjIcx3pP3FMIX18vqkVtXHlpHHXatHRf wPSotKTuTSyQXCC76+jbll0ruJ2y6iivfPZ2XCQPqxOPGNoABhpl2g8q2SLjCnvdhUqz9V3x3Qc F/JAt77/gUKn1rWWJ4GcoKbWSLhcWEzgXO23H5vjpiU9cHtlxU6MUvDrrUnM6gPp1EG46Zm27xO hJxQQRNNZqOn+nqZQX9MLRVNY86XyC+jlGbq48M1Avrd3gmFDsu+slKNAlzXSHMmF4MKqUPy4OB QQBMANZb2cZnsVUxs+YIuOSsNrA/X825upkIDujlA4c97h9HxLWq6k8U5Qpfv40lw7GNbtTPS55 xBUbDaQC5yl79ADY8yqa+hN3EmbZAxMFMpQoUJOIwGiolsZw= X-Google-Smtp-Source: AGHT+IF2dijl2kk5jegjtYU+p2rAjAUxOPkElW1UrGDWDO80C/PI+gSKcgMJoxorFBd7cfrm8u/VBQ== X-Received: by 2002:a5d:6a49:0:b0:3a5:2848:2e78 with SMTP id ffacd0b85a97d-3b5f18ceba8mr7079826f8f.28.1752393983475; Sun, 13 Jul 2025 01:06:23 -0700 (PDT) Received: from [192.168.224.50] ([213.208.155.167]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3b5e8dc22a8sm9386608f8f.34.2025.07.13.01.06.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Jul 2025 01:06:23 -0700 (PDT) From: Luca Weiss Date: Sun, 13 Jul 2025 10:05:25 +0200 Subject: [PATCH v2 03/15] dt-bindings: crypto: qcom,prng: document Milos Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250713-sm7635-fp6-initial-v2-3-e8f9a789505b@fairphone.com> References: <20250713-sm7635-fp6-initial-v2-0-e8f9a789505b@fairphone.com> In-Reply-To: <20250713-sm7635-fp6-initial-v2-0-e8f9a789505b@fairphone.com> To: Will Deacon , Robin Murphy , Joerg Roedel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , "Rafael J. Wysocki" , Viresh Kumar , Manivannan Sadhasivam , Herbert Xu , "David S. Miller" , Vinod Koul , Bjorn Andersson , Konrad Dybcio , Robert Marko , Das Srinagesh , Thomas Gleixner , Jassi Brar , Amit Kucheria , Thara Gopinath , Daniel Lezcano , Zhang Rui , Lukasz Luba , Ulf Hansson Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-crypto@vger.kernel.org, dmaengine@vger.kernel.org, linux-mmc@vger.kernel.org, Luca Weiss X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1752393945; l=875; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=lXJt/yDsoHDSuPe8QmNNkzF3KEBLxNVR5QCRJEM7U6s=; b=YWlNKu1yk/YAFD8w90VWlOFTNCiHXfhuYzMgW1x9mK56voio6ksNRmFDk/XDI+kjQDc4mizBK mmfj6LeJyvMD7UovUB4bVNyGfJtrvgMzTuaEsoMvHBWmXosueoYs69L X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= Document Milos SoC compatible for the True Random Number Generator. Signed-off-by: Luca Weiss Acked-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/crypto/qcom,prng.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/crypto/qcom,prng.yaml b/Docu= mentation/devicetree/bindings/crypto/qcom,prng.yaml index ed7e16bd11d33c16d0adf02c38419dbaee87ac48..0fdef054a1a30c363e0d9951835= 1fb18124904f0 100644 --- a/Documentation/devicetree/bindings/crypto/qcom,prng.yaml +++ b/Documentation/devicetree/bindings/crypto/qcom,prng.yaml @@ -20,6 +20,7 @@ properties: - qcom,ipq5332-trng - qcom,ipq5424-trng - qcom,ipq9574-trng + - qcom,milos-trng - qcom,qcs615-trng - qcom,qcs8300-trng - qcom,sa8255p-trng --=20 2.50.1 From nobody Tue Oct 7 07:06:06 2025 Received: from mail-wr1-f49.google.com (mail-wr1-f49.google.com [209.85.221.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B68AB1F03D5 for ; Sun, 13 Jul 2025 08:06:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.49 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752393999; cv=none; b=HRxezPziUW1aH4wg/rpdIOZr67v1MBjB9PHenGfvrGh8oNO0syRsqvUCX4H4AhXkFVjjVoGdmTsPmecJZNVmiuSAz2DmS0n11oVEjyzAgf0aW8LqU7saf3eisXtrmwKfJtRlOTrYhISyXrPzs0YVR5I/ZgJZ6abcCKCO5AiszAw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752393999; c=relaxed/simple; bh=tMLsPA0quQvuGmIREPbj4TjYGghQCOz1jliVkGJZk/w=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=WbPjgIpYXrMKd0bPlDJFEbuEgZEAAS5I0VcJHn4Xt9nnZyUiDS1vLJnC8Pwsw1fd8sCe0jZGsX7nLeSJ+RisejGJwoi7IK1ejYLv4uoIlIR5i8Q8sVSm0KSMfjg6Z9gH36yswnpreDTrY1oFQ5H+RfJgvYyngfz3Lc7R39jjbbw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=fairphone.com; spf=pass smtp.mailfrom=fairphone.com; dkim=pass (2048-bit key) header.d=fairphone.com header.i=@fairphone.com header.b=cSPh43rn; arc=none smtp.client-ip=209.85.221.49 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=fairphone.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=fairphone.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=fairphone.com header.i=@fairphone.com header.b="cSPh43rn" Received: by mail-wr1-f49.google.com with SMTP id ffacd0b85a97d-3a6cdc27438so2884665f8f.2 for ; Sun, 13 Jul 2025 01:06:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fairphone.com; s=fair; t=1752393994; x=1752998794; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=AdkfO4ocsxOWvyOKIsWLa8yR7W3TV/OTXW4E8s0id9w=; b=cSPh43rnl0OpMF1Cv27rL2MSxBiF+tJZgM9IST5JZv4D5UCoUIq9ut1J0+BV/WkTYq SVrSr1P6hIkOTOyz9clA0Al7oipo3WoBQcH9XBEDt1MZwKjbM6w6708uifLQ9dSPWK6F d8oaCjXHel42nHbtT0Jo8cloNJ7rVRVHxfiKZKt1XJePJxfGx/+oWNgPpLxEptuZlqKg je9ogFrLDCLNLQ+sKUBaXAeuV6R0sYGmrzsJA6IRalmR8XjExDKboqGuo8JLqP7SsiHb ZorKtcD2d/Yb7sg2QERWnH9bcftRZqUA4FuNvQHdv1QDXOm3Zcd/SP9FeUEiviBCzAdH zPWQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1752393994; x=1752998794; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=AdkfO4ocsxOWvyOKIsWLa8yR7W3TV/OTXW4E8s0id9w=; b=Wa8fb9iStQiLjxLl+KNysQiloT2wOnca3g0fmBb9hJmHwzK+3BbOq+lJODmcNSu0KK wIMCly+MKnAeYqdLH9lAsew4YCMuxn52Oixh5CzLBgGKYuFbNrYNNUaA0x2/a2vAlJ7Y LNuGRhGVa1zhNBK/5Hd6AIcqEL/w+Df2YonJQhtn3HfjVyQsTI8B2L6fh0k5Iwnq5CJD XitJspcExRUACVf87z2pWdSTzAVKzQUIGz0fGhswlHNkaOlAmuBPAYQEvqZfMriO8zEo s/n8VHayn7PH/nErQb+IkleF0iQmw9J49Wr7q5Ubs9Kkl7ppwr0CbE56WIApeumEuiV3 VS1A== X-Forwarded-Encrypted: i=1; AJvYcCWJq4Nbn/ZWLSFZejMQoAfPYArvAAtaDNS/Fj+WNRTFhyUNWmCb3UD9VxCPE0di5WDRmY7/P8komJiAvR4=@vger.kernel.org X-Gm-Message-State: AOJu0YzphcGvERz/PA/mg9pkMntNycZkBJ8kCMSkQeJk2HKyJMEqLRoF wi98GAhDZiZie3u/0055a8vvCkCFdFVde3RMUgbDQa8ZN9H5hYkwQM/IyDwJkYCMQts= X-Gm-Gg: ASbGncsncrjcLdJOljszEHQ8S53eL2IAqdRxINFCBe4FEOGan7jTe5gtP6KW9jsysj0 r2h3+HI9ZS8p8d3YWaqZ9cYmoQTCWAqT6NXklp19xocQOiMlRGhLVnHo3VflCOndTwuhO3986rN DYudQN7NKR/J9dmhSq6VWM4xcJQuXjYULPajquj3PbWNy/p1ZJMt+kuDL+87BnDZ6C6zNIyAjgC EMZ0KG6/IxIA4h7vT+pgSLO9N3i4D8SszH4SnZEcasWahTldNlXekUYgaiFNh7d01SgLRQVvqdL 63g9a1+/z81hTmMgZ5KMFM+bh2nIxYMg+kpdA1G41+nf6pMMAhnu+wVzJ+k6EbrokTMca6lkrvx XcGWnjamIdCtd7AYaSL+aT68xSAZ6LsVquEmy X-Google-Smtp-Source: AGHT+IETm4Mw4C1WYnuRN1dk6ybQZp+9JbAH95T21UPA3HATzrdU0KuRyY3yw2FY1OGAeUmBlJ7Q9Q== X-Received: by 2002:a05:6000:2410:b0:3b5:f0af:4bb0 with SMTP id ffacd0b85a97d-3b5f2dd1547mr6813098f8f.23.1752393994069; Sun, 13 Jul 2025 01:06:34 -0700 (PDT) Received: from [192.168.224.50] ([213.208.155.167]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3b5e8dc22a8sm9386608f8f.34.2025.07.13.01.06.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Jul 2025 01:06:33 -0700 (PDT) From: Luca Weiss Date: Sun, 13 Jul 2025 10:05:26 +0200 Subject: [PATCH v2 04/15] dt-bindings: firmware: qcom,scm: document Milos SCM Firmware Interface Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250713-sm7635-fp6-initial-v2-4-e8f9a789505b@fairphone.com> References: <20250713-sm7635-fp6-initial-v2-0-e8f9a789505b@fairphone.com> In-Reply-To: <20250713-sm7635-fp6-initial-v2-0-e8f9a789505b@fairphone.com> To: Will Deacon , Robin Murphy , Joerg Roedel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , "Rafael J. Wysocki" , Viresh Kumar , Manivannan Sadhasivam , Herbert Xu , "David S. Miller" , Vinod Koul , Bjorn Andersson , Konrad Dybcio , Robert Marko , Das Srinagesh , Thomas Gleixner , Jassi Brar , Amit Kucheria , Thara Gopinath , Daniel Lezcano , Zhang Rui , Lukasz Luba , Ulf Hansson Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-crypto@vger.kernel.org, dmaengine@vger.kernel.org, linux-mmc@vger.kernel.org, Luca Weiss X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1752393945; l=1075; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=tMLsPA0quQvuGmIREPbj4TjYGghQCOz1jliVkGJZk/w=; b=wu4AXtzoN4ob1c0+EbjfVXv57Iq6e0C+uSlV0gsPf5gka7RfNfnS0ibFZYnFdL1sPEcYX22VD XbfEFfvkl6AB0MjF8vd/pEno76wGjhFqV0jo7S1Szl8EFehBgvQGvL1 X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= Document the SCM Firmware Interface on the Milos SoC. Signed-off-by: Luca Weiss Acked-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/firmware/qcom,scm.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml b/Doc= umentation/devicetree/bindings/firmware/qcom,scm.yaml index 8cdaac8011ba499794ebc5b4291b7983c209821b..b913192219e40324c03f4ff1dce= 955881e7fb3d2 100644 --- a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml +++ b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml @@ -32,6 +32,7 @@ properties: - qcom,scm-ipq8074 - qcom,scm-ipq9574 - qcom,scm-mdm9607 + - qcom,scm-milos - qcom,scm-msm8226 - qcom,scm-msm8660 - qcom,scm-msm8916 @@ -198,6 +199,7 @@ allOf: compatible: contains: enum: + - qcom,scm-milos - qcom,scm-sm8450 - qcom,scm-sm8550 - qcom,scm-sm8650 --=20 2.50.1 From nobody Tue Oct 7 07:06:06 2025 Received: from mail-wm1-f46.google.com (mail-wm1-f46.google.com [209.85.128.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3ECF91FF1C8 for ; Sun, 13 Jul 2025 08:06:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752394005; cv=none; b=XGRWWM/NxIZXREFTteujcRx9euBUt1F65oPHBhtdXiU+JTdUeyTyEVb/88nXjGkPMXsHnDP5TJs4YbmvqlBuG/S/ZixfoiYi8T3hb6kmxIQMEEBMG5vnhWIL+7TQz7xYFcv5dOQZ3lTRJQLTFyV8c36qL8pqbIFNf2cFx4JGuhc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752394005; c=relaxed/simple; bh=15ZIEjfNdTMtgNXBiiZtGshrEuJe2UKgX3LhuQVRQYU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=GH5UtS3E5TH7XMC3+L/NmShIDJ64sXe+CwTAbphAtJyHK7Ut5WD3W4OS4tvetu6Qquk/DQobu0klQR8cUeWUyfXmoeAMIf6qTWYCBXSDAZOrFSXThWV0IvGp/FEGWGd74GgDUO+PJ+QnsTJ0LcgN8ZQKeyqyTHFkThzfhAXWcEs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=fairphone.com; spf=pass smtp.mailfrom=fairphone.com; dkim=pass (2048-bit key) header.d=fairphone.com header.i=@fairphone.com header.b=yrzg/RZS; arc=none smtp.client-ip=209.85.128.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=fairphone.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=fairphone.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=fairphone.com header.i=@fairphone.com header.b="yrzg/RZS" Received: by mail-wm1-f46.google.com with SMTP id 5b1f17b1804b1-4560add6cd2so4680855e9.0 for ; Sun, 13 Jul 2025 01:06:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fairphone.com; s=fair; t=1752394001; x=1752998801; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=sgf1Do8YljBtD81sfx5m266n9gTHXW+o9sPsSEgzP8Q=; b=yrzg/RZSbkRCAWDNuAre/ZMEHVwFjv3P+GTZ7YwKmqhwz1U/ldqpMjXeO6cwdnMOaU iPSgc1nJthruNehCsXOtSuQWw8rHRyeciTvxrnt/vhPP527EA1v8RqqKjsJVcgT2b1dz GNvjfxWp7MNXlHMiCAkxk86nsYypGD0BgPVHpXsodf4biaCOpwgE2Ss3/WxHnQB55r5U R3AV37B2j2HY8h18JbYzT2pJELqfPuKfm1YZm6sv/Hk2BdTbFSOt09ltWmodaPYFvfAF JzTu9h1Xw5w9RJSPZRHKDOE+epZQIlyCjyaki9vyKFrkZfLB0BHRLrGRHLQvogk3tGA3 88uA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1752394001; x=1752998801; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=sgf1Do8YljBtD81sfx5m266n9gTHXW+o9sPsSEgzP8Q=; b=oHtD5v2kxK7KmZhgMOFOZ2KJ+8UfkSySHae+1Ctz2Ia41vMEOsFiIpHfxB12Vehila 8pFqlA0SQ6k6rkuTN/W9eLENB2sFjPb8A3H5lWfSgFW0mlAOKE6iWIWMyLo7uNVgpi6J A9iaOY0DmPhAZsL2etnyiyix6eX0DFh0s5Y8Wg0AGentZzLCPCJ/p/M6DgabMt93FgqX R0Hack+dOX3ni6imK6nuNATZji4Zw0Y+Wp4+26O5VPu9h/r2KwpKJTaZVFreEnDMsDfE g1c9QUYNzbSsXVxJxaOLoU4JsC3+bo3blip6pMURsUo2UvtiDFDO4qTw0wvlfFwzgnWT HfDg== X-Forwarded-Encrypted: i=1; AJvYcCUZIjub/N8jCzOu5xcmkyMy1rzoipeMXSgzu94fcIEcCc19fzJU/jge5KirrwV99P57Eptx83V8IJggfWQ=@vger.kernel.org X-Gm-Message-State: AOJu0Yx1Yq6bOBFsR5k1fon496Zu0M33joRTgas9FX+roKT0mbrb8Zn3 Rd/UwUdmI3FRiG7n4XxMxg3OfWr0sohEY1q2waZzkS/rqDo8K+WkyyXdlCV3y3e7tQE= X-Gm-Gg: ASbGncuCwR8U9uD9ohkTaNRlI3nB+/ZQZIGjbmYMqIdGsv+lkZco2sCb4ojNVf0PpTx jzzWx66gtEpdyBQUT4U8JJku7KgC2Cve97DivdvaPuip253NQ/9E7ER09fT9C6NxNeXYvRM7on2 3efZPD/Ex4O/zPIPFAI4ERIxSz6n3p65IFi+4p99AX9YE4i333VHWfC+JRYEu7eXhTx7noACdZx jW1A1tFiMEMwahwx6tqnVsSNVYPW++szyfFe8TsHpZNSOlPV8CTBtprAHYaBVQUwmCYNfQL7+lv zUfSQP1cZHTLaEMdWN+zvelI/Z1ZcdICkMmEYk4Qv6dZ+50iUxyZv9zvbbCL9//zSJaKjEhLSuk nZdDWc9khe7QzoCshRn+u91SZ++Bkb0oiVdzb X-Google-Smtp-Source: AGHT+IHyWnqMEVpaRvOXMO0vblvM86y2YgLw6BQSvoG4RgYbH/Ui7SAEt4W5s37bEA/xrCAo7hGufA== X-Received: by 2002:a05:600c:3f07:b0:456:15a1:9ae0 with SMTP id 5b1f17b1804b1-45615a19f78mr8952975e9.13.1752394001510; Sun, 13 Jul 2025 01:06:41 -0700 (PDT) Received: from [192.168.224.50] ([213.208.155.167]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3b5e8dc22a8sm9386608f8f.34.2025.07.13.01.06.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Jul 2025 01:06:41 -0700 (PDT) From: Luca Weiss Date: Sun, 13 Jul 2025 10:05:27 +0200 Subject: [PATCH v2 05/15] dt-bindings: qcom,pdc: document the Milos Power Domain Controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250713-sm7635-fp6-initial-v2-5-e8f9a789505b@fairphone.com> References: <20250713-sm7635-fp6-initial-v2-0-e8f9a789505b@fairphone.com> In-Reply-To: <20250713-sm7635-fp6-initial-v2-0-e8f9a789505b@fairphone.com> To: Will Deacon , Robin Murphy , Joerg Roedel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , "Rafael J. Wysocki" , Viresh Kumar , Manivannan Sadhasivam , Herbert Xu , "David S. Miller" , Vinod Koul , Bjorn Andersson , Konrad Dybcio , Robert Marko , Das Srinagesh , Thomas Gleixner , Jassi Brar , Amit Kucheria , Thara Gopinath , Daniel Lezcano , Zhang Rui , Lukasz Luba , Ulf Hansson Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-crypto@vger.kernel.org, dmaengine@vger.kernel.org, linux-mmc@vger.kernel.org, Luca Weiss X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1752393945; l=844; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=15ZIEjfNdTMtgNXBiiZtGshrEuJe2UKgX3LhuQVRQYU=; b=XFV7UWYTfrWv1RcxcWxJVUHuCP5Ysa43LHrg+BrPBDS/KgoKimDYxgTjN9ghI3i9G3ovnwPgG q1r+xiIEV0UBYOCual5XEBtwmgOfedsf3RrNLH/7nc4A/rgd1Nrjzie X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= Document the Power Domain Controller on the Milos SoC. Signed-off-by: Luca Weiss Acked-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/qcom,pd= c.yaml b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.ya= ml index f06b40f88778929579ef9b3b3206f075e140ba96..3f90917a5a4dd9d068ec472565f= 5009690ea2c5b 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml @@ -26,6 +26,7 @@ properties: compatible: items: - enum: + - qcom,milos-pdc - qcom,qcs615-pdc - qcom,qcs8300-pdc - qcom,qdu1000-pdc --=20 2.50.1 From nobody Tue Oct 7 07:06:06 2025 Received: from mail-wm1-f49.google.com (mail-wm1-f49.google.com [209.85.128.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 66FAA1EA7E1 for ; Sun, 13 Jul 2025 08:06:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.49 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752394014; cv=none; b=k1RMFXapxevlQXtqxKsClEeVPX3KQdxa/nTVYe3/UMoow73GyyJ50RnDw85DmW+RrFKgeLYSr6uhO+vXFCOXtboTQ/RUKPwvOZpke3STn2epSz6L5sanNksXl+aws4EAWmSXvxMkD4NmG82ieaeL3nrS4ODY4DVunoYS6OHphlU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752394014; c=relaxed/simple; bh=Elfy6tnJleoo2wYkconqwz9MsTMigTuOtLwwGmq+1oU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ErQn2CnI73rvh6Ty8ytSRhhNQytE8xsLlGmySgbSJ27tNG+XY0B1OVrCiJ1eJFzNpIXET6RXbVZi4H1nhg6JSg8uhDZkGYeYUUcSFtgNSZ1Y2IwCao29N78nBoB6eUisi4VY/+lNFZ2ZGQcuuW7vvNpxTNWb+53Uo8TJk4FnCCM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=fairphone.com; spf=pass smtp.mailfrom=fairphone.com; dkim=pass (2048-bit key) header.d=fairphone.com header.i=@fairphone.com header.b=N3gZsHt7; arc=none smtp.client-ip=209.85.128.49 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=fairphone.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=fairphone.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=fairphone.com header.i=@fairphone.com header.b="N3gZsHt7" Received: by mail-wm1-f49.google.com with SMTP id 5b1f17b1804b1-451d6ade159so24404545e9.1 for ; Sun, 13 Jul 2025 01:06:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fairphone.com; s=fair; t=1752394011; x=1752998811; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=FAW08S+Y4FxJpq/IdHakejhpfXSII54ErAoQ1lsTS5c=; b=N3gZsHt7V9hqmIcHZvDcCJdstid1626nMHcQ5wB9717CeCe3HvPTccBSZP+AeI8Z6u 4ckINECSedmZCm3I+QThA3zguJU89ahIuhFVrdNzTvKtB1ciD23FHH2fWnj/Nn/I/o+4 7U8Ed3O2+r88qjlrjjztgwbHEp+nnQY1HUx3lV4bJskQb+exKJ8sbNER8c6QOhygejI8 RN2Oe5c4zp1aBxPUnHjXbCO5EwdYOsW5erhABSU9V2fa6DLCtZdFCeEP/SXX8rbnVSKg PeHE5yHL1zKEiUXM+Ai5uE3oEPbujXEDpL/1Ihb+DhtjqAsnCO2P6v3oiImVLj+LqC3c z61Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1752394011; x=1752998811; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FAW08S+Y4FxJpq/IdHakejhpfXSII54ErAoQ1lsTS5c=; b=xSKYZ9nt6U7S135t12XLocQ3hUwn/CEkrvopp0MkruK0hnaDLpWiYKgQrC2wVL9WQj XdQtxN3t3QuOJj9sjapwAcRB1YgGKEQrS3xPOp+YsO1uUZzloTcmT1dLjditipoMaAbj +xCFecDaVYqB9EnN6aIZrgmIEBn47FghUWTeWZNI0dIaAwMouUW4XdBS8mDiW4FCFkpV kAZAmQWJZVLbcinK45++1N1gJDs+xjKp7SoS7DlWCi5AyibAdi4ErO0XgxWSWI2fYi2L tsOAHeXrrUwTIkuw4vwp2u7AxI1IbdtyFCi7vFryWHelkWXtb+RVlB6Y+h0a2yPomQaA azrw== X-Forwarded-Encrypted: i=1; AJvYcCUcEXIle4krPJiyihJOrRQGtFz5mwLxp/2GniGx7Gx2vMGmISHI3MJHbGAxQ3I3L5kMpBufiJbGYuSTmqk=@vger.kernel.org X-Gm-Message-State: AOJu0YyHm4zOLxmQ0I+5qn1+sPgOTJJ7iEIRj3X6f3x4pNRyMmzhpODi iq4aojONaKV3uQgtwr67qEpPoBp6WaGPr+oHNC2EFp+z+lK0NCstC3aagbl1YLk8fis= X-Gm-Gg: ASbGncvNjlkdldmP/KTAk6covbcElj3kBBATDPWK5QsyK3MCeGIfRmLLtLFLpXCCRPy RZRUQGnDZR2KV2jMj6tnQwyyuFfqgq/U2vwIhdVRUvQRmovUp81fTQUqB+g/DI6N4T4yLyUhGPs g8JTl5RHtM5aNepiFsiaukQf3755Y3FML68ZovJlZJqaaHfRl93V/VVGwgFDON+BcElLziANVzD 4QuCK041xZ+UMaN6etjafW6JzhUSSb6OyAymTrA77AA+fxq012N/hY9OVMq86U6hyQhWTg6sXeE Yd/Q4Ef01fzuS/eEHuBZ2NrXj8aILRgAMEswKpucfRGTA//jvVlQyyLDXKwyOF46EThS7yuzBe0 GmnZ0Gbl15UmvCd1fQew9pj9YTsjM9A++QCuN X-Google-Smtp-Source: AGHT+IFzbSLLoq4xPNfOGVd8sTIPd/t0yDUx4KghGsVDwxM4zXUXdUnMHorpLtbhoNnu0OiVsDGzYw== X-Received: by 2002:a05:600c:3512:b0:43d:fa59:cc8f with SMTP id 5b1f17b1804b1-454f425a934mr75835865e9.33.1752394010817; Sun, 13 Jul 2025 01:06:50 -0700 (PDT) Received: from [192.168.224.50] ([213.208.155.167]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3b5e8dc22a8sm9386608f8f.34.2025.07.13.01.06.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Jul 2025 01:06:50 -0700 (PDT) From: Luca Weiss Date: Sun, 13 Jul 2025 10:05:28 +0200 Subject: [PATCH v2 06/15] dt-bindings: mailbox: qcom-ipcc: document the Milos Inter-Processor Communication Controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250713-sm7635-fp6-initial-v2-6-e8f9a789505b@fairphone.com> References: <20250713-sm7635-fp6-initial-v2-0-e8f9a789505b@fairphone.com> In-Reply-To: <20250713-sm7635-fp6-initial-v2-0-e8f9a789505b@fairphone.com> To: Will Deacon , Robin Murphy , Joerg Roedel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , "Rafael J. Wysocki" , Viresh Kumar , Manivannan Sadhasivam , Herbert Xu , "David S. Miller" , Vinod Koul , Bjorn Andersson , Konrad Dybcio , Robert Marko , Das Srinagesh , Thomas Gleixner , Jassi Brar , Amit Kucheria , Thara Gopinath , Daniel Lezcano , Zhang Rui , Lukasz Luba , Ulf Hansson Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-crypto@vger.kernel.org, dmaengine@vger.kernel.org, linux-mmc@vger.kernel.org, Luca Weiss X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1752393945; l=806; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=Elfy6tnJleoo2wYkconqwz9MsTMigTuOtLwwGmq+1oU=; b=T2sEIpk5VLO06Z/e33bFZTdbkdzXowfc67kVkvG9wOw56FtIAb0kMpA2M7/tW/buZQMtHaZQQ Pon1YBhAc/uBXmxbSDoNOEBzgAwqhggF7KCZYb3eZ+GNZX+lwv3/qKq X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= Document the Inter-Processor Communication Controller on the Milos SoC. Signed-off-by: Luca Weiss Acked-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml b/Doc= umentation/devicetree/bindings/mailbox/qcom-ipcc.yaml index f69c0ec5d19d3dd726a42d86f8a77433267fdf28..e5c423130db67109355d7da3e51= e1eeb008dee84 100644 --- a/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml +++ b/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml @@ -24,6 +24,7 @@ properties: compatible: items: - enum: + - qcom,milos-ipcc - qcom,qcs8300-ipcc - qcom,qdu1000-ipcc - qcom,sa8255p-ipcc --=20 2.50.1 From nobody Tue Oct 7 07:06:06 2025 Received: from mail-wm1-f51.google.com (mail-wm1-f51.google.com [209.85.128.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 46B0C1E5714 for ; Sun, 13 Jul 2025 08:07:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752394027; cv=none; b=Ns9o+Pfs7vVrsxDRZ6Q7ItsuKGL69oK1CHE3qwRNo9ApfxrB17kccPOz4f8JmK/sKyPpTOYfoJtett/VLb0HE+BRN+lXl/rhnCDYwRMTQ7LOMtizryQ/73QvzuUoSVhpi75YSGclnVLBgZXaRUWkybSXXl5ZpxgU/bFSSwxN9wQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752394027; c=relaxed/simple; bh=psKgizPd8idK+9Xng1zZOiGE+n8ZxAcQQoK6CGGlaAM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Q+sINdPNhDqwos2HRuNEfB64A78e5DTL9ukTcYkbMwdoq/0IGE7cK4rgl3XUz+HFN920gfiIifrbE5DFUmZYRunTXcMN5L0eO/Rjpmd0T0n9nrjx0WQk5AqUx3HIiiazbdHkPfx87+3wyu9UMRThZ4UMsAFgkA+bBdN35hgJopI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=fairphone.com; spf=pass smtp.mailfrom=fairphone.com; dkim=pass (2048-bit key) header.d=fairphone.com header.i=@fairphone.com header.b=Q1PNwP8A; arc=none smtp.client-ip=209.85.128.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=fairphone.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=fairphone.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=fairphone.com header.i=@fairphone.com header.b="Q1PNwP8A" Received: by mail-wm1-f51.google.com with SMTP id 5b1f17b1804b1-4561514c7f0so2132095e9.0 for ; Sun, 13 Jul 2025 01:07:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fairphone.com; s=fair; t=1752394024; x=1752998824; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=6lM8usxsSz+hgDvjepavl+3hVj5I731y8p/a4jtJD7g=; b=Q1PNwP8AFHY3h5FTQVJQoXXLObhKXKjrdBmRnqFLzpcn3mYZm3EQd4e3cpwKBWrIO/ sK7GHZE3Ho3nM5mfLj9VvDKQriNFkg4fzFf7QlmdDE/HE7uKzvUXEHRDvmER1l6k2QJt dvXUg6WjsFpoZ5gky1pM1H9euwV3ksCPnfs8K1q25HDZY5DRWekJGLiDF6qbVkPFJ6gZ AgvSlAL7IlqCtFS1ys9LkJy45rD+DAhGpswHJUYgzQwuy8b6ZEf9lKEJ1LDnARmay+FQ PZSzYJ4S6Y+RznIM3SVnAYZmDuup/ZJKu+aDqSLDSVnVIJlG41ymN74uTsaZBQOWX5jj o6LQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1752394024; x=1752998824; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6lM8usxsSz+hgDvjepavl+3hVj5I731y8p/a4jtJD7g=; b=iOwkerYo0G1CvYEdvGAYbng5e1qTDH4TXVG8enWCZ2r84ywdP+pZiZ2X4X0/Px+PZt E85gKV/q618xbnUkjMn9NqiL+5ZASNX8Dg2mVUo/HxIwd5OlDiauslO3zrk6+h5um51/ 6EAuC/pRT4oysiQ2BUX7o8V1TrymKFm1SOBycrJ2CmQJzuT/7jT9mP7cPPeWJwSSRRIY 3z2OvaB9HSy3BszLVBwQyri3Obm0XrjKtX8fq4QshAPV8TLifSdKggZCk05IzRBaDoYQ U/S7ywo9eUgbhdln5aked+ak2qCEnciMIV/pBaRSMYBHU9VxaaG0A+7f15MkI7gtAJ+o Monw== X-Forwarded-Encrypted: i=1; AJvYcCXpifmwzw7gu1ixVAGeq5J7ZTN2UNE5mcXFg65XYepKZRX0ECpI3q3BHU/1HIA/2U17FEgkF6G/ezA59N8=@vger.kernel.org X-Gm-Message-State: AOJu0YzLEpw1wRtG7dYbD8hJIroq+0nsMiY3OLMACS9dHQJ4NQFo4QHi 24eAzZYi/0/48CuVHuGvo1MyvPgW2sQENvO9Wps4b2n5vvjc39lhzLmsmt+6IOSE9tY= X-Gm-Gg: ASbGncsqze755ebBxWBpDbGwCJc16YAmUSdE3cFKtwx9GmK3G3eWBZEATlzImT2GXhd 8RXgVHLMrBDio+fmJWE0ImL6fpUo88jJAUOYor3lPIMqgryTtHq8Vv6q3g2MANBIJumG0Somopf HAZeQ9Q1dRqMDdBYA5k+kcXonTJ1eb6nkDaK4RDck8AegLnyb8PvyhyJAkyBoD9kyWTXz7WyEts Rhx8UX1iPUXedW9TzChkOBNNySVrl6g8Uir1XnUpRi0nlaxC6tDqPBFLJhC2bO7pz+CQeWx0rnk ONCdFyhxvhCpaHwuTKwvpDrDaemK9JnVAKVZajl285R9AGPCkCmezX8k3NnyAlNO3wvG+8+jaYl VMofEqdYYSvZab7nGtvXblc8sYXOl1c9/8w1v X-Google-Smtp-Source: AGHT+IG3pwvpc6BxS1YVZvmLXezCAzje9Y6cdBA2Ax5A0e9Me5Q1M68h5GqdQnaD8/2y2jlQ5aoTTQ== X-Received: by 2002:a05:600c:1c95:b0:453:86cc:739c with SMTP id 5b1f17b1804b1-454ec14a50bmr77388375e9.1.1752394023657; Sun, 13 Jul 2025 01:07:03 -0700 (PDT) Received: from [192.168.224.50] ([213.208.155.167]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3b5e8dc22a8sm9386608f8f.34.2025.07.13.01.06.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Jul 2025 01:07:03 -0700 (PDT) From: Luca Weiss Date: Sun, 13 Jul 2025 10:05:29 +0200 Subject: [PATCH v2 07/15] dt-bindings: soc: qcom,aoss-qmp: document the Milos Always-On Subsystem side channel Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250713-sm7635-fp6-initial-v2-7-e8f9a789505b@fairphone.com> References: <20250713-sm7635-fp6-initial-v2-0-e8f9a789505b@fairphone.com> In-Reply-To: <20250713-sm7635-fp6-initial-v2-0-e8f9a789505b@fairphone.com> To: Will Deacon , Robin Murphy , Joerg Roedel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , "Rafael J. Wysocki" , Viresh Kumar , Manivannan Sadhasivam , Herbert Xu , "David S. Miller" , Vinod Koul , Bjorn Andersson , Konrad Dybcio , Robert Marko , Das Srinagesh , Thomas Gleixner , Jassi Brar , Amit Kucheria , Thara Gopinath , Daniel Lezcano , Zhang Rui , Lukasz Luba , Ulf Hansson Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-crypto@vger.kernel.org, dmaengine@vger.kernel.org, linux-mmc@vger.kernel.org, Luca Weiss X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1752393945; l=838; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=psKgizPd8idK+9Xng1zZOiGE+n8ZxAcQQoK6CGGlaAM=; b=OPdqk8kzOonRIU/FvMHf4OTch/jvk1/7G0B29tz1FcPCzLFyfw2MFYAPDwPtuFr0E3EKR2CfP Ni3Mb/Ur7LsDyQ+nsHsg5e6NHg8v4v7jXauIS2CrOl7e6VQ6BFwELcm X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= Document the Always-On Subsystem side channel on the Milos SoC. Signed-off-by: Luca Weiss Acked-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml = b/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml index 41fbbe059d80cebb214317df8ae15b86573546bc..d11bb623d08c0877cbef8e8ce47= 95974188b2fbb 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml @@ -25,6 +25,7 @@ properties: compatible: items: - enum: + - qcom,milos-aoss-qmp - qcom,qcs615-aoss-qmp - qcom,qcs8300-aoss-qmp - qcom,qdu1000-aoss-qmp --=20 2.50.1 From nobody Tue Oct 7 07:06:06 2025 Received: from mail-wr1-f48.google.com (mail-wr1-f48.google.com [209.85.221.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1EC7B1F5838 for ; Sun, 13 Jul 2025 08:07:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752394039; cv=none; b=Y+S91rSjpxJSmKzApK4/6nYiQNsd9K5PHl+h0//PWkNVUcGa+jfmeymUfzgNQt2XItHAR51xSNTrk2NRSP9mcIUxoZ1opM3rdC1smoIEtorUt/c91MKOsMhu9uE2/hTMysI/ApYvQsrg9p2iGm0fr4A9KU+DemkWrTsyPNAfOtI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752394039; c=relaxed/simple; bh=ZPOAK3xFvDZxKtMubUGBzI+X0LzZj/ehseUCLqV9308=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Z7SER5AVGI8OepfGkODOPUxceBBsIp98xNjYA0B7RJr+4lgqwdqxLCsAG0iyddD9nlIQLFWz0mTP1065qaahHaQhz6IoykEoE9Dg0v0XpykGvmSw6QsK8LED6Mc1096yG/vQpvrUkrO17t+NHNk0GiSuDbGZzUUeR0+coyv8plg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=fairphone.com; spf=pass smtp.mailfrom=fairphone.com; dkim=pass (2048-bit key) header.d=fairphone.com header.i=@fairphone.com header.b=TG7RkjQO; arc=none smtp.client-ip=209.85.221.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=fairphone.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=fairphone.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=fairphone.com header.i=@fairphone.com header.b="TG7RkjQO" Received: by mail-wr1-f48.google.com with SMTP id ffacd0b85a97d-3a548a73ff2so2930196f8f.0 for ; Sun, 13 Jul 2025 01:07:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fairphone.com; s=fair; t=1752394035; x=1752998835; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=aJyl6Itr2J8CcBOnf8YZMhnDEgMz2YqGF17cfLG0u0w=; b=TG7RkjQOt1q81yyyKBTbe1QUYdoIKhdpCxzaOTjGMogHOwNKL6Egi3VqxzvthquTke TeaOLBI24wSWILWT7/7wJkFK0oilg/7rZY+pPtU6m+EcgQqQuFsC5+Q6Z4P0Tyn3Lt3Y 967nN9RiFvhWO7cPiojPW60sDOF5D9SiuJ4cv/AByYCqxnC0Yvd8RVirluvsG1R9YeUS 2bmhun+vzkTjSE2xvcQnaUuIOrqEh+ub4UVi+CfZms6IGl209PTWVITiezNPFNkTlci2 6bXqW+7tlU+Xu5+p+TENSe+syb3cczNXZZHgm7PZa6DRQLax9ODPMF8yXRi0mwtSaqFi NZMw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1752394035; x=1752998835; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=aJyl6Itr2J8CcBOnf8YZMhnDEgMz2YqGF17cfLG0u0w=; b=Nrtw1VX/8NcYcrzav3PVpNCqA3K3sbzXiD/sf+7fkWSq8WDzTWf4HGt2161vg8RQQA Vxns2h5BPSWpecld7NPa2rtHqDA0+ZvfxSlOQh1qzHzrJHfbksyXUQv40cJNyPd2eiqs 2NPSwuhx+5RY+t+c9B0zULCVPj7QicenBj4rtO8Ek3hY9Bk5jWLFZprkyuLx3MKMwaxZ LSU4kMRjAgLmQM/ZgAjW69cxXan+aqocXmVg+rSBldtj+GOQJh6AKY2gSluizn3EVoE6 ZanOa5KVHYwCUmGzp1rBdiub6OIa2DBpKgFIUcqD1TstG9QJmY0eAIfMwhlrKz1oW803 +5KA== X-Forwarded-Encrypted: i=1; AJvYcCX/lLTp26N3+bCPchViA8rSDODtHbO7iqal8eFnV/KxHrmla1fb623eZeKsaWt3kw7aiGEicVEapRRtM/Y=@vger.kernel.org X-Gm-Message-State: AOJu0Yya5lTzQ0KdLS4+mCX/pmbwbtF4D3woD9yCj87o/mm41ayyDzG/ ugprr+ja7FaOYAVixQ1nknrO1++3qxY9Edw9ZMdKJJUee2rrvxbeuRRYTJsr9AhjK/w= X-Gm-Gg: ASbGncsEFWAcQogiuITBg8A0T8zwUwBirlpoS7rbNIXCPd6Zpt79F//IPoM/AQxXFTs 6v6gdQ73aVOih5h68y5iQTIVLQHD5fMDzBUuZWPddX8pAi4K7Gj1vnU9S7I9rav5Ehhldi+iJjX eBCWPwnRRre74qtQ8v6LFS6W+7cxBd7Oed9gx+iD1CE1s4OuXyGRRMbqBFpzIuU08i87rsucneZ yAIJ1KN6zcSCaeTEByJ+gw7sXpWEzm2r/+VLmVp32i30FoKo2PkdmaV/hB9GbOYujOoWw3OfqZB RTe9zKt1cUgrFTqF8mHXSsNb1N7QrD+1/p7w6wlUM756dcqt7b1YaCa8WJadTaG3OuPlHnB/BV5 VLJL3MnHF1B7PL1VkqVaft6xcAerVKRJ6YgUH X-Google-Smtp-Source: AGHT+IFDkaJX0TEdwthvnMnibkv7x2m1KVCrimnEeDmcfRvTFWioaF6EXSVrFnCJ2KS+deMt9VV08Q== X-Received: by 2002:adf:ae4a:0:b0:3a4:f787:9b58 with SMTP id ffacd0b85a97d-3b5f18abc86mr5290060f8f.58.1752394035324; Sun, 13 Jul 2025 01:07:15 -0700 (PDT) Received: from [192.168.224.50] ([213.208.155.167]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3b5e8dc22a8sm9386608f8f.34.2025.07.13.01.07.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Jul 2025 01:07:14 -0700 (PDT) From: Luca Weiss Date: Sun, 13 Jul 2025 10:05:30 +0200 Subject: [PATCH v2 08/15] dt-bindings: thermal: qcom-tsens: document the Milos Temperature Sensor Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250713-sm7635-fp6-initial-v2-8-e8f9a789505b@fairphone.com> References: <20250713-sm7635-fp6-initial-v2-0-e8f9a789505b@fairphone.com> In-Reply-To: <20250713-sm7635-fp6-initial-v2-0-e8f9a789505b@fairphone.com> To: Will Deacon , Robin Murphy , Joerg Roedel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , "Rafael J. Wysocki" , Viresh Kumar , Manivannan Sadhasivam , Herbert Xu , "David S. Miller" , Vinod Koul , Bjorn Andersson , Konrad Dybcio , Robert Marko , Das Srinagesh , Thomas Gleixner , Jassi Brar , Amit Kucheria , Thara Gopinath , Daniel Lezcano , Zhang Rui , Lukasz Luba , Ulf Hansson Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-crypto@vger.kernel.org, dmaengine@vger.kernel.org, linux-mmc@vger.kernel.org, Luca Weiss X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1752393945; l=844; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=ZPOAK3xFvDZxKtMubUGBzI+X0LzZj/ehseUCLqV9308=; b=g6khw9Eoj3k7qdE6HzUK3LwUa3ARHqiUtNifgmAtPNMijChPBfhsPG+M6zDWw7Jp/LdMvpqx0 G/ABS6yAzifCr1yjRWLDxYJ5Q3VDCx3clJN4ZacevbE60KKq1Tn9u0D X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= Document the Temperature Sensor (TSENS) on the Milos SoC. Signed-off-by: Luca Weiss Acked-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/thermal/qcom-tsens.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml b/Do= cumentation/devicetree/bindings/thermal/qcom-tsens.yaml index 0e653bbe9884953b58c4d8569b8d096db47fd54f..94311ebd7652d42eb6f3ae0dba7= 92872c90b623f 100644 --- a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml +++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml @@ -49,6 +49,7 @@ properties: - description: v2 of TSENS items: - enum: + - qcom,milos-tsens - qcom,msm8953-tsens - qcom,msm8996-tsens - qcom,msm8998-tsens --=20 2.50.1 From nobody Tue Oct 7 07:06:06 2025 Received: from mail-wm1-f50.google.com (mail-wm1-f50.google.com [209.85.128.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DD5AD1F9406 for ; Sun, 13 Jul 2025 08:07:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.50 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752394049; cv=none; b=gJ3Sj5PLsBB9ZdMw1td54H8akxilcTO8mhfcAaHE59dMeb2kfnFVACJHZpWrWHRss+ODm0lMuAk7qDbMO1TCWGt0183ekgn54Y9mUFkKMdjCr/Lnm8RaRp9e/gbDrScmaSof8vP42FUuUiYFDIWJDY7UuK+B3QQAIAy/iLC+ags= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752394049; c=relaxed/simple; bh=cmEjmUIEwJdszNuha6SGlHW2o0fXW5xz6+LSWPvZsgg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=NSuAkQPPGGBEHDEdT/YABzilPwghztrTLlZMiczP+oeX9+ZEtisECXimB80fVin+VcAl7iNMsKMzixaR4906hI3BFeQMqEMV65saqgCvqG84P1jfpUxk1NeEsMX8VUXIpy6H4pZCkX7Yu1iCgpO/Jl6EF0mzCYdTEJeDF90r1T8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=fairphone.com; spf=pass smtp.mailfrom=fairphone.com; dkim=pass (2048-bit key) header.d=fairphone.com header.i=@fairphone.com header.b=rhCmBe63; arc=none smtp.client-ip=209.85.128.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=fairphone.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=fairphone.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=fairphone.com header.i=@fairphone.com header.b="rhCmBe63" Received: by mail-wm1-f50.google.com with SMTP id 5b1f17b1804b1-45610582d07so3280125e9.0 for ; Sun, 13 Jul 2025 01:07:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fairphone.com; s=fair; t=1752394046; x=1752998846; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=HAOuh0e5PjdM5Thiks9XcjQnZt1mrG00zqw/b7U8tlE=; b=rhCmBe63rQcKHBXGf5EHrUzC/Dzyy9df2hTQQco/McWi33I6jERrxoswYpCVq2pMTC ioz623171BTrfBfPuxeDTQ4qfIaJdwe4lsh9T3T8rmCQABJNUXM3h4bKudmxtnUNDgpO ndepDwaMbhlRVJ3HuGgYVhkv2a9qjK6AlTyayqWKELm9gL+Yc2jI+9K4VuEZesA06kIy wtKhOFDARDhqQeRqWcq1QTBiwYrDM4bGd7RAfNUIvPKMg9jEc+IvNuQGsvDx4tZmSYA8 olHDRBckQIXEE8VOzPFrg/jYLWJgIRNERXYePXJfRdocIWgm02CD66ZYZzyBEbDOFZNG 5ULA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1752394046; x=1752998846; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HAOuh0e5PjdM5Thiks9XcjQnZt1mrG00zqw/b7U8tlE=; b=QkPzSQtLiMgqQhPsvBCwCNFdV2t/ncU06shzWnZoaZBXgFYkE8ykChG85fLETcM4XV X2F8rZNw90UDhiLevynoKB2yk/BxuP1ouTtT7kT5iBZbs6y7GgMDoKE7wojT5FdxCcOD eqar0mgbO0h0AaqtsJKNElf36tjV0lPdkw4Jb9wD207WfjU7Qbo+KW4i8f4mYt8JSHbX riW3dlD8EuKacsvjK0bUwcxMuS4h/PunJeP0rVIhzypTmnLnBYESKoixMYEtEorkwrH9 iOBg+zsR4iVpUGKeMLVnARXjZL+yUjEg4JR9J3Oi62ZwzX09zx3QQ9QcPydnJgT6Gala KfDw== X-Forwarded-Encrypted: i=1; AJvYcCX5RlMR0wYauxJn/t5QuQaF3fyTh/MLiBSO0mO6QlfN9omwiVpnGSuJ0snI68fCKxhMCqzEuId2/q72yKg=@vger.kernel.org X-Gm-Message-State: AOJu0YzBsmGupM+4FQct9e9puPJ28e2vi1dhi7pNJ/s5+pnXkrMAjWA1 Ws7l7MzC4Wcm/34G77rcAmsL/gVhHeb7zypA4wIre4RQpX2/0/isThmhIsQ4iH0Nz3E= X-Gm-Gg: ASbGncumoO9q8vU7Lr8A7q2+ilnb5XXCUn3OZYb9aP67D0jhpIg7jj7TFs50KJdKCaj cwUOjY3vdTxPhMGVsVdxDM0NSiBBSCWWJqNuYA9dIF7lEUeUPTfXFmjdtgwXoVH8bSj6gH56Jbo szqQrJjnHg8FfIgw0CQrd+Z+8eKTmbEoE3pAtVZcRsy7SdMPN+AgXKbW3nkUx8mYlJIYPynPbxa vBPRom8EZO9pHQvCxFGcFaXzykumDa3L0pKyUSNCrXfpWj3QG1UVpcVk3ShJsd6nUnZaeZ/n5na Ja7K7Nuibp1LPl69k1QaTR9o91KxWNpkR/9VZfCpapoB/AxaXa9jJegaZJX/E/XqdZ93b8TqyuC G4VKYOFFet9TxDe4pSmHej3+aqhHFYovBMcxb X-Google-Smtp-Source: AGHT+IHNat+zEG/luHBNIINd5V8v6XlcBVNxebQV2Q9VeRLv4kxzRp8ULT+stMytttEuuhYWEbWuVw== X-Received: by 2002:a05:6000:2086:b0:3a5:67d5:a400 with SMTP id ffacd0b85a97d-3b5f18b3eaemr8361545f8f.33.1752394046075; Sun, 13 Jul 2025 01:07:26 -0700 (PDT) Received: from [192.168.224.50] ([213.208.155.167]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3b5e8dc22a8sm9386608f8f.34.2025.07.13.01.07.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Jul 2025 01:07:25 -0700 (PDT) From: Luca Weiss Date: Sun, 13 Jul 2025 10:05:31 +0200 Subject: [PATCH v2 09/15] dt-bindings: dma: qcom,gpi: document the Milos GPI DMA Engine Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250713-sm7635-fp6-initial-v2-9-e8f9a789505b@fairphone.com> References: <20250713-sm7635-fp6-initial-v2-0-e8f9a789505b@fairphone.com> In-Reply-To: <20250713-sm7635-fp6-initial-v2-0-e8f9a789505b@fairphone.com> To: Will Deacon , Robin Murphy , Joerg Roedel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , "Rafael J. Wysocki" , Viresh Kumar , Manivannan Sadhasivam , Herbert Xu , "David S. Miller" , Vinod Koul , Bjorn Andersson , Konrad Dybcio , Robert Marko , Das Srinagesh , Thomas Gleixner , Jassi Brar , Amit Kucheria , Thara Gopinath , Daniel Lezcano , Zhang Rui , Lukasz Luba , Ulf Hansson Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-crypto@vger.kernel.org, dmaengine@vger.kernel.org, linux-mmc@vger.kernel.org, Luca Weiss X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1752393945; l=809; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=cmEjmUIEwJdszNuha6SGlHW2o0fXW5xz6+LSWPvZsgg=; b=PdARDzzFMZy7Ut6DdJtISA7htSoj0AT2jFnSpJ6mCPR7xKdPfXUdr9NJCuHBaBjbgQNs+Hcav 9Qi/8P7T+qNBz/thYmFy0Bn74Jp3O9N12GTa6rI4xDYY/rk8g6EpebR X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= Document the GPI DMA Engine on the Milos SoC. Signed-off-by: Luca Weiss Acked-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/dma/qcom,gpi.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/dma/qcom,gpi.yaml b/Document= ation/devicetree/bindings/dma/qcom,gpi.yaml index 7052468b15c87430bb98fd10bc972cbe6307a866..1655f21a4f64c588851c48381a1= 8965c946e2df0 100644 --- a/Documentation/devicetree/bindings/dma/qcom,gpi.yaml +++ b/Documentation/devicetree/bindings/dma/qcom,gpi.yaml @@ -24,6 +24,7 @@ properties: - qcom,sm6350-gpi-dma - items: - enum: + - qcom,milos-gpi-dma - qcom,qcm2290-gpi-dma - qcom,qcs8300-gpi-dma - qcom,qdu1000-gpi-dma --=20 2.50.1 From nobody Tue Oct 7 07:06:06 2025 Received: from mail-wr1-f49.google.com (mail-wr1-f49.google.com [209.85.221.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 20770221268 for ; Sun, 13 Jul 2025 08:07:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.49 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752394056; cv=none; b=p9wUEccgGMjePxdteKAt8ElsFkPKXbxcz2H/DkWSO9SY1OgWHa5NLrZCTBZZLCnDrIvk6LV7UAuHgekyHcWygSNznpkhzZOKWMrZkC1ga+YGMbU0yR2Gob21CC8+6IVWapCNpl82RqcZwC9F8uCJg8y/cHMkNUn8f0q7tS02oeg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752394056; c=relaxed/simple; bh=aDMmuhwLGm8e9aVoqg3PeCCwJAaRLrTPedtNvgdSwWY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=pTGw7YfCCzvc3zlkSPqSsyfusXLzJ6K4PCFRCpX53uJT7jlsuvp65bZ1d9KyrMZRzwz/VwVgyBcLbDQOcZB2Ir6gezmwyQizCI4+ug+5RAWB2yHkULFs0bAw5JoUZI1iECwGozn6LkZAFMfwTGdC7WMXpIaZfbWjDUymxRNZSuI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=fairphone.com; spf=pass smtp.mailfrom=fairphone.com; dkim=pass (2048-bit key) header.d=fairphone.com header.i=@fairphone.com header.b=zd6OKtlv; arc=none smtp.client-ip=209.85.221.49 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=fairphone.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=fairphone.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=fairphone.com header.i=@fairphone.com header.b="zd6OKtlv" Received: by mail-wr1-f49.google.com with SMTP id ffacd0b85a97d-3a53359dea5so1861614f8f.0 for ; Sun, 13 Jul 2025 01:07:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fairphone.com; s=fair; t=1752394052; x=1752998852; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=9/c/J3A9ASq/x8Yj1Xu/txbcuuFB9UfWNR/sa9FS0As=; b=zd6OKtlvvCClUwllW0CO64sKlzsP6TbpD1VGG6auzuAmCJEVoreA3lWokdtjNOUL/E MYk1bTMuV6bZtow/wxvLKKu+V6LUDJkwEXmw09v9RwBnL/l1HdNxvCq6JXNQC2p9pkRp bbnjlAUchvCzHC7kbb5iKNWT5VPsvQU/hCEpc21hHLwSlu5MBl9iko75YGMQ6cA6uv69 SbihEP40qDhrNYAKFmh6w9eHvgXjTsoQ2gl7f0g3NJ9vfpRf2bSsUD/kuSbm/lv0p/SS VzroI0RjSw2wMHm9IqFnI/GcQrEWetSUXWBCAwsav2yCU+CbHurxRFiU2iebpD3KRlU7 BddQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1752394052; x=1752998852; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9/c/J3A9ASq/x8Yj1Xu/txbcuuFB9UfWNR/sa9FS0As=; b=kyRAOb5/HdO2vsLk64XrYAU4V8JWWle3Aifc8CV8tmxg+17zhiwxY4BGAoEB47UDLl Wx5r/WZMAYH4bbfuxVS+aIbj/SO+PfLNNCpVRsLoXf/6A2OJE7Vl7VmDoCf3k0XHtxzE sqS/1tKQ1XsxjCjNz7FGAZfx0bEui4zGoW6pyyILwVToLsWBeKIs2VgkUFA+LbOCpezy ZXMLC8UE/DmMKg/YJVnBjJYpC7hfcLIyXGrJPljO4RR+ZluaLTobHNvg+s3OyEwQIlSf SYDVf8re8lno0tK5fPW6czFIwWmN950RwFl1BprvRWpeSytX1pViy0ejp++4hVNobfMg KBeg== X-Forwarded-Encrypted: i=1; AJvYcCWPhpfPFLosRE2+/JIopRp4x0Bb2pjgLhOXIypOh2PcH63AIkpk7nzJo2opGJDa6feGDw/rW9BetIqqT6M=@vger.kernel.org X-Gm-Message-State: AOJu0YzFVZZm/rkiKKlxTaA7DkaxeAKTYFYe8m9CYh7L+MM485YgHvpr Ra9+XXzV2iiyK5atbndj7QlErTZ72xWN0GwYyR3+P6kLQAKPxR7BTP3LtXZUospivGE= X-Gm-Gg: ASbGncvRgLnA84kyWxbQP1JEV7MRe6aKqojlkQ2xampkBUTEri/2ZG40g+iVVFa3Xs9 MbE4PJGu+byFf/gKnO2k0DBw/yNKU64tntxa2p/SZNAqzteGnpzYFZqwxCMiJxBXGaaMD80iUkv 8iB1Qq7VyiqzBIfgtD8R1pCLI36XD74DVlPg3E6S5J5hxouHrdFI9VVmwIscS4Vv9jKi2EnyEMD O+Gj69kkiBLuw+xB5P7Iez569MMihfjHKpe6LZDzvPhhombRyP5nCsLFRF2yZNgRp1osXRk1DHr ImkOmqySSUd4miMOqmpGaKvb8NHBx3xQkuekEHPFGFjMOuW2inApBoh+iB91NfipwTdKrHB6mMd aVIMM+9w6IpaPVDxr/dvClNanfF0ugCTfKXx2 X-Google-Smtp-Source: AGHT+IHfutuWB7rD4cm9MzDFG+4cnjfzK3xIdEUacutPo2JmbTjuiRMzIjn8M5NoivS2vTb1Jp+CSw== X-Received: by 2002:a05:6000:470c:b0:3a4:d994:be7d with SMTP id ffacd0b85a97d-3b5f2dd470dmr6368310f8f.23.1752394052404; Sun, 13 Jul 2025 01:07:32 -0700 (PDT) Received: from [192.168.224.50] ([213.208.155.167]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3b5e8dc22a8sm9386608f8f.34.2025.07.13.01.07.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Jul 2025 01:07:32 -0700 (PDT) From: Luca Weiss Date: Sun, 13 Jul 2025 10:05:32 +0200 Subject: [PATCH v2 10/15] dt-bindings: mmc: sdhci-msm: document the Milos SDHCI Controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250713-sm7635-fp6-initial-v2-10-e8f9a789505b@fairphone.com> References: <20250713-sm7635-fp6-initial-v2-0-e8f9a789505b@fairphone.com> In-Reply-To: <20250713-sm7635-fp6-initial-v2-0-e8f9a789505b@fairphone.com> To: Will Deacon , Robin Murphy , Joerg Roedel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , "Rafael J. Wysocki" , Viresh Kumar , Manivannan Sadhasivam , Herbert Xu , "David S. Miller" , Vinod Koul , Bjorn Andersson , Konrad Dybcio , Robert Marko , Das Srinagesh , Thomas Gleixner , Jassi Brar , Amit Kucheria , Thara Gopinath , Daniel Lezcano , Zhang Rui , Lukasz Luba , Ulf Hansson Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-crypto@vger.kernel.org, dmaengine@vger.kernel.org, linux-mmc@vger.kernel.org, Luca Weiss X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1752393945; l=846; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=aDMmuhwLGm8e9aVoqg3PeCCwJAaRLrTPedtNvgdSwWY=; b=QyvoywS+ViPILVHSWP4Oe4jmXijRzJRl4R/Cid8Kttmp8MEimcvZbZ2reSR7fMW32bxl68sjl rIaZtlOjefZAQM2+cVveN692VtVF73WT6QgLclxD9GL7msUjQM+72/5 X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= Document the SDHCI Controller on the Milos SoC. Signed-off-by: Luca Weiss Acked-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/mmc/sdhci-msm.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml b/Documen= tation/devicetree/bindings/mmc/sdhci-msm.yaml index 2b2cbce2458b70b96b98c042109b10ead26e2291..6f3fee4929ea827fd75e59f3152= 7f96b79b2cca8 100644 --- a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml +++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml @@ -42,6 +42,7 @@ properties: - qcom,ipq5424-sdhci - qcom,ipq6018-sdhci - qcom,ipq9574-sdhci + - qcom,milos-sdhci - qcom,qcm2290-sdhci - qcom,qcs404-sdhci - qcom,qcs615-sdhci --=20 2.50.1 From nobody Tue Oct 7 07:06:06 2025 Received: from mail-wr1-f46.google.com (mail-wr1-f46.google.com [209.85.221.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 38FF61F12F8 for ; Sun, 13 Jul 2025 08:07:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752394074; cv=none; b=EIrnueb3L5tDZYciYu2CFH7fuUZpxxPP5VfY2WUtRM/ExTXb2i8RiyPMhNxk/n+N/BqLqddLPt9aCAxY7Ou5OofvLhogm6m1FBLPnUKtYYPAQYQSOjOXg0ZrsADDQUY0IsrjF6xlP0OSTZzM9+ouW0gKPPs42alE0/Qs3kD1XfI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752394074; c=relaxed/simple; bh=DMp52hjvQJeToXn5ideaGQ3795khbQZVtSdtbMOEerA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=MT2p4Q/PB9x+JX6XVUzbGTdpg9cxZaRkCIzv8kYwPPRWnYmG3OqJNB9sVnZ0tx2DSjqIz5+w03Y9Ki84zye5+R8w83yhlktriCUbE8qK/Fga7jMihoMpWq9Er1mTSPgp0se1+esqEDH7M9iARazn1TzWpGDA2ohl+Mr7CTdjKmo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=fairphone.com; spf=pass smtp.mailfrom=fairphone.com; dkim=pass (2048-bit key) header.d=fairphone.com header.i=@fairphone.com header.b=rt+sHqQP; arc=none smtp.client-ip=209.85.221.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=fairphone.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=fairphone.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=fairphone.com header.i=@fairphone.com header.b="rt+sHqQP" Received: by mail-wr1-f46.google.com with SMTP id ffacd0b85a97d-3ab112dea41so1828665f8f.1 for ; Sun, 13 Jul 2025 01:07:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fairphone.com; s=fair; t=1752394069; x=1752998869; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=4SQo06CwZZ+bZ2XWolSLrsJUXJrZwysl3KLdIVv7Q+Y=; b=rt+sHqQPbL7q5CG+qaoS+jJe3AhOvlQP1dx2b3qHEkebGRA0vIuvEkVEDiYde71sGu rSECSw2ILnHKlJVyCjpBj6jinCKACGppP1w93tov3veV+/FYN1pbeSOuQH7BFcW2WwE6 PtA/PNu0oKmxRLY6YQRg+gw30J9Z4aupn9At/k6PevB+YXXwj6SkHz0ITYGS8DHo0MJJ JWbtF/ULKEjd6wTtekBZQ2WPti1g/fTFizbUZYayoBjT+jUeVwZQ4BuD1R45iI723l03 tebeHQUGrdr1Zh+z5aDYZeLondo3smy18h1R4JWNW3nupMKIyHbxsoGiO1H+f0CPPnM4 NuTg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1752394069; x=1752998869; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4SQo06CwZZ+bZ2XWolSLrsJUXJrZwysl3KLdIVv7Q+Y=; b=mN/MO4KmAJ/BHZBK6jD13XEmlv3v6Pu0vY1dv9QZKqt1UN5mCdm/VrQMdAqRuGKULW 5gkVck+zRPPk3K8GcjCX8eQKYcBF1B6mUzHFWlsjHXIUfWa6sAEkSjTn8qpdTkB3sdKT yow8p5EjJ2RXY1qUDV9kZkoImgJQEbw7c7wJzwrjLwG+asiS0jyYNXby1zpRkslTsXPM HriyNN5iKU4LOjf+1+Vze6Qe0ea+3EQMmmPH4CFnP/KKMq3HjZtOa35XetuYOvm8eqc8 QBE2Zrz+4ydOsEr0EjRG+yknWsX3iIsaKPD7q1HabhottbOESbfXGEKPudlqdDfax8G6 jmfQ== X-Forwarded-Encrypted: i=1; AJvYcCV8GjSTtI/oqS6P8AvkIUFdlSKTjXFomvTC3RPjTIFRN3yk662wrfAJs6LTH4vpL+YT1KP0lFC0vKRJUQA=@vger.kernel.org X-Gm-Message-State: AOJu0YwR1hFn9hqgn1TfmWZ7JnVlGzu+7pH9SWtVcq7HjVupSnbXqF79 lBI/3pZckr2fDPcU+livpmMauc9c8ec1DxQ4MQJUJlQ+zEUFmkzrLnRxnJiL2J3s0+g= X-Gm-Gg: ASbGncvqz6K1jFsyj7LoMaOU+KoQM0wjGFypTiMxaUG9lnhRI13apsPQNkm12lo76Yg ybJrcGpCJIZIEamhOdP216CutgGVxk3JyjWI9RigCSmW5q3b1ZR9jftg1oXGwYl1QdsICsEJ4K+ ezlyA42LUBbaTlyuL3+OZOz4fr24PuCk59UzN/8oTxLukOrFiyvlvtjP/63iC3sdKcKmU1bRB34 cwM9vyiv2FRK/MKMtu0+TlmGHQ3909hw1KFvF8ytYsjTxL8Lug+XrFUycpFizwEpvKybBoe9MnG oRieAugIhJ7geiSygWe9z716iZfyTH5L6Xz0484AFoKWnls8v2aDHWaDFe13HP70AGdvZyMzBDH vgB74GtgzzJSf4Hg8MWPIVJmx8W/oMxOszmIC X-Google-Smtp-Source: AGHT+IHS2sHqpL2/eZHUmAy8MZC5zOfAiyOO2INQCZr8EwbUKzOMR7kfyYk7nmZApin+IuOyVWkYMw== X-Received: by 2002:a05:6000:40cf:b0:3a6:f2da:7fe5 with SMTP id ffacd0b85a97d-3b5f359996cmr6132510f8f.55.1752394069433; Sun, 13 Jul 2025 01:07:49 -0700 (PDT) Received: from [192.168.224.50] ([213.208.155.167]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3b5e8dc22a8sm9386608f8f.34.2025.07.13.01.07.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Jul 2025 01:07:49 -0700 (PDT) From: Luca Weiss Date: Sun, 13 Jul 2025 10:05:33 +0200 Subject: [PATCH v2 11/15] dt-bindings: soc: qcom: qcom,pmic-glink: document Milos compatible Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250713-sm7635-fp6-initial-v2-11-e8f9a789505b@fairphone.com> References: <20250713-sm7635-fp6-initial-v2-0-e8f9a789505b@fairphone.com> In-Reply-To: <20250713-sm7635-fp6-initial-v2-0-e8f9a789505b@fairphone.com> To: Will Deacon , Robin Murphy , Joerg Roedel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , "Rafael J. Wysocki" , Viresh Kumar , Manivannan Sadhasivam , Herbert Xu , "David S. Miller" , Vinod Koul , Bjorn Andersson , Konrad Dybcio , Robert Marko , Das Srinagesh , Thomas Gleixner , Jassi Brar , Amit Kucheria , Thara Gopinath , Daniel Lezcano , Zhang Rui , Lukasz Luba , Ulf Hansson Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-crypto@vger.kernel.org, dmaengine@vger.kernel.org, linux-mmc@vger.kernel.org, Luca Weiss X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1752393945; l=913; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=DMp52hjvQJeToXn5ideaGQ3795khbQZVtSdtbMOEerA=; b=2eut1D91kUWr+UGFcP8InACFwKyZfGSbIzuWVeP5xkcguaoH4DRmEvY3vHIxpLqdLQJKX+0r2 KfHKbW+PBgpAlCoAY9hPuWiP349REQ62oa0RFzX6yRzG0QgrVbKKlFK X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= Document the Milos compatible used to describe the pmic glink on this SoC. Signed-off-by: Luca Weiss Acked-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yam= l b/Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml index 4c9e78f29523e3d77aacb4299f64ab96f9b1a831..48114bb0c9276c9326db3256401= a3ecaa8b3b9fe 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml @@ -37,6 +37,7 @@ properties: - const: qcom,pmic-glink - items: - enum: + - qcom,milos-pmic-glink - qcom,sm8650-pmic-glink - qcom,sm8750-pmic-glink - qcom,x1e80100-pmic-glink --=20 2.50.1 From nobody Tue Oct 7 07:06:06 2025 Received: from mail-wr1-f52.google.com (mail-wr1-f52.google.com [209.85.221.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F0233223DEF for ; Sun, 13 Jul 2025 08:07:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752394081; cv=none; b=RtE9nOeyeV9VRsVxYJmTt7+AgGg7g+2AhKfqegRbZ+vpb+vMuJPof0nQiXTRiZADLNghSOMHrDBox1T0z5/qtv7EnQAO5YKFerfWz3mC3T/idd8GMQV2FFq8HGazeT25UEvvQTNcQXPOf8U4S++lHHGs6fKN/cM5yxKn/YS8Sp4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752394081; c=relaxed/simple; bh=yPJZUHzJ6XbbvDpc1ODgE88aN81oenBu6+oDbLZi6Fw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=E7S1kqUpQRUxz29bjkY7CZVm78F3S5M3Goy2lNTl3vILygDAXZLM2rbELrGKM5tUlMzAH2IQz6uY79/jVk2/6omqGxfObLDpUB+gGMws3XafFVZ7qgaxp38C76W1l4xCXJsOEE/2uDEal7qQnm029VkymUKqSXlFIpah+Ja8uIM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=fairphone.com; spf=pass smtp.mailfrom=fairphone.com; dkim=pass (2048-bit key) header.d=fairphone.com header.i=@fairphone.com header.b=4yA6yoPi; arc=none smtp.client-ip=209.85.221.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=fairphone.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=fairphone.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=fairphone.com header.i=@fairphone.com header.b="4yA6yoPi" Received: by mail-wr1-f52.google.com with SMTP id ffacd0b85a97d-3a53359dea5so1861674f8f.0 for ; Sun, 13 Jul 2025 01:07:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fairphone.com; s=fair; t=1752394077; x=1752998877; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=Uq6707S6F7Ph6Bn24TeKW5JdfT2AUuElQEXV+Ub8YnU=; b=4yA6yoPi6nA8XogS+h88iocKe8iUorOKdq6CEkffaek4fVuzES58/+4wvxf4x2zBOH h59crMtSLFTngxNZTVnn3T2+r0RaaubOUyy/rCr9X7EHaEvR8u8dK4bP29Z9kXPsmXcL qsTZMyMKkwoUzPhm01bf94RJC1DYW91N0qEd9E36BjrCNJGG/BZCA1g5b4BPL5vWaKOl uPr3IYx0cfY0J7Fmfx0E/FKdGV1OKeViBvmU59kMdXChP9JwoHjoKRR9udVx+fZOHArG IaK0ix0NWG2L8t6MA2HJfTri3/UBOq2gwxiE4MIvcuxNb+bfTT4DI9mTVTMIieuUxwXW PjBg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1752394077; x=1752998877; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Uq6707S6F7Ph6Bn24TeKW5JdfT2AUuElQEXV+Ub8YnU=; b=GdOcncwRRzTN2MBk61160cS6Ybh6/iL7yG/VjV/NTJQ7aQC35JC5aJx+vlCsTEhsLd OGkPLNsxhumCbFxCacCDwP7LTaDzA46yFS7UDGi61CG3R4JHCQS5LQXBfXywW6Qboues yMviqXTdSNozv1ztyE0CA14OT9C4KxN3tXZoNzsdCi9HjtoOEySfk9pYk0nw5fx3y7ZY d5W0nqbCOT9ucsnJeIhnryxHlsNFsM7omnh5p01cW0Dp3Vb//iMDB35lwS47809RxvnO KqdKItdrhJnvAqGfPeMLvjUFNo1UnTkc3auRsXFK5Jo4Ky76fsy2uedRUEQ5gvBBekTT xpbQ== X-Forwarded-Encrypted: i=1; AJvYcCXgXQyjaTu17xe1f9JBV8iCFNoFfYNXbrj20IZGOqreOhmBzR79q0hAi82Ba11AcZGZEKnHt4yhob7OfPE=@vger.kernel.org X-Gm-Message-State: AOJu0YwYDerAiD8cLaGjmz0YmUSu0OG6q2qQMzoXt0vJW0iWggU5BPH2 eJroBvs70zEGgx5yfMkGma3VlfLJEVvrAPeSMLvu3lUGCQ8tloGCzETYF4LKBPjXgtE= X-Gm-Gg: ASbGncvdg2+ghJ5QVJ+ImZ3h2yiD3wsERhqN3nSEDsyEPjZabBDhaE6axISRnU+BmnX wVt3Q1cKBS/Votgg1HIMlXbzuc95+4ELHwh1o2h5TrYF7N+9C0dPYMjYD8EP0/1AHvg4wEmS+3D +JYOeJ4ds2ip1rHjoL7nYS2PHEdD02QgQdNnvQp5/WVfSdM8S0wWMjCxkEPCYJVqPNFfSpHrrZO MdJ9JxC5V32foVy1ymJXXbombwPkJtq+rDRIZebsRXjFgPr0gHWysYM+j6vXEAXlmeZf/PZ1I0N Jnk4dYnE7vlj9xkXG7XUUAIh6MrAA6t97J3k71qQR3Xti0B23oEWHUHWhFzuzWhYpLOZN/zCHf4 6HuaO9/SqpWKq7AchAOsjiLuQ/S41UNgvtf+9 X-Google-Smtp-Source: AGHT+IGMCdx7d+JV7VT+NDUL2DlG4mtQQoySy69Gfp3Ds2b0lZ7KbU9s/Vv3M69/0Uqu3iIlOqMa4w== X-Received: by 2002:a05:6000:490e:b0:3b4:9dfa:b7 with SMTP id ffacd0b85a97d-3b5f2dd49c9mr7880135f8f.25.1752394077215; Sun, 13 Jul 2025 01:07:57 -0700 (PDT) Received: from [192.168.224.50] ([213.208.155.167]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3b5e8dc22a8sm9386608f8f.34.2025.07.13.01.07.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Jul 2025 01:07:56 -0700 (PDT) From: Luca Weiss Date: Sun, 13 Jul 2025 10:05:34 +0200 Subject: [PATCH v2 12/15] dt-bindings: arm: qcom: Add Milos and The Fairphone (Gen. 6) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250713-sm7635-fp6-initial-v2-12-e8f9a789505b@fairphone.com> References: <20250713-sm7635-fp6-initial-v2-0-e8f9a789505b@fairphone.com> In-Reply-To: <20250713-sm7635-fp6-initial-v2-0-e8f9a789505b@fairphone.com> To: Will Deacon , Robin Murphy , Joerg Roedel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , "Rafael J. Wysocki" , Viresh Kumar , Manivannan Sadhasivam , Herbert Xu , "David S. Miller" , Vinod Koul , Bjorn Andersson , Konrad Dybcio , Robert Marko , Das Srinagesh , Thomas Gleixner , Jassi Brar , Amit Kucheria , Thara Gopinath , Daniel Lezcano , Zhang Rui , Lukasz Luba , Ulf Hansson Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-crypto@vger.kernel.org, dmaengine@vger.kernel.org, linux-mmc@vger.kernel.org, Luca Weiss X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1752393945; l=994; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=yPJZUHzJ6XbbvDpc1ODgE88aN81oenBu6+oDbLZi6Fw=; b=ymzq2LdMSZzjV86mE+IAARRAmbShVDeXvVgWjbmxw1Q6I+K7W0/9mujh7mmVhB2ZPk3JCIpSp C8m500WFnKfDTPHOjcBz48HP3rjsUZ2kL+OAwZmfz//lxGpiwkj5SEo X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= Document the Milos-based The Fairphone (Gen. 6) smartphone. Signed-off-by: Luca Weiss Acked-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/arm/qcom.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentatio= n/devicetree/bindings/arm/qcom.yaml index 56f78f0f3803fedcb6422efd6adec3bbc81c2e03..38871129f8a271bd5005a01f174= ff5127a3faefa 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -34,6 +34,7 @@ description: | ipq8074 ipq9574 mdm9615 + milos msm8226 msm8660 msm8916 @@ -155,6 +156,11 @@ properties: - qcom,apq8084-sbc - const: qcom,apq8084 =20 + - items: + - enum: + - fairphone,fp6 + - const: qcom,milos + - items: - enum: - microsoft,dempsey --=20 2.50.1 From nobody Tue Oct 7 07:06:06 2025 Received: from mail-wr1-f51.google.com (mail-wr1-f51.google.com [209.85.221.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 06979205AB6 for ; Sun, 13 Jul 2025 08:08:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752394091; cv=none; b=tk8aaKE9l7fLJR6l+sW66AXUsAkGTr0G96x200rlgNNw89A1r1Q9VDeK/BILOzR3ODGajCt0G+hsGpz7moMj0Q0sUr6qm5A4F0c1wuVYmqUeAorYyMFj6ZtRRWS+MYSnZi9xRLsQQu6QOWzEEx3CBf5cOsfLlv/d0Xtq8IHFAvg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752394091; c=relaxed/simple; bh=TDGLdncjHrRfwJLeRJx0srg3hwRbkzZPPtbM9rMrBJ0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=DOZU20YaySx8Y/wx8IlB610cY4XRYrkq4t9/Kc9hOHtKZ3WNTegnDcGoe7f+nBAHycz38ridaLaxo+dUMd3HT8X+jaBDqJJUiwcPYMONxXsYm7zhB0ctA2jJFNxa8oj/x9+Y4dew5T/b1isu7DaBrFdTK/KQVbI7hJZH0vTL0dU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=fairphone.com; spf=pass smtp.mailfrom=fairphone.com; dkim=pass (2048-bit key) header.d=fairphone.com header.i=@fairphone.com header.b=sMgAMuon; arc=none smtp.client-ip=209.85.221.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=fairphone.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=fairphone.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=fairphone.com header.i=@fairphone.com header.b="sMgAMuon" Received: by mail-wr1-f51.google.com with SMTP id ffacd0b85a97d-3a51481a598so1774834f8f.3 for ; Sun, 13 Jul 2025 01:08:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fairphone.com; s=fair; t=1752394087; x=1752998887; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=H+6gXYwyTRWuBa8Md4EiJFqvKmQqpIFr/3pDxL4GvdQ=; b=sMgAMuonw8basfApNDTKqifBh9wAd7YrabsdArmen2YtJClm6aFU06A6Ruifjna74F zTILoBtEBgvkrKk4GUhN4XLyMxkj17cA+u+vOq+yb5qQlOGnKjzN0m9SYWl3f2AOnYbZ Y8ZpVyc5NgvG6YLQn8YZTl/iX08n40QWnw/+vgb7PRf7HJlQAIqF4hcA6PWiHcYJMzMw 6lP/zHqK9gr/W64ZcNrpWJ7OwuIABitZKZw512I7JkJf7Q2CtVc8PIVGq4WprUR4oNkT WCuCjfrXW2SI14xgbLxdpKL62pZn/ZUFdBMLmDsR7m70GbzvaUlORdkzaa26g2VuX2Jp +6hw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1752394087; x=1752998887; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=H+6gXYwyTRWuBa8Md4EiJFqvKmQqpIFr/3pDxL4GvdQ=; b=grexcbt3SBwJ+TxHG0UC5bjxk+taZ5Ewt6HsUEjETTbX++8yfiwFntvTEsu6Ik4ief UNVAW8ytOlPGsmWSuAYDaFvo6ldb743HYEl/ht4+souYwfQnurLV1sD7pPI9t31+1/or 6VojzGxGn2UVsYZRiwEyglwSmhqYlHzgpvBu0j1lZPA2C7Mj5K372+leEw8a7L9bVdlL DJ0hPT5dZTShMEaw/xiVSVEm5epeYINwXCW46wYnJpuIrO+Sv9GfSAaOgCPYXk6LirET PkCSwxqXgoRkmyn+AdjLBrZ/2IjqbE6SfvHDw7JKfVfZQw8g30LqZznBha6kX0oEkWOt TkNA== X-Forwarded-Encrypted: i=1; AJvYcCWgMzbiSlR9P00cJJz+DXkJdMRJZlp0gh8xdfgocWr+mD2Mn+c632EJkYJSVrK7okuB4spY1ZT9NIrVO/k=@vger.kernel.org X-Gm-Message-State: AOJu0Yx0eL29sWnh2mkn9oGJKNrrSk5pfHNyT1p4pojk2uRhTv9iKM1D JDi4WNzb8gSHqIRqguoTqvVnql7m4BV0xCTkCe1Eu8JOY79kDdFQrCRAQh8SlfOO8vU= X-Gm-Gg: ASbGncvAr0IHTMgB+Eoxi7c6Ohxpd9rpxZ6YEwPsHTHEztFU33rm+XWn5idjbeevQdE GLJjJHnW3GF69O+bGht/AlicVa2Cjt5haDYkRsGqKoTRlMz49RhdOFcgwiRjkFwuB+EH0qaPzXu tZ2oT7sfKp3Bw0czedqYAySKM8SXzo1lYfFcjT3Zwqo8Ne+lBw8PgqeFyzmauOPfrEn3mHiltgu dVk7Ubuy1HoPxbnaza4TuiLAMOTa5b3q9Bi17boqkHkHe+gdoLd8De+rYg9ImqHjxTWFFG3gazs 6y/aiz5kOEwm3Tv3tXbzWGwpMI3Sxyga4EfxyrnLAfHvF/zSx4+X48h/1emgCJ5Aruy9uQE6D+M irTgGTX6G6LfhxM3w8FlBdFY9b1OA7VkFNVkl X-Google-Smtp-Source: AGHT+IHlbVBRzVBx+TB+ru8FP2l2jobEeZXcX09t3vF/BFXG1VnybV1VXvA6fI2r0VYJILh3gQH2vA== X-Received: by 2002:a05:6000:4012:b0:3a4:c8c1:aed8 with SMTP id ffacd0b85a97d-3b5f2e229a9mr6323377f8f.39.1752394087188; Sun, 13 Jul 2025 01:08:07 -0700 (PDT) Received: from [192.168.224.50] ([213.208.155.167]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3b5e8dc22a8sm9386608f8f.34.2025.07.13.01.07.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Jul 2025 01:08:06 -0700 (PDT) From: Luca Weiss Date: Sun, 13 Jul 2025 10:05:35 +0200 Subject: [PATCH v2 13/15] arm64: dts: qcom: pm8550vs: Disable different PMIC SIDs by default Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250713-sm7635-fp6-initial-v2-13-e8f9a789505b@fairphone.com> References: <20250713-sm7635-fp6-initial-v2-0-e8f9a789505b@fairphone.com> In-Reply-To: <20250713-sm7635-fp6-initial-v2-0-e8f9a789505b@fairphone.com> To: Will Deacon , Robin Murphy , Joerg Roedel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , "Rafael J. Wysocki" , Viresh Kumar , Manivannan Sadhasivam , Herbert Xu , "David S. Miller" , Vinod Koul , Bjorn Andersson , Konrad Dybcio , Robert Marko , Das Srinagesh , Thomas Gleixner , Jassi Brar , Amit Kucheria , Thara Gopinath , Daniel Lezcano , Zhang Rui , Lukasz Luba , Ulf Hansson Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-crypto@vger.kernel.org, dmaengine@vger.kernel.org, linux-mmc@vger.kernel.org, Luca Weiss X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1752393945; l=8108; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=TDGLdncjHrRfwJLeRJx0srg3hwRbkzZPPtbM9rMrBJ0=; b=7/Ta1AVjfApt3ZZgioiKcM9HcANPYIqXuA2LD86TP3WHJJEb5D6A6bd7fmkfxJZCxeY/WKqID y4uY7T/4HGWCJqYS2e5Ga+XlN8dfeKNnzax7x/f1PVibKRdXAhFmgrx X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= Keep the different PMIC definitions in pm8550vs.dtsi disabled by default, and only enable them in boards explicitly. This allows to support boards better which only have pm8550vs_c, like the Milos/SM7635-based Fairphone (Gen. 6). Note: I assume that at least some of these devices with PM8550VS also don't have _c, _d, _e and _g, but this patch is keeping the resulting devicetree the same as before this change, disabling them on boards that don't actually have those is out of scope for this patch. Signed-off-by: Luca Weiss Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/pm8550vs.dtsi | 8 ++++++++ arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi | 16 ++++++++++++= ++++ arch/arm64/boot/dts/qcom/sm8550-hdk.dts | 16 ++++++++++++= ++++ arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 16 ++++++++++++= ++++ arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 16 ++++++++++++= ++++ arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts | 16 ++++++++++++= ++++ .../boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts | 16 ++++++++++++= ++++ arch/arm64/boot/dts/qcom/sm8650-hdk.dts | 16 ++++++++++++= ++++ arch/arm64/boot/dts/qcom/sm8650-mtp.dts | 16 ++++++++++++= ++++ arch/arm64/boot/dts/qcom/sm8650-qrd.dts | 16 ++++++++++++= ++++ 10 files changed, 152 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/pm8550vs.dtsi b/arch/arm64/boot/dts/q= com/pm8550vs.dtsi index 6426b431616bde2d960780be2bed4c623af246c2..7b5898c263ad8a687e8c914fbb0= 072c58799b6b2 100644 --- a/arch/arm64/boot/dts/qcom/pm8550vs.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8550vs.dtsi @@ -98,6 +98,8 @@ pm8550vs_c: pmic@2 { #address-cells =3D <1>; #size-cells =3D <0>; =20 + status =3D "disabled"; + pm8550vs_c_temp_alarm: temp-alarm@a00 { compatible =3D "qcom,spmi-temp-alarm"; reg =3D <0xa00>; @@ -122,6 +124,8 @@ pm8550vs_d: pmic@3 { #address-cells =3D <1>; #size-cells =3D <0>; =20 + status =3D "disabled"; + pm8550vs_d_temp_alarm: temp-alarm@a00 { compatible =3D "qcom,spmi-temp-alarm"; reg =3D <0xa00>; @@ -146,6 +150,8 @@ pm8550vs_e: pmic@4 { #address-cells =3D <1>; #size-cells =3D <0>; =20 + status =3D "disabled"; + pm8550vs_e_temp_alarm: temp-alarm@a00 { compatible =3D "qcom,spmi-temp-alarm"; reg =3D <0xa00>; @@ -170,6 +176,8 @@ pm8550vs_g: pmic@6 { #address-cells =3D <1>; #size-cells =3D <0>; =20 + status =3D "disabled"; + pm8550vs_g_temp_alarm: temp-alarm@a00 { compatible =3D "qcom,spmi-temp-alarm"; reg =3D <0xa00>; diff --git a/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi b/arch/arm64/boot= /dts/qcom/qcs8550-aim300.dtsi index e6ac529e6b7216ac4b9e10900c5ddc9a06c9011c..e6ebb643203b62ba0050d119305= 76023207a2e35 100644 --- a/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi @@ -366,6 +366,22 @@ &pm8550b_eusb2_repeater { vdd3-supply =3D <&vreg_l5b_3p1>; }; =20 +&pm8550vs_c { + status =3D "okay"; +}; + +&pm8550vs_d { + status =3D "okay"; +}; + +&pm8550vs_e { + status =3D "okay"; +}; + +&pm8550vs_g { + status =3D "okay"; +}; + &sleep_clk { clock-frequency =3D <32764>; }; diff --git a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts b/arch/arm64/boot/dts/= qcom/sm8550-hdk.dts index 9dfb248f9ab52b354453cf42c09d93bbee99214f..ae90b59172d845be9778901f979= d579750511dcc 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts @@ -1111,6 +1111,22 @@ &pm8550b_eusb2_repeater { vdd3-supply =3D <&vreg_l5b_3p1>; }; =20 +&pm8550vs_c { + status =3D "okay"; +}; + +&pm8550vs_d { + status =3D "okay"; +}; + +&pm8550vs_e { + status =3D "okay"; +}; + +&pm8550vs_g { + status =3D "okay"; +}; + &pon_pwrkey { status =3D "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/= qcom/sm8550-mtp.dts index fdcecd41297d6ebc81c5088472e4731ca0782fcb..7e0ff2f1c7cd56754e6df6f3663= 4070b19ecf953 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts @@ -793,6 +793,22 @@ &pm8550b_eusb2_repeater { vdd3-supply =3D <&vreg_l5b_3p1>; }; =20 +&pm8550vs_c { + status =3D "okay"; +}; + +&pm8550vs_d { + status =3D "okay"; +}; + +&pm8550vs_e { + status =3D "okay"; +}; + +&pm8550vs_g { + status =3D "okay"; +}; + &qupv3_id_0 { status =3D "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/= qcom/sm8550-qrd.dts index 49438a7e77ceaab9506158855b6262206bca94ec..594178ec9d3372ec657e08713a0= ab2b620fc2b48 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts @@ -961,6 +961,22 @@ &pm8550b_eusb2_repeater { vdd3-supply =3D <&vreg_l5b_3p1>; }; =20 +&pm8550vs_c { + status =3D "okay"; +}; + +&pm8550vs_d { + status =3D "okay"; +}; + +&pm8550vs_e { + status =3D "okay"; +}; + +&pm8550vs_g { + status =3D "okay"; +}; + &pon_pwrkey { status =3D "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts b/arch/arm64/b= oot/dts/qcom/sm8550-samsung-q5q.dts index 7d29a57a2b540708fa88fb59e821406f400a3174..af963f506269c954e3ab629d809= 2341a9e44f86a 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts @@ -533,6 +533,22 @@ volume_up_n: volume-up-n-state { }; }; =20 +&pm8550vs_c { + status =3D "okay"; +}; + +&pm8550vs_d { + status =3D "okay"; +}; + +&pm8550vs_e { + status =3D "okay"; +}; + +&pm8550vs_g { + status =3D "okay"; +}; + &pon_pwrkey { status =3D "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts b/= arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts index d90dc7b37c4a74cbfb03c929646fda3381413084..0e6ed6fce614706590ab37eb96c= 1077622d0d532 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts @@ -661,6 +661,22 @@ focus_n: focus-n-state { }; }; =20 +&pm8550vs_c { + status =3D "okay"; +}; + +&pm8550vs_d { + status =3D "okay"; +}; + +&pm8550vs_e { + status =3D "okay"; +}; + +&pm8550vs_g { + status =3D "okay"; +}; + &pm8550vs_g_gpios { cam_pwr_a_cs: cam-pwr-a-cs-state { pins =3D "gpio4"; diff --git a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts b/arch/arm64/boot/dts/= qcom/sm8650-hdk.dts index d0912735b54e5090f9f213c2c9341e03effbbbff..19284298d64dfb39bab5355fd98= f64b03931c998 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts @@ -1046,6 +1046,22 @@ &pm8550b_eusb2_repeater { vdd3-supply =3D <&vreg_l5b_3p1>; }; =20 +&pm8550vs_c { + status =3D "okay"; +}; + +&pm8550vs_d { + status =3D "okay"; +}; + +&pm8550vs_e { + status =3D "okay"; +}; + +&pm8550vs_g { + status =3D "okay"; +}; + &pmk8550_rtc { status =3D "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts b/arch/arm64/boot/dts/= qcom/sm8650-mtp.dts index 76ef43c10f77d8329ccf0a05c9d590a46372315f..ebc9b4b7bd881f8d9098d1a8b3a= c281e9c94313b 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-mtp.dts @@ -688,6 +688,22 @@ &pm8550b_eusb2_repeater { vdd3-supply =3D <&vreg_l5b_3p1>; }; =20 +&pm8550vs_c { + status =3D "okay"; +}; + +&pm8550vs_d { + status =3D "okay"; +}; + +&pm8550vs_e { + status =3D "okay"; +}; + +&pm8550vs_g { + status =3D "okay"; +}; + &qupv3_id_1 { status =3D "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts b/arch/arm64/boot/dts/= qcom/sm8650-qrd.dts index 71033fba21b56bc63620dca3e453c14191739675..97e29b8039d508e343c3136e61b= 237c7e9111aec 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts @@ -1002,6 +1002,22 @@ &pm8550b_eusb2_repeater { vdd3-supply =3D <&vreg_l5b_3p1>; }; =20 +&pm8550vs_c { + status =3D "okay"; +}; + +&pm8550vs_d { + status =3D "okay"; +}; + +&pm8550vs_e { + status =3D "okay"; +}; + +&pm8550vs_g { + status =3D "okay"; +}; + &pmk8550_rtc { status =3D "okay"; }; --=20 2.50.1 From nobody Tue Oct 7 07:06:06 2025 Received: from mail-wr1-f45.google.com (mail-wr1-f45.google.com [209.85.221.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5B4751F417B for ; Sun, 13 Jul 2025 08:08:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.45 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752394110; cv=none; b=HB39O75HrIF04rVf5957Z52//NBkCxMI2iQLv0mDfJfEUQbM4SjYooDKaIOGsbM69H8ZZvbRnKXRnB2mamqjVx6aMh0yPsAUZj8Bw/SveRN17bzCyoakIoFrjjEDQ+wZHdssQPrKwtBN7v7XxDg2+y78C5XnX7nKhG/zldG8MVI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752394110; c=relaxed/simple; bh=UFGPnJmOfICp22mcO8QbWbCLwewER49nJAY+BBcMOoM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=IjlKU3P/Aj/fsWONE3uO89wg65Lcz2krEYZng80hp7qMC2HR+pGQyNuFTwzG/4hvyAHMcymDvuGbvVN+ZER9E+8UM9RMC3hnWpxSjcPzfYjmImEDwnj4Z7D32bEExFoXP9R56aK8iXy3StU0PH+ZpIHCQfpFiFTyVAFdIDA35po= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=fairphone.com; spf=pass smtp.mailfrom=fairphone.com; dkim=pass (2048-bit key) header.d=fairphone.com header.i=@fairphone.com header.b=PwtsDcsM; arc=none smtp.client-ip=209.85.221.45 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=fairphone.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=fairphone.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=fairphone.com header.i=@fairphone.com header.b="PwtsDcsM" Received: by mail-wr1-f45.google.com with SMTP id ffacd0b85a97d-3a575a988f9so1933667f8f.0 for ; Sun, 13 Jul 2025 01:08:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fairphone.com; s=fair; t=1752394104; x=1752998904; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=ty+BqSFipnBYMiZcC7yJYfZ6Y8LTZraIsrsqcZq5EvY=; b=PwtsDcsM7og1M9FVM6KgZske7TX4rhxByIqgj7t0jZWf48aZHt1rt24aa4hbJsY4Ka +cu8kXHafci1Zy9ec6dsoqPE6SWXqNRlugroG9KcZS/CAZf9GuFwDNqBGF/KEsExkiWU IvF1/KM/hIJJdfw74QwF0yRlLwWtudQRb7ovhqqz3vfieBvQ5lFhJ4OMurCn7ks9+P2P urRYlRbhlm6V2I/XJlHlnjyQ5LwxmXYLQCvKV7pgMSa8T0dZW3s1UFW0zoM5eVXvYdTH 0r594Ce+YveKbqgnx6rBJ2Ju7xZQbFgfVDNnSD5OH0ZWa99KwFosPgy3O5AzkfDyS9hu /Onw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1752394104; x=1752998904; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ty+BqSFipnBYMiZcC7yJYfZ6Y8LTZraIsrsqcZq5EvY=; b=FvsTdf6GF39qDN87vHe8i+S2sDLex0CccLrVjnKRXMIl0w0rZrNmE2L7O5CcNJFJF7 6GSXL9ydRRRbfPcNjmwjCC2pGC8+NN5Sg9FyaVVntWPHYjV4qBqIhxMVoAI/LE6qfY0Y ZES7rJan7wExRmWSUyY0mcsKs4ED7gZHIgGS+GW0jwnhrOUub25N63tCtwe52rKWljuu dslky41qEy1E2zbMYjtDC89P7AmjEiLxh5isXHXf4pHAOUOPVmW3DN0GodgLaI6841K8 NQCcOohlfm4E3LdjyBgXvPEy/AlK6TK6MBCjE2oD3pF4mtdW3Zg9kOeExGuYfnCxPpPm T6QA== X-Forwarded-Encrypted: i=1; AJvYcCVvjG2s9Yyj9seEIg1+A8/2livLlW0fpuhoMtSDccDVsuhV97nnSswZEQdLlKiurUXs1aMb2NhnmAEcgGQ=@vger.kernel.org X-Gm-Message-State: AOJu0YxbUrpTyXGesRztlHJ015hY876f2FGOlzfd+h978bnqGUn+aI1I eM6YK/enMqMSN/dTRJMPsVTbL6tXA+2IGbOfIZi2eW8vRsgOc1Ixw2oVVbPreLGaUM4= X-Gm-Gg: ASbGnctCNvwn3iWNJyUNYiRnCO9QLREEDbrDIrUwMITomAH7KLWYM5L90yJ8DiV7Trw +ootmMi0AXpiBQsJLbgd4aAPht3fI/33J9VA489O2M2d04gvD3BGu9mDISOoxVfc5KeauhDkM0J O5Ah1vpNN/Aqo+VTcxA0w9QuUHI2f1616pfUzXqQ9dJDuIc9JjGI+yyLnIIDhtwzSxq5RZFSdZu fi32hHdaE14Dt6IV3mbytLaCv2RYCPN8NVKqufPKhVW5dEpMxWPpQ4fgpbVSo9Ce2Zn2mKHJuqZ 6UsKzdyVFH+bM1hpGcqrI36FliNme1wDMWcdWvtKKVH6Y8lr9ynB57HWzBAZyG+q1r2RGMKZoce v9pFOLzi5xf6G8O4q8cm+FJgvQLCJz22+M51o X-Google-Smtp-Source: AGHT+IHsO6NgA1XVwYg7ZLfOGK9ipUjwr0jKTk4n1todptHfETJyvbBdMsdfNOJxHIIrYov2cxi20w== X-Received: by 2002:a05:6000:2888:b0:3a5:3b15:ef52 with SMTP id ffacd0b85a97d-3b5f187adbcmr7873831f8f.8.1752394103420; Sun, 13 Jul 2025 01:08:23 -0700 (PDT) Received: from [192.168.224.50] ([213.208.155.167]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3b5e8dc22a8sm9386608f8f.34.2025.07.13.01.08.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Jul 2025 01:08:22 -0700 (PDT) From: Luca Weiss Date: Sun, 13 Jul 2025 10:05:36 +0200 Subject: [PATCH v2 14/15] arm64: dts: qcom: Add initial Milos dtsi Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250713-sm7635-fp6-initial-v2-14-e8f9a789505b@fairphone.com> References: <20250713-sm7635-fp6-initial-v2-0-e8f9a789505b@fairphone.com> In-Reply-To: <20250713-sm7635-fp6-initial-v2-0-e8f9a789505b@fairphone.com> To: Will Deacon , Robin Murphy , Joerg Roedel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , "Rafael J. Wysocki" , Viresh Kumar , Manivannan Sadhasivam , Herbert Xu , "David S. Miller" , Vinod Koul , Bjorn Andersson , Konrad Dybcio , Robert Marko , Das Srinagesh , Thomas Gleixner , Jassi Brar , Amit Kucheria , Thara Gopinath , Daniel Lezcano , Zhang Rui , Lukasz Luba , Ulf Hansson Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-crypto@vger.kernel.org, dmaengine@vger.kernel.org, linux-mmc@vger.kernel.org, Luca Weiss X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1752393945; l=70070; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=UFGPnJmOfICp22mcO8QbWbCLwewER49nJAY+BBcMOoM=; b=TbvbeeavUIRhD4txoFuJ2++HXWLFoOsP6gntZl5wJNFv47EJ91fDZrvltCCpdawuQyWTKKExI W/ntFQFDDijDJhKB27r24i8ZSPfQD6EslDV8bpxrn1ia3kBqiuz/4KT X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= Add a devicetree description for the Milos SoC, which is for example Snapdragon 7s Gen 3 (SM7635). Signed-off-by: Luca Weiss --- arch/arm64/boot/dts/qcom/milos.dtsi | 2802 +++++++++++++++++++++++++++++++= ++++ 1 file changed, 2802 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/milos.dtsi b/arch/arm64/boot/dts/qcom= /milos.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..130f258828dffa937477c065c04= 97c8119c5ac0f --- /dev/null +++ b/arch/arm64/boot/dts/qcom/milos.dtsi @@ -0,0 +1,2802 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2025, Luca Weiss + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/ { + interrupt-parent =3D <&intc>; + + #address-cells =3D <2>; + #size-cells =3D <2>; + + chosen { }; + + clocks { + xo_board: xo-board { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <76800000>; + }; + + sleep_clk: sleep-clk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <32764>; + }; + }; + + cpus { + #address-cells =3D <2>; + #size-cells =3D <0>; + + cpu0: cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a520"; + reg =3D <0x0 0x0>; + + clocks =3D <&cpufreq_hw 0>; + + power-domains =3D <&cpu_pd0>; + power-domain-names =3D "psci"; + + enable-method =3D "psci"; + next-level-cache =3D <&l2_0>; + capacity-dmips-mhz =3D <1024>; + dynamic-power-coefficient =3D <100>; + + qcom,freq-domain =3D <&cpufreq_hw 0>; + + #cooling-cells =3D <2>; + + l2_0: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3_0>; + + l3_0: l3-cache { + compatible =3D "cache"; + cache-level =3D <3>; + cache-unified; + }; + }; + }; + + cpu1: cpu@100 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a520"; + reg =3D <0x0 0x100>; + + clocks =3D <&cpufreq_hw 0>; + + power-domains =3D <&cpu_pd1>; + power-domain-names =3D "psci"; + + enable-method =3D "psci"; + next-level-cache =3D <&l2_0>; + capacity-dmips-mhz =3D <1024>; + dynamic-power-coefficient =3D <100>; + + qcom,freq-domain =3D <&cpufreq_hw 0>; + + #cooling-cells =3D <2>; + }; + + cpu2: cpu@200 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a520"; + reg =3D <0x0 0x200>; + + clocks =3D <&cpufreq_hw 0>; + + power-domains =3D <&cpu_pd2>; + power-domain-names =3D "psci"; + + enable-method =3D "psci"; + next-level-cache =3D <&l2_2>; + capacity-dmips-mhz =3D <1024>; + dynamic-power-coefficient =3D <100>; + + qcom,freq-domain =3D <&cpufreq_hw 0>; + + #cooling-cells =3D <2>; + + l2_2: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3_0>; + }; + }; + + cpu3: cpu@300 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a520"; + reg =3D <0x0 0x300>; + + clocks =3D <&cpufreq_hw 0>; + + power-domains =3D <&cpu_pd3>; + power-domain-names =3D "psci"; + + enable-method =3D "psci"; + next-level-cache =3D <&l2_2>; + capacity-dmips-mhz =3D <1024>; + dynamic-power-coefficient =3D <100>; + + qcom,freq-domain =3D <&cpufreq_hw 0>; + + #cooling-cells =3D <2>; + }; + + cpu4: cpu@400 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a720"; + reg =3D <0x0 0x400>; + + clocks =3D <&cpufreq_hw 1>; + + power-domains =3D <&cpu_pd4>; + power-domain-names =3D "psci"; + + enable-method =3D "psci"; + next-level-cache =3D <&l2_4>; + capacity-dmips-mhz =3D <1670>; + dynamic-power-coefficient =3D <264>; + + qcom,freq-domain =3D <&cpufreq_hw 1>; + + #cooling-cells =3D <2>; + + l2_4: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3_0>; + }; + }; + + cpu5: cpu@500 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a720"; + reg =3D <0x0 0x500>; + + clocks =3D <&cpufreq_hw 1>; + + power-domains =3D <&cpu_pd5>; + power-domain-names =3D "psci"; + + enable-method =3D "psci"; + next-level-cache =3D <&l2_5>; + capacity-dmips-mhz =3D <1670>; + dynamic-power-coefficient =3D <264>; + + qcom,freq-domain =3D <&cpufreq_hw 1>; + + #cooling-cells =3D <2>; + + l2_5: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3_0>; + }; + }; + + cpu6: cpu@600 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a720"; + reg =3D <0x0 0x600>; + + clocks =3D <&cpufreq_hw 1>; + + power-domains =3D <&cpu_pd6>; + power-domain-names =3D "psci"; + + enable-method =3D "psci"; + next-level-cache =3D <&l2_6>; + capacity-dmips-mhz =3D <1670>; + dynamic-power-coefficient =3D <264>; + + qcom,freq-domain =3D <&cpufreq_hw 1>; + + #cooling-cells =3D <2>; + + l2_6: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3_0>; + }; + }; + + cpu7: cpu@700 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a720"; + reg =3D <0x0 0x700>; + + clocks =3D <&cpufreq_hw 2>; + + power-domains =3D <&cpu_pd7>; + power-domain-names =3D "psci"; + + enable-method =3D "psci"; + next-level-cache =3D <&l2_7>; + capacity-dmips-mhz =3D <1670>; + dynamic-power-coefficient =3D <287>; + + qcom,freq-domain =3D <&cpufreq_hw 2>; + + #cooling-cells =3D <2>; + + l2_7: l2-cache { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&l3_0>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu =3D <&cpu0>; + }; + + core1 { + cpu =3D <&cpu1>; + }; + + core2 { + cpu =3D <&cpu2>; + }; + + core3 { + cpu =3D <&cpu3>; + }; + }; + + cluster1 { + core0 { + cpu =3D <&cpu4>; + }; + + core1 { + cpu =3D <&cpu5>; + }; + + core2 { + cpu =3D <&cpu6>; + }; + }; + + cluster2 { + core0 { + cpu =3D <&cpu7>; + }; + }; + }; + + idle-states { + entry-method =3D "psci"; + + silver_cpu_sleep_0: cpu-sleep-0-0 { + compatible =3D "arm,idle-state"; + idle-state-name =3D "pc"; + arm,psci-suspend-param =3D <0x40000003>; + entry-latency-us =3D <250>; + exit-latency-us =3D <700>; + min-residency-us =3D <5200>; + local-timer-stop; + }; + + silver_cpu_sleep_1: cpu-sleep-0-1 { + compatible =3D "arm,idle-state"; + idle-state-name =3D "silver-rail-power-collapse"; + arm,psci-suspend-param =3D <0x40000004>; + entry-latency-us =3D <550>; + exit-latency-us =3D <750>; + min-residency-us =3D <6700>; + local-timer-stop; + }; + + gold_cpu_sleep_0: cpu-sleep-1-0 { + compatible =3D "arm,idle-state"; + idle-state-name =3D "silver-power-collapse"; + arm,psci-suspend-param =3D <0x40000003>; + entry-latency-us =3D <400>; + exit-latency-us =3D <900>; + min-residency-us =3D <5511>; + local-timer-stop; + }; + + gold_cpu_sleep_1: cpu-sleep-1-1 { + compatible =3D "arm,idle-state"; + idle-state-name =3D "gold-rail-power-collapse"; + arm,psci-suspend-param =3D <0x40000004>; + entry-latency-us =3D <600>; + exit-latency-us =3D <1300>; + min-residency-us =3D <8136>; + local-timer-stop; + }; + + gold_plus_cpu_sleep_0: cpu-sleep-2-0 { + compatible =3D "arm,idle-state"; + idle-state-name =3D "gold-plus-rail-power-collapse"; + arm,psci-suspend-param =3D <0x40000004>; + entry-latency-us =3D <600>; + exit-latency-us =3D <1500>; + min-residency-us =3D <8551>; + local-timer-stop; + }; + }; + + domain-idle-states { + cluster_sleep_0: cluster-sleep-0 { + compatible =3D "domain-idle-state"; + arm,psci-suspend-param =3D <0x41000044>; + entry-latency-us =3D <750>; + exit-latency-us =3D <2350>; + min-residency-us =3D <9144>; + }; + + cluster_sleep_1: cluster-sleep-1 { + compatible =3D "domain-idle-state"; + arm,psci-suspend-param =3D <0x41003344>; + entry-latency-us =3D <2800>; + exit-latency-us =3D <4400>; + min-residency-us =3D <10150>; + }; + }; + }; + + firmware { + scm: scm { + compatible =3D "qcom,scm-milos", "qcom,scm"; + qcom,dload-mode =3D <&tcsr 0x19000>; + }; + }; + + clk_virt: interconnect-0 { + compatible =3D "qcom,milos-clk-virt"; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + mc_virt: interconnect-1 { + compatible =3D "qcom,milos-mc-virt"; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + memory@0 { + device_type =3D "memory"; + /* We expect the bootloader to fill in the size */ + reg =3D <0 0 0 0>; + }; + + pmu-a520 { + compatible =3D "arm,cortex-a520-pmu"; + interrupts =3D ; + }; + + pmu-a720 { + compatible =3D "arm,cortex-a720-pmu"; + interrupts =3D ; + }; + + psci { + compatible =3D "arm,psci-1.0"; + method =3D "smc"; + + cpu_pd0: power-domain-cpu0 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&silver_cpu_sleep_0>, <&silver_cpu_sleep_1>; + }; + + cpu_pd1: power-domain-cpu1 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&silver_cpu_sleep_0>, <&silver_cpu_sleep_1>; + }; + + cpu_pd2: power-domain-cpu2 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&silver_cpu_sleep_0>, <&silver_cpu_sleep_1>; + }; + + cpu_pd3: power-domain-cpu3 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&silver_cpu_sleep_0>, <&silver_cpu_sleep_1>; + }; + + cpu_pd4: power-domain-cpu4 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&gold_cpu_sleep_0>, <&gold_cpu_sleep_1>; + }; + + cpu_pd5: power-domain-cpu5 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&gold_cpu_sleep_0>, <&gold_cpu_sleep_1>; + }; + + cpu_pd6: power-domain-cpu6 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&gold_cpu_sleep_0>, <&gold_cpu_sleep_1>; + }; + + cpu_pd7: power-domain-cpu7 { + #power-domain-cells =3D <0>; + power-domains =3D <&cluster_pd>; + domain-idle-states =3D <&gold_plus_cpu_sleep_0>; + }; + + cluster_pd: power-domain-cluster { + #power-domain-cells =3D <0>; + domain-idle-states =3D <&cluster_sleep_0>, <&cluster_sleep_1>; + }; + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + gunyah_hyp_mem: gunyah-hyp-region@80000000 { + reg =3D <0x0 0x80000000 0x0 0xe00000>; + no-map; + }; + + xbl_sc_mem: xbl-sc-region@81800000 { + reg =3D <0x0 0x81800000 0x0 0x40000>; + no-map; + }; + + cpucp_fw_mem: cpucp-fw-region@81840000 { + reg =3D <0x0 0x81840000 0x0 0x1c0000>; + no-map; + }; + + xbl_dtlog_mem: xbl-dtlog-region@81a00000 { + reg =3D <0x0 0x81a00000 0x0 0x40000>; + no-map; + }; + + xbl_ramdump_mem: xbl-ramdump-region@81a40000 { + reg =3D <0x0 0x81a40000 0x0 0x1c0000>; + no-map; + }; + + aop_image_mem: aop-image-region@81c00000 { + reg =3D <0x0 0x81c00000 0x0 0x60000>; + no-map; + }; + + aop_cmd_db_mem: aop-cmd-db-region@81c60000 { + compatible =3D "qcom,cmd-db"; + reg =3D <0x0 0x81c60000 0x0 0x20000>; + no-map; + }; + + aop_config_mem: aop-config-region@81c80000 { + reg =3D <0x0 0x81c80000 0x0 0x20000>; + no-map; + }; + + tme_crash_dump_mem: tme-crash-dump-region@81ca0000 { + reg =3D <0x0 0x81ca0000 0x0 0x40000>; + no-map; + }; + + tme_log_mem: tme-log-region@81ce0000 { + reg =3D <0x0 0x81ce0000 0x0 0x4000>; + no-map; + }; + + uefi_log_mem: uefi-log-region@81ce4000 { + reg =3D <0x0 0x81ce4000 0x0 0x10000>; + no-map; + }; + + chipinfo_mem: chipinfo-region@81cf4000 { + reg =3D <0x0 0x81cf4000 0x0 0x1000>; + no-map; + }; + + secdata_apss_mem: secdata-apss-region@81cff000 { + reg =3D <0x0 0x81cff000 0x0 0x1000>; + no-map; + }; + + smem_mem: smem-region@81d00000 { + compatible =3D "qcom,smem"; + reg =3D <0x0 0x81d00000 0x0 0x200000>; + hwlocks =3D <&tcsr_mutex 3>; + no-map; + }; + + adsp_mhi_mem: adsp-mhi-region@81f00000 { + reg =3D <0x0 0x81f00000 0x0 0x20000>; + no-map; + }; + + pvm_fw_mem: pvm-fw-region@824a0000 { + reg =3D <0x0 0x824a0000 0x0 0x100000>; + no-map; + }; + + hyp_mem_database_mem: hyp-mem-database-region@825a0000 { + reg =3D <0x0 0x825a0000 0x0 0x60000>; + no-map; + }; + + global_sync_mem: global-sync-region@82600000 { + reg =3D <0x0 0x82600000 0x0 0x100000>; + no-map; + }; + + tz_stat_mem: tz-stat-region@82700000 { + reg =3D <0x0 0x82700000 0x0 0x100000>; + no-map; + }; + + qdss_apps_mem: qdss-apps-region@82800000 { + reg =3D <0x0 0x82800000 0x0 0x2000000>; + reusable; + }; + + mpss_mem: mpss-region@8ac00000 { + reg =3D <0x0 0x8ac00000 0x0 0xe600000>; + no-map; + }; + + q6_mpss_dtb_mem: q6-mpss-dtb-region@99200000 { + reg =3D <0x0 0x99200000 0x0 0x80000>; + no-map; + }; + + q6_adsp_dtb_mem: q6-adsp-dtb-region@99280000 { + reg =3D <0x0 0x99280000 0x0 0x80000>; + no-map; + }; + + adspslpi_mem: adspslpi-region@99300000 { + reg =3D <0x0 0x99300000 0x0 0x2800000>; + no-map; + }; + + wpss_mem: wpss-region@9bb00000 { + reg =3D <0x0 0x9bb00000 0x0 0x1900000>; + no-map; + }; + + video_mem: video-region@9d400000 { + reg =3D <0x0 0x9d400000 0x0 0x700000>; + no-map; + }; + + cdsp_mem: cdsp-region@9db00000 { + reg =3D <0x0 0x9db00000 0x0 0xf00000>; + no-map; + }; + + q6_cdsp_dtb_mem: q6-cdsp-dtb-region@9ea00000 { + reg =3D <0x0 0x9ea00000 0x0 0x80000>; + no-map; + }; + + ipa_fw_mem: ipa-fw-region@9ea80000 { + reg =3D <0x0 0x9ea80000 0x0 0x10000>; + no-map; + }; + + ipa_gsi_mem: ipa-gsi-region@9ea90000 { + reg =3D <0x0 0x9ea90000 0x0 0xa000>; + no-map; + }; + + gpu_microcode_mem: gpu-microcode-region@9ea9a000 { + reg =3D <0x0 0x9ea9a000 0x0 0x2000>; + no-map; + }; + + camera_mem: camera-region@9eb00000 { + reg =3D <0x0 0x9eb00000 0x0 0x800000>; + no-map; + }; + + wlan_msa_mem: wlan-msa-region@a6400000 { + reg =3D <0x0 0xa6400000 0x0 0xc00000>; + no-map; + }; + + cpusys_vm_mem: cpusys-vm-region@e0600000 { + reg =3D <0x0 0xe0600000 0x0 0x400000>; + no-map; + }; + + rmtfs_mem: rmtfs@e1f00000 { + compatible =3D "qcom,rmtfs-mem"; + reg =3D <0x0 0xe1f00000 0x0 0x600000>; + no-map; + + qcom,client-id =3D <1>; + qcom,vmid =3D ; + }; + + qtee_mem: qtee-region@e8900000 { + reg =3D <0x0 0xe8900000 0x0 0x500000>; + no-map; + }; + + tags_mem: tags-region@e8e00000 { + reg =3D <0x0 0xe8e00000 0x0 0x700000>; + no-map; + }; + + trusted_apps_mem: trusted-apps-region@e9500000 { + reg =3D <0x0 0xe9500000 0x0 0x1200000>; + no-map; + }; + }; + + smp2p-adsp { + compatible =3D "qcom,smp2p"; + qcom,smem =3D <443>, <429>; + interrupts-extended =3D <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes =3D <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,local-pid =3D <0>; + qcom,remote-pid =3D <2>; + + smp2p_adsp_out: master-kernel { + qcom,entry-name =3D "master-kernel"; + #qcom,smem-state-cells =3D <1>; + }; + + smp2p_adsp_in: slave-kernel { + qcom,entry-name =3D "slave-kernel"; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + smp2p-cdsp { + compatible =3D "qcom,smp2p"; + qcom,smem =3D <94>, <432>; + interrupts-extended =3D <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes =3D <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,local-pid =3D <0>; + qcom,remote-pid =3D <5>; + + smp2p_cdsp_out: master-kernel { + qcom,entry-name =3D "master-kernel"; + #qcom,smem-state-cells =3D <1>; + }; + + smp2p_cdsp_in: slave-kernel { + qcom,entry-name =3D "slave-kernel"; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + smp2p-modem { + compatible =3D "qcom,smp2p"; + qcom,smem =3D <435>, <428>; + interrupts-extended =3D <&ipcc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes =3D <&ipcc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,local-pid =3D <0>; + qcom,remote-pid =3D <1>; + + smp2p_modem_out: master-kernel { + qcom,entry-name =3D "master-kernel"; + #qcom,smem-state-cells =3D <1>; + }; + + smp2p_modem_in: slave-kernel { + qcom,entry-name =3D "slave-kernel"; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + smp2p_ipa_out: ipa-ap-to-modem { + qcom,entry-name =3D "ipa"; + #qcom,smem-state-cells =3D <1>; + }; + + smp2p_ipa_in: ipa-modem-to-ap { + qcom,entry-name =3D "ipa"; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + smp2p-wpss { + compatible =3D "qcom,smp2p"; + qcom,smem =3D <617>, <616>; + interrupts-extended =3D <&ipcc IPCC_CLIENT_WPSS + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + mboxes =3D <&ipcc IPCC_CLIENT_WPSS + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,local-pid =3D <0>; + qcom,remote-pid =3D <13>; + + smp2p_wpss_out: master-kernel { + qcom,entry-name =3D "master-kernel"; + #qcom,smem-state-cells =3D <1>; + }; + + smp2p_wpss_in: slave-kernel { + qcom,entry-name =3D "slave-kernel"; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + smp2p_wlan_out: wlan-ap-to-wpss { + qcom,entry-name =3D "wlan"; + #qcom,smem-state-cells =3D <1>; + }; + + smp2p_wlan_in: wlan-wpss-to-ap { + qcom,entry-name =3D "wlan"; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + }; + + soc: soc@0 { + compatible =3D "simple-bus"; + + #address-cells =3D <2>; + #size-cells =3D <2>; + dma-ranges =3D <0 0 0 0 0x10 0>; + ranges =3D <0 0 0 0 0x10 0>; + + gcc: clock-controller@100000 { + compatible =3D "qcom,milos-gcc"; + reg =3D <0x0 0x00100000 0x0 0x1f4200>; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>, + <0>, /* pcie_0_pipe_clk */ + <0>, /* pcie_1_pipe_clk */ + <0>, /* ufs_phy_rx_symbol_0_clk */ + <0>, /* ufs_phy_rx_symbol_1_clk */ + <0>, /* ufs_phy_tx_symbol_0_clk */ + <0>; /* usb3_phy_wrapper_gcc_usb30_pipe_clk */ + protected-clocks =3D , , + , , + , , + , , + , , + , ; + + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + + ipcc: mailbox@405000 { + compatible =3D "qcom,milos-ipcc", "qcom,ipcc"; + reg =3D <0x0 0x00405000 0x0 0x1000>; + + interrupts =3D ; + interrupt-controller; + #interrupt-cells =3D <3>; + + #mbox-cells =3D <2>; + }; + + gpi_dma1: dma-controller@800000 { + compatible =3D "qcom,milos-gpi-dma", "qcom,sm6350-gpi-dma"; + reg =3D <0x0 0x00800000 0x0 0x60000>; + + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + ; + + dma-channels =3D <12>; + dma-channel-mask =3D <0x3f>; + #dma-cells =3D <3>; + + iommus =3D <&apps_smmu 0x36 0x0>; + dma-coherent; + }; + + qupv3_id_1: geniqup@8c0000 { + compatible =3D "qcom,geni-se-qup"; + reg =3D <0x0 0x008c0000 0x0 0x2000>; + + clocks =3D <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + clock-names =3D "m-ahb", + "s-ahb"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core"; + + iommus =3D <&apps_smmu 0x23 0>; + + dma-coherent; + + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + status =3D "disabled"; + + i2c7: i2c@880000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00880000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &cnoc_cfg SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + + dmas =3D <&gpi_dma1 0 0 QCOM_GPI_I2C>, + <&gpi_dma1 1 0 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_i2c7_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + uart11: serial@890000 { + compatible =3D "qcom,geni-uart"; + reg =3D <0x0 0x00890000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &cnoc_cfg SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "qup-core", + "qup-config"; + + pinctrl-0 =3D <&qup_uart11_default>, <&qup_uart11_cts_rts>; + pinctrl-names =3D "default"; + + status =3D "disabled"; + }; + }; + + gpi_dma0: dma-controller@a00000 { + compatible =3D "qcom,milos-gpi-dma", "qcom,sm6350-gpi-dma"; + reg =3D <0x0 0x00a00000 0x0 0x60000>; + + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + ; + + dma-channels =3D <12>; + dma-channel-mask =3D <0x3e>; + #dma-cells =3D <3>; + + iommus =3D <&apps_smmu 0x576 0x0>; + dma-coherent; + }; + + qupv3_id_0: geniqup@ac0000 { + compatible =3D "qcom,geni-se-qup"; + reg =3D <0x0 0x00ac0000 0x0 0x2000>; + + clocks =3D <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + clock-names =3D "m-ahb", + "s-ahb"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core"; + + iommus =3D <&apps_smmu 0x563 0>; + + dma-coherent; + + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + status =3D "disabled"; + + spi0: spi@a80000 { + compatible =3D "qcom,geni-spi"; + reg =3D <0x0 0x00a80000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &cnoc_cfg SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + + dmas =3D <&gpi_dma0 0 0 QCOM_GPI_SPI>, + <&gpi_dma0 1 0 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_spi0_data_clk>, <&qup_spi0_cs>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + i2c1: i2c@a84000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00a84000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &cnoc_cfg SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + + dmas =3D <&gpi_dma0 0 1 QCOM_GPI_I2C>, + <&gpi_dma0 1 1 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_i2c1_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + i2c3: i2c@a8c000 { + compatible =3D "qcom,geni-i2c"; + reg =3D <0x0 0x00a8c000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &cnoc_cfg SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names =3D "qup-core", + "qup-config", + "qup-memory"; + + dmas =3D <&gpi_dma0 0 3 QCOM_GPI_I2C>, + <&gpi_dma0 1 3 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + + pinctrl-0 =3D <&qup_i2c3_data_clk>; + pinctrl-names =3D "default"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + }; + + uart5: serial@a94000 { + compatible =3D "qcom,geni-debug-uart"; + reg =3D <0x0 0x00a94000 0x0 0x4000>; + + interrupts =3D ; + + clocks =3D <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + clock-names =3D "se"; + + interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &cnoc_cfg SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "qup-core", + "qup-config"; + + pinctrl-0 =3D <&qup_uart5_default>; + pinctrl-names =3D "default"; + + status =3D "disabled"; + }; + }; + + rng: rng@10c3000 { + compatible =3D "qcom,milos-trng", "qcom,trng"; + reg =3D <0x0 0x010c3000 0x0 0x1000>; + }; + + mmss_noc: interconnect@1400000 { + compatible =3D "qcom,milos-mmss-noc"; + reg =3D <0x0 0x01400000 0x0 0xdb800>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + cnoc_main: interconnect@1500000 { + compatible =3D "qcom,milos-cnoc-main"; + reg =3D <0x0 0x01500000 0x0 0x14400>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + cnoc_cfg: interconnect@1600000 { + compatible =3D "qcom,milos-cnoc-cfg"; + reg =3D <0x0 0x01600000 0x0 0x6e00>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + system_noc: interconnect@1680000 { + compatible =3D "qcom,milos-system-noc"; + reg =3D <0x0 0x01680000 0x0 0x40000>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + pcie_anoc: interconnect@16c0000 { + compatible =3D "qcom,milos-pcie-anoc"; + reg =3D <0x0 0x016c0000 0x0 0x12400>; + #interconnect-cells =3D <2>; + clocks =3D <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, + <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + aggre1_noc: interconnect@16e0000 { + compatible =3D "qcom,milos-aggre1-noc"; + reg =3D <0x0 0x016e0000 0x0 0x16400>; + #interconnect-cells =3D <2>; + clocks =3D <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + aggre2_noc: interconnect@1700000 { + compatible =3D "qcom,milos-aggre2-noc"; + reg =3D <0x0 0x01700000 0x0 0x1f400>; + #interconnect-cells =3D <2>; + clocks =3D <&rpmhcc RPMH_IPA_CLK>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + tcsr_mutex: hwlock@1f40000 { + compatible =3D "qcom,tcsr-mutex"; + reg =3D <0x0 0x01f40000 0x0 0x20000>; + + #hwlock-cells =3D <1>; + }; + + tcsr: clock-controller@1fc0000 { + compatible =3D "qcom,milos-tcsr", "syscon"; + reg =3D <0x0 0x01fc0000 0x0 0xa0000>; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>; + + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; + + remoteproc_adsp: remoteproc@3000000 { + compatible =3D "qcom,milos-adsp-pas"; + reg =3D <0x0 0x03000000 0x0 0x10000>; + + interrupts-extended =3D <&pdc 6 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names =3D "wdog", + "fatal", + "ready", + "handover", + "stop-ack", + "shutdown-ack"; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "xo"; + + power-domains =3D <&rpmhpd RPMHPD_LCX>, + <&rpmhpd RPMHPD_LMX>; + power-domain-names =3D "lcx", + "lmx"; + + interconnects =3D <&lpass_ag_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + + memory-region =3D <&adspslpi_mem>, <&q6_adsp_dtb_mem>; + + qcom,qmp =3D <&aoss_qmp>; + + qcom,smem-states =3D <&smp2p_adsp_out 0>; + qcom,smem-state-names =3D "stop"; + + status =3D "disabled"; + + glink-edge { + interrupts-extended =3D <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes =3D <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label =3D "lpass"; + qcom,remote-pid =3D <2>; + }; + }; + + lpass_ag_noc: interconnect@3c40000 { + compatible =3D "qcom,milos-lpass-ag-noc"; + reg =3D <0x0 0x03c40000 0x0 0x17200>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + gpucc: clock-controller@3d90000 { + compatible =3D "qcom,milos-gpucc"; + reg =3D <0x0 0x03d90000 0x0 0x9800>; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + + adreno_smmu: iommu@3da0000 { + compatible =3D "qcom,milos-smmu-500", "qcom,adreno-smmu", + "qcom,smmu-500", "arm,mmu-500"; + reg =3D <0x0 0x03da0000 0x0 0x40000>; + #iommu-cells =3D <2>; + #global-interrupts =3D <1>; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + clocks =3D <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>; + clock-names =3D "hlos", + "bus", + "iface", + "ahb"; + power-domains =3D <&gpucc GPU_CC_CX_GDSC>; + dma-coherent; + }; + + remoteproc_mpss: remoteproc@4080000 { + compatible =3D "qcom,milos-mpss-pas"; + reg =3D <0x0 0x04080000 0x0 0x10000>; + + interrupts-extended =3D <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, + <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, + <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names =3D "wdog", + "fatal", + "ready", + "handover", + "stop-ack", + "shutdown-ack"; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "xo"; + + power-domains =3D <&rpmhpd RPMHPD_CX>, + <&rpmhpd RPMHPD_MSS>; + power-domain-names =3D "cx", + "mss"; + + interconnects =3D <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + + memory-region =3D <&mpss_mem>; + + qcom,qmp =3D <&aoss_qmp>; + + qcom,smem-states =3D <&smp2p_modem_out 0>; + qcom,smem-state-names =3D "stop"; + + status =3D "disabled"; + + glink-edge { + interrupts-extended =3D <&ipcc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes =3D <&ipcc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label =3D "mpss"; + qcom,remote-pid =3D <1>; + }; + }; + + sdhc_2: mmc@8804000 { + compatible =3D "qcom,milos-sdhci", "qcom,sdhci-msm-v5"; + reg =3D <0x0 0x08804000 0x0 0x1000>; + + interrupts =3D , + ; + interrupt-names =3D "hc_irq", + "pwr_irq"; + + clocks =3D <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "iface", + "core", + "xo"; + + interconnects =3D <&aggre2_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &cnoc_cfg SLAVE_SDCC_2 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "sdhc-ddr", + "cpu-sdhc"; + + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&sdhc2_opp_table>; + + iommus =3D <&apps_smmu 0x540 0>; + + bus-width =3D <4>; + + qcom,dll-config =3D <0x0007442c>; + qcom,ddr-config =3D <0x80040868>; + + dma-coherent; + + status =3D "disabled"; + + sdhc2_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-100000000 { + opp-hz =3D /bits/ 64 <100000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-202000000 { + opp-hz =3D /bits/ 64 <202000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + usb_1_hsphy: phy@88e3000 { + compatible =3D "qcom,milos-snps-eusb2-phy", + "qcom,sm8550-snps-eusb2-phy"; + reg =3D <0x0 0x088e3000 0x0 0x154>; + #phy-cells =3D <0>; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "ref"; + + resets =3D <&gcc GCC_QUSB2PHY_PRIM_BCR>; + + status =3D "disabled"; + }; + + remoteproc_wpss: remoteproc@8a00000 { + compatible =3D "qcom,milos-wpss-pas"; + reg =3D <0x0 0x08a00000 0x0 0x10000>; + + interrupts-extended =3D <&intc GIC_SPI 579 IRQ_TYPE_EDGE_RISING>, + <&smp2p_wpss_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_wpss_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_wpss_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_wpss_in 3 IRQ_TYPE_EDGE_RISING>, + <&smp2p_wpss_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names =3D "wdog", + "fatal", + "ready", + "handover", + "stop-ack", + "shutdown-ack"; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "xo"; + + power-domains =3D <&rpmhpd RPMHPD_CX>, + <&rpmhpd RPMHPD_MX>; + power-domain-names =3D "cx", + "mx"; + + memory-region =3D <&wpss_mem>; + + qcom,qmp =3D <&aoss_qmp>; + + qcom,smem-states =3D <&smp2p_wpss_out 0>; + qcom,smem-state-names =3D "stop"; + + status =3D "disabled"; + + glink-edge { + interrupts-extended =3D <&ipcc IPCC_CLIENT_WPSS + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes =3D <&ipcc IPCC_CLIENT_WPSS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label =3D "wpss"; + qcom,remote-pid =3D <13>; + }; + }; + + usb_1: usb@a600000 { + compatible =3D "qcom,milos-dwc3", "qcom,snps-dwc3"; + reg =3D <0x0 0x0a600000 0x0 0x10000>; + + clocks =3D <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi", + "xo"; + + assigned-clocks =3D <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>; + assigned-clock-rates =3D <19200000>, <133333333>; + + interrupts-extended =3D <&intc GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 14 IRQ_TYPE_EDGE_BOTH>, + <&pdc 15 IRQ_TYPE_EDGE_BOTH>, + <&pdc 25 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names =3D "dwc_usb3", + "pwr_event", + "dp_hs_phy_irq", + "dm_hs_phy_irq", + "ss_phy_irq"; + + iommus =3D <&apps_smmu 0x40 0x0>; + power-domains =3D <&gcc USB30_PRIM_GDSC>; + required-opps =3D <&rpmhpd_opp_nom>; + + resets =3D <&gcc GCC_USB30_PRIM_BCR>; + + interconnects =3D <&aggre1_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &cnoc_cfg SLAVE_USB3_0 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "usb-ddr", "apps-usb"; + + phys =3D <&usb_1_hsphy>; + phy-names =3D "usb2-phy"; + + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,dis_enblslpm_quirk; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + snps,has-lpm-erratum; + snps,hird-threshold =3D /bits/ 8 <0x0>; + snps,is-utmi-l1-suspend; + snps,parkmode-disable-ss-quirk; + tx-fifo-resize; + dma-coherent; + usb-role-switch; + + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + usb_1_dwc3_hs: endpoint { + }; + }; + }; + }; + + videocc: clock-controller@aaf0000 { + compatible =3D "qcom,milos-videocc"; + reg =3D <0x0 0x0aaf0000 0x0 0x10000>; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>, + <&gcc GCC_VIDEO_AHB_CLK>; + + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + + camcc: clock-controller@adb0000 { + compatible =3D "qcom,milos-camcc"; + reg =3D <0x0 0x0adb0000 0x0 0x40000>; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>, + <&gcc GCC_CAMERA_AHB_CLK>; + + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + + dispcc: clock-controller@af00000 { + compatible =3D "qcom,milos-dispcc"; + reg =3D <0x0 0x0af00000 0x0 0x20000>; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>, + <&gcc GCC_DISP_AHB_CLK>, + <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, + <0>, /* dsi0_phy_pll_out_byteclk */ + <0>, /* dsi0_phy_pll_out_dsiclk */ + <0>, /* dp0_phy_pll_link_clk */ + <0>; /* dp0_phy_pll_vco_div_clk */ + + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + + pdc: interrupt-controller@b220000 { + compatible =3D "qcom,milos-pdc", "qcom,pdc"; + reg =3D <0x0 0x0b220000 0x0 0x30000>, <0x0 0x174000f0 0x0 0x64>; + interrupt-parent =3D <&intc>; + + qcom,pdc-ranges =3D <0 480 40>, <40 140 11>, <51 527 47>, + <98 609 31>, <129 63 1>, <130 716 12>, + <142 251 5>; + + #interrupt-cells =3D <2>; + interrupt-controller; + }; + + tsens0: thermal-sensor@c228000 { + compatible =3D "qcom,milos-tsens", "qcom,tsens-v2"; + reg =3D <0x0 0x0c228000 0x0 0x1ff>, /* TM */ + <0x0 0x0c222000 0x0 0x1ff>; /* SROT */ + + interrupts =3D , + ; + interrupt-names =3D "uplow", + "critical"; + + #qcom,sensors =3D <15>; + + #thermal-sensor-cells =3D <1>; + }; + + tsens1: thermal-sensor@c229000 { + compatible =3D "qcom,milos-tsens", "qcom,tsens-v2"; + reg =3D <0x0 0x0c229000 0x0 0x1ff>, /* TM */ + <0x0 0x0c223000 0x0 0x1ff>; /* SROT */ + + interrupts =3D , + ; + interrupt-names =3D "uplow", + "critical"; + + #qcom,sensors =3D <14>; + + #thermal-sensor-cells =3D <1>; + }; + + aoss_qmp: power-management@c300000 { + compatible =3D "qcom,milos-aoss-qmp", "qcom,aoss-qmp"; + reg =3D <0x0 0x0c300000 0x0 0x400>; + + interrupt-parent =3D <&ipcc>; + interrupts-extended =3D <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_= QMP + IRQ_TYPE_EDGE_RISING>; + + mboxes =3D <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; + + #clock-cells =3D <0>; + }; + + sram@c3f0000 { + compatible =3D "qcom,rpmh-stats"; + reg =3D <0x0 0x0c3f0000 0x0 0x400>; + }; + + spmi_bus: spmi@c400000 { + compatible =3D "qcom,spmi-pmic-arb"; + reg =3D <0x0 0x0c400000 0x0 0x3000>, + <0x0 0x0c500000 0x0 0x400000>, + <0x0 0x0c440000 0x0 0x80000>, + <0x0 0x0c4c0000 0x0 0x10000>, + <0x0 0x0c42d000 0x0 0x4000>; + reg-names =3D "core", + "chnls", + "obsrvr", + "intr", + "cnfg"; + + interrupts-extended =3D <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names =3D "periph_irq"; + + qcom,ee =3D <0>; + qcom,channel =3D <0>; + qcom,bus-id =3D <0>; + + interrupt-controller; + #interrupt-cells =3D <4>; + + #address-cells =3D <2>; + #size-cells =3D <0>; + }; + + tlmm: pinctrl@f100000 { + compatible =3D "qcom,milos-tlmm"; + reg =3D <0x0 0x0f100000 0x0 0x300000>; + + interrupts =3D ; + + gpio-controller; + #gpio-cells =3D <2>; + + interrupt-controller; + #interrupt-cells =3D <2>; + + gpio-ranges =3D <&tlmm 0 0 168>; + + wakeup-parent =3D <&pdc>; + + qup_i2c1_data_clk: qup-i2c1-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio4", "gpio5"; + function =3D "qup0_se1"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_i2c3_data_clk: qup-i2c3-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio15", "gpio16"; + function =3D "qup0_se3"; + drive-strength =3D <2>; + bias-pull-up =3D <2200>; + }; + + qup_i2c7_data_clk: qup-i2c7-data-clk-state { + /* SDA, SCL */ + pins =3D "gpio32", "gpio33"; + function =3D "qup1_se0"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_spi0_cs: qup-spi0-cs-state { + pins =3D "gpio3"; + function =3D "qup0_se0"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_spi0_data_clk: qup-spi0-data-clk-state { + /* MISO, MOSI, CLK */ + pins =3D "gpio0", "gpio1", "gpio2"; + function =3D "qup0_se0"; + drive-strength =3D <6>; + bias-disable; + }; + + qup_uart5_default: qup-uart5-default-state { + /* TX, RX */ + pins =3D "gpio25", "gpio26"; + function =3D "qup0_se5"; + drive-strength =3D <2>; + bias-disable; + }; + + qup_uart11_default: qup-uart11-default-state { + /* TX, RX */ + pins =3D "gpio50", "gpio51"; + function =3D "qup1_se4"; + drive-strength =3D <2>; + bias-pull-up; + }; + + qup_uart11_cts_rts: qup-uart11-cts-rts-state { + /* CTS, RTS */ + pins =3D "gpio48", "gpio49"; + function =3D "qup1_se4"; + drive-strength =3D <2>; + bias-pull-down; + }; + + sdc2_default: sdc2-default-state { + clk-pins { + pins =3D "gpio62"; + function =3D "sdc2_clk"; + drive-strength =3D <16>; + bias-disable; + }; + + cmd-pins { + pins =3D "gpio61"; + function =3D "sdc2_cmd"; + drive-strength =3D <10>; + bias-pull-up; + }; + + data-pins { + pins =3D "gpio58", "gpio57", "gpio35", "gpio34"; + function =3D "sdc2_data"; + drive-strength =3D <10>; + bias-pull-up; + }; + }; + + sdc2_sleep: sdc2-sleep-state { + clk-pins { + pins =3D "gpio62"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + cmd-pins { + pins =3D "gpio61"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + + data-pins { + pins =3D "gpio58", "gpio57", "gpio35", "gpio34"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + }; + }; + + apps_smmu: iommu@15000000 { + compatible =3D "qcom,milos-smmu-500", "qcom,smmu-500", "arm,mmu-500"; + reg =3D <0x0 0x15000000 0x0 0x100000>; + #iommu-cells =3D <2>; + #global-interrupts =3D <1>; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + dma-coherent; + }; + + intc: interrupt-controller@17100000 { + compatible =3D "arm,gic-v3"; + reg =3D <0x0 0x17100000 0x0 0x10000>, /* GICD */ + <0x0 0x17180000 0x0 0x200000>; /* GICR * 8 */ + + interrupts =3D ; + + #interrupt-cells =3D <3>; + interrupt-controller; + + #redistributor-regions =3D <1>; + redistributor-stride =3D <0 0x40000>; + + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + gic_its: msi-controller@17140000 { + compatible =3D "arm,gic-v3-its"; + reg =3D <0x0 0x17140000 0x0 0x20000>; + + msi-controller; + #msi-cells =3D <1>; + }; + }; + + timer@17420000 { + compatible =3D "arm,armv7-timer-mem"; + reg =3D <0x0 0x17420000 0x0 0x1000>; + + ranges =3D <0 0 0 0x20000000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + frame@17421000 { + reg =3D <0x17421000 0x1000>, + <0x17422000 0x1000>; + + interrupts =3D , + ; + + frame-number =3D <0>; + }; + + frame@17423000 { + reg =3D <0x17423000 0x1000>; + + interrupts =3D ; + + frame-number =3D <1>; + + status =3D "disabled"; + }; + + frame@17425000 { + reg =3D <0x17425000 0x1000>; + + interrupts =3D ; + + frame-number =3D <2>; + + status =3D "disabled"; + }; + + frame@17427000 { + reg =3D <0x17427000 0x1000>; + + interrupts =3D ; + + frame-number =3D <3>; + + status =3D "disabled"; + }; + + frame@17429000 { + reg =3D <0x17429000 0x1000>; + + interrupts =3D ; + + frame-number =3D <4>; + + status =3D "disabled"; + }; + + frame@1742b000 { + reg =3D <0x1742b000 0x1000>; + + interrupts =3D ; + + frame-number =3D <5>; + + status =3D "disabled"; + }; + + frame@1742d000 { + reg =3D <0x1742d000 0x1000>; + + interrupts =3D ; + + frame-number =3D <6>; + + status =3D "disabled"; + }; + }; + + apps_rsc: rsc@17a00000 { + compatible =3D "qcom,rpmh-rsc"; + reg =3D <0x0 0x17a00000 0x0 0x10000>, + <0x0 0x17a10000 0x0 0x10000>, + <0x0 0x17a20000 0x0 0x10000>; + reg-names =3D "drv-0", + "drv-1", + "drv-2"; + + interrupts =3D , + , + ; + + power-domains =3D <&cluster_pd>; + + qcom,tcs-offset =3D <0xd00>; + qcom,drv-id =3D <2>; + qcom,tcs-config =3D , , + , ; + + label =3D "apps_rsc"; + + apps_bcm_voter: bcm-voter { + compatible =3D "qcom,bcm-voter"; + }; + + rpmhcc: clock-controller { + compatible =3D "qcom,milos-rpmh-clk"; + + clocks =3D <&xo_board>; + clock-names =3D "xo"; + + #clock-cells =3D <1>; + }; + + rpmhpd: power-controller { + compatible =3D "qcom,milos-rpmhpd"; + #power-domain-cells =3D <1>; + operating-points-v2 =3D <&rpmhpd_opp_table>; + + rpmhpd_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + rpmhpd_opp_ret: opp-16 { + opp-level =3D ; + }; + + rpmhpd_opp_low_svs_d1: opp-56 { + opp-level =3D ; + }; + + rpmhpd_opp_low_svs: opp-64 { + opp-level =3D ; + }; + + rpmhpd_opp_svs: opp-128 { + opp-level =3D ; + }; + + rpmhpd_opp_svs_l1: opp-192 { + opp-level =3D ; + }; + + rpmhpd_opp_nom: opp-256 { + opp-level =3D ; + }; + + rpmhpd_opp_nom_l1: opp-320 { + opp-level =3D ; + }; + + rpmhpd_opp_turbo: opp-384 { + opp-level =3D ; + }; + + rpmhpd_opp_turbo_l1: opp-416 { + opp-level =3D ; + }; + }; + }; + }; + + cpufreq_hw: cpufreq@17d91000 { + compatible =3D "qcom,milos-cpufreq-epss", "qcom,cpufreq-epss"; + reg =3D <0x0 0x17d91000 0x0 0x1000>, + <0x0 0x17d92000 0x0 0x1000>, + <0x0 0x17d93000 0x0 0x1000>; + reg-names =3D "freq-domain0", + "freq-domain1", + "freq-domain2"; + + interrupts =3D , + , + ; + interrupt-names =3D "dcvsh-irq-0", + "dcvsh-irq-1", + "dcvsh-irq-2"; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; + clock-names =3D "xo", "alternate"; + + #freq-domain-cells =3D <1>; + #clock-cells =3D <1>; + }; + + gem_noc: interconnect@24100000 { + compatible =3D "qcom,milos-gem-noc"; + reg =3D <0x0 0x24100000 0x0 0xff080>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + nsp_noc: interconnect@320c0000 { + compatible =3D "qcom,milos-nsp-noc"; + reg =3D <0x0 0x320c0000 0x0 0xe080>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + remoteproc_cdsp: remoteproc@32300000 { + compatible =3D "qcom,milos-cdsp-pas"; + reg =3D <0x0 0x32300000 0x0 0x10000>; + + interrupts-extended =3D <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names =3D "wdog", + "fatal", + "ready", + "handover", + "stop-ack", + "shutdown-ack"; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "xo"; + + power-domains =3D <&rpmhpd RPMHPD_CX>, + <&rpmhpd RPMHPD_MX>; + power-domain-names =3D "cx", + "mx"; + + interconnects =3D <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + + memory-region =3D <&cdsp_mem>, <&q6_cdsp_dtb_mem>; + + qcom,qmp =3D <&aoss_qmp>; + + qcom,smem-states =3D <&smp2p_cdsp_out 0>; + qcom,smem-state-names =3D "stop"; + + status =3D "disabled"; + + glink-edge { + interrupts-extended =3D <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes =3D <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label =3D "cdsp"; + qcom,remote-pid =3D <5>; + }; + }; + }; + + thermal-zones { + aoss0-thermal { + thermal-sensors =3D <&tsens0 0>; + + trips { + aoss0-hot { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "hot"; + }; + + aoss0-critical { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + cpuss0-thermal { + thermal-sensors =3D <&tsens0 1>; + + trips { + cpuss0-hot { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "hot"; + }; + + cpuss0-critical { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + cpuss1-thermal { + thermal-sensors =3D <&tsens0 2>; + + trips { + cpuss1-hot { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "hot"; + }; + + cpuss1-critical { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + cpu4-left-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens0 3>; + + trips { + trip-point0 { + temperature =3D <90000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu4-left-critical { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu4-right-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens0 4>; + + trips { + trip-point0 { + temperature =3D <90000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu4-right-critical { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu5-left-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens0 5>; + + trips { + trip-point0 { + temperature =3D <90000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu5-left-critical { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu5-right-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens0 6>; + + trips { + trip-point0 { + temperature =3D <90000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu5-right-critical { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu6-left-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens0 7>; + + trips { + trip-point0 { + temperature =3D <90000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu6-left-critical { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu6-right-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens0 8>; + + trips { + trip-point0 { + temperature =3D <90000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu6-right-critical { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu7-left-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens0 9>; + + trips { + trip-point0 { + temperature =3D <90000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu7-left-critical { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu7-right-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens0 10>; + + trips { + trip-point0 { + temperature =3D <90000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu7-right-critical { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu0-thermal { + thermal-sensors =3D <&tsens0 11>; + + trips { + trip-point0 { + temperature =3D <90000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu0-critical { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu1-thermal { + thermal-sensors =3D <&tsens0 12>; + + trips { + trip-point0 { + temperature =3D <90000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu1-critical { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu2-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens0 13>; + + trips { + trip-point0 { + temperature =3D <90000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu2-critical { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + cpu3-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens0 14>; + + trips { + trip-point0 { + temperature =3D <90000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <95000>; + hysteresis =3D <2000>; + type =3D "passive"; + }; + + cpu3-critical { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + aoss1-thermal { + thermal-sensors =3D <&tsens1 0>; + + trips { + aoss1-hot { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "hot"; + }; + + aoss1-critical { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + nsphvx0-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens1 1>; + + trips { + nsphvx0-hot { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "hot"; + }; + + nsphvx0-critical { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + nsphmx1-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens1 2>; + + trips { + nsphmx1-hot { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "hot"; + }; + + nsphmx1-critical { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + nsphmx0-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens1 3>; + + trips { + nsphmx0-hot { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "hot"; + }; + + nsphmx0-critical { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + gpuss0-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens1 4>; + + trips { + gpu0_alert0: trip-point0 { + temperature =3D <85000>; + hysteresis =3D <1000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <90000>; + hysteresis =3D <1000>; + type =3D "hot"; + }; + + gpuss0-critical { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + gpuss1-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens1 5>; + + trips { + gpu1_alert0: trip-point0 { + temperature =3D <85000>; + hysteresis =3D <1000>; + type =3D "passive"; + }; + + trip-point1 { + temperature =3D <90000>; + hysteresis =3D <1000>; + type =3D "hot"; + }; + + gpuss1-critical { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "critical"; + }; + }; + }; + + video-thermal { + thermal-sensors =3D <&tsens1 7>; + + trips { + video-hot { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "hot"; + }; + + video-critical { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + ddr-thermal { + polling-delay-passive =3D <10>; + + thermal-sensors =3D <&tsens1 8>; + + trips { + ddr-hot { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "hot"; + }; + + ddr-critical { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + camera0-thermal { + thermal-sensors =3D <&tsens1 9>; + + trips { + camera0-hot { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "hot"; + }; + + camera0-critical { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + modem0-thermal { + polling-delay-passive =3D <100>; + + thermal-sensors =3D <&tsens1 10>; + + trips { + modem0-hot { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "hot"; + }; + + modem0-critical { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + modem1-thermal { + polling-delay-passive =3D <100>; + + thermal-sensors =3D <&tsens1 11>; + + trips { + modem1-hot { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "hot"; + }; + + modem1-critical { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + modem2-thermal { + polling-delay-passive =3D <100>; + + thermal-sensors =3D <&tsens1 12>; + + trips { + modem2-hot { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "hot"; + }; + + modem2-critical { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + + modem3-thermal { + polling-delay-passive =3D <100>; + + thermal-sensors =3D <&tsens1 13>; + + trips { + modem3-hot { + temperature =3D <110000>; + hysteresis =3D <1000>; + type =3D "hot"; + }; + + modem3-critical { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + }; + + timer { + compatible =3D "arm,armv8-timer"; + + interrupts =3D , + , + , + ; + }; +}; --=20 2.50.1 From nobody Tue Oct 7 07:06:06 2025 Received: from mail-wm1-f49.google.com (mail-wm1-f49.google.com [209.85.128.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1E4DD20E03F for ; Sun, 13 Jul 2025 08:08:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.49 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752394117; cv=none; b=c1hydNki/TyGJMnnmxkKFqlH1FDLQ6iWCwPj24KYq7mWuS727ErF+dv/DhtAIIIThtUV3exfYUhfZRqi/7qTyDFCdtZRTymy66IcB6lU4DAWO8QyWsxNBWvzZDXQFOAWKCL8L+RyO1x2rE4l2IQsnjw4Y2NkY4mIoUr7FiO5v/A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752394117; c=relaxed/simple; bh=0KjwSxa72FPBPkf24xy97A7MrZMj8P2DBUJ2h92ORCE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=KjFNPnrgwz2qJCMbJcrGD/VKuDEyV7I6T7sVLW0jj7ixn6z722F4Ghz5JpLOzu3vyu83UUNrKFvMKY/G6vTOyrpmWWmSu67FsU4cTNfKy4KOv+tmoWR0HxehKNpGcg+vSEmYrSIKbytM8l+KiVgtGRrKjEJenzTvlI1ElfwMdtQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=fairphone.com; spf=pass smtp.mailfrom=fairphone.com; dkim=pass (2048-bit key) header.d=fairphone.com header.i=@fairphone.com header.b=uiawi0/a; arc=none smtp.client-ip=209.85.128.49 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=fairphone.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=fairphone.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=fairphone.com header.i=@fairphone.com header.b="uiawi0/a" Received: by mail-wm1-f49.google.com with SMTP id 5b1f17b1804b1-45610582d07so3283455e9.0 for ; Sun, 13 Jul 2025 01:08:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fairphone.com; s=fair; t=1752394112; x=1752998912; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=U2jRQDyiYWA48zC7SFF4YTscb0dZ8X09eBuE8747BuU=; b=uiawi0/a1H1xlK1zl+1/VXKaFywvIr9+yFiAhH6jCV13TPoxc92uDNZD520ubyfTSO sBIC2T7lYdGBJoUGXAJL1aL4CbFONo1++40llQvKY9jnE4mi5gpOJ2q0+PZFzrC5ZZCZ GtBjmmhnZ53ksv2V/osatySi38LjBsLG+22xspqCOqcapZUhQKwJALiULXZaUyCB/Noi rrm2dcDmw4wiGN/ZVMOraOCLmN6KL2APMKSF2Kd6WGeRELTC+aK7G6W+bC1O7BWQ6qry jscylVFKlfFVxXgX7uxsAElshR4K8sUsEuSHZrIZ7ZGqqtewU0Gktp50aaWnInCZwEZ3 ij7A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1752394112; x=1752998912; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=U2jRQDyiYWA48zC7SFF4YTscb0dZ8X09eBuE8747BuU=; b=jbPqzvFegRXqVJwiL27w009EYyqn/wT231V+TaWgI9a7IVEiizGeFv9Dy2LRHaUTdZ mJ+ym8NIUh2Q8Vh1KwqnhBBvaEFG2O2EOQa+lXF0srS6qeIhM9Y8T4nbqKwrZodHosG2 K+BhorM9f1j0zACACxBnYUm58GKqefgJ8912E9qJ9dgX6Z7qpLE4TRSsjfFz9K6vOOK0 1q8P6g4wLFPX7ycsO4sDME1lW+AUq6hYIuvX50tNuGcmHDjSVFfCRjWLco6GRWaO0lxt OSvjqeYGNjhHXhNuzP5rZlBplI++AOhg9Sop+7yZ6m0Io95ledcjDK8bUNBtrmT2FtyA q5mw== X-Forwarded-Encrypted: i=1; AJvYcCVFFHCxq3aTcI/h696MYue7O0ko5EMt3KWoUJ1tpVSjAifNbQSAdCrqm+fjT27H+SA5AT4JFq5OSA7/cas=@vger.kernel.org X-Gm-Message-State: AOJu0YzxpCvaSOsiITcT3AcNvKKp17eXR9Lvtwt+aryJWnPY8ArEYW/E DMe9TPxTOQ0bChLlfiyzv0gSLj7WSYk+U6Wtm90/KOrixG+WIqCJew/RcHvTVzTcYk8= X-Gm-Gg: ASbGncu7mqLdv9LALUmHXYjUunUozHjFfDayew9urt7o9iV+3oCHAvzOgkvH3/BkY02 QtfimAkLOOXC9LyVeFCKks909SzS2frQ/qsGq1e2sXzl1Et+IjAVsv6/AklZ1wS95LS3o6RMjr/ 6GfRrsM1K7BR1pRHxJpxm0q1WbX0etMAYSYEouvWu4uEZGvetwakMwZ8zMzBJGTi+AZUt+HWUny hwtywrcsXRcA/PzS5IBcVg6EykuOGXdahJBqW2FhSNtSNr11FphIssGjC0xeZjnKeKMIQWyYVYA KeWvMWLRnABgVE4eg0X4TV9wrhllLRxjAzjC/ZHCG+xGThPcynCtjSbXx4t+Lxwv8pMpsd32Gre VOQZc5zXYMbJc7ATaO0YirABb6KNvRSIfjhmnRR04MfkW1a8= X-Google-Smtp-Source: AGHT+IEJntnIxR9SIneQpdYXf6fWz6lm1ZYFTxOLkLZpPWZMvmuFoCXGGjHBFX6LZnYTVi3bUJIw8A== X-Received: by 2002:a05:600c:314c:b0:450:c210:a01b with SMTP id 5b1f17b1804b1-454fe0f93e3mr101630205e9.17.1752394112258; Sun, 13 Jul 2025 01:08:32 -0700 (PDT) Received: from [192.168.224.50] ([213.208.155.167]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3b5e8dc22a8sm9386608f8f.34.2025.07.13.01.08.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Jul 2025 01:08:31 -0700 (PDT) From: Luca Weiss Date: Sun, 13 Jul 2025 10:05:37 +0200 Subject: [PATCH v2 15/15] arm64: dts: qcom: Add The Fairphone (Gen. 6) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250713-sm7635-fp6-initial-v2-15-e8f9a789505b@fairphone.com> References: <20250713-sm7635-fp6-initial-v2-0-e8f9a789505b@fairphone.com> In-Reply-To: <20250713-sm7635-fp6-initial-v2-0-e8f9a789505b@fairphone.com> To: Will Deacon , Robin Murphy , Joerg Roedel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , "Rafael J. Wysocki" , Viresh Kumar , Manivannan Sadhasivam , Herbert Xu , "David S. Miller" , Vinod Koul , Bjorn Andersson , Konrad Dybcio , Robert Marko , Das Srinagesh , Thomas Gleixner , Jassi Brar , Amit Kucheria , Thara Gopinath , Daniel Lezcano , Zhang Rui , Lukasz Luba , Ulf Hansson Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-crypto@vger.kernel.org, dmaengine@vger.kernel.org, linux-mmc@vger.kernel.org, Luca Weiss X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1752393945; l=21652; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=0KjwSxa72FPBPkf24xy97A7MrZMj8P2DBUJ2h92ORCE=; b=XjUO1r4nohsCQBKIblzIygz28SG95SjXvQpWvakia5Cd3w5CVqBdFkydJnuWO1FoZTLmhvM2L jHzybLqo1n7CXaKizuvwGdd5NL+d8MtmUGb5tHKKpj7PVPFc7dT6LyD X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= Add a devicetree for The Fairphone (Gen. 6) smartphone, which is based on the Milos/SM7635 SoC. Supported functionality as of this initial submission: * Debug UART * Regulators (PM7550, PM8550VS, PMR735B, PM8008) * Remoteprocs (ADSP, CDSP, MPSS, WPSS) * Power Button, Volume Keys, Switch * Display (using simple-framebuffer) * PMIC-GLINK (Charger, Fuel gauge, USB-C mode switching) * Camera flash/torch LED * SD card * USB Signed-off-by: Luca Weiss --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts | 815 +++++++++++++++++++= ++++ 2 files changed, 816 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index 669b888b27a1daa93ac15f47e8b9a302bb0922c2..af9649e22c8c9bcadc39ff3179a= f33304ba7b8b2 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -28,6 +28,7 @@ dtb-$(CONFIG_ARCH_QCOM) +=3D ipq9574-rdp433.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D ipq9574-rdp449.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D ipq9574-rdp453.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D ipq9574-rdp454.dtb +dtb-$(CONFIG_ARCH_QCOM) +=3D milos-fairphone-fp6.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8216-samsung-fortuna3g.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8916-acer-a1-724.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D msm8916-alcatel-idol347.dtb diff --git a/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts b/arch/arm64/= boot/dts/qcom/milos-fairphone-fp6.dts new file mode 100644 index 0000000000000000000000000000000000000000..edf0bd333f448d9a777648315b8= 2761a4083365e --- /dev/null +++ b/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts @@ -0,0 +1,815 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2025, Luca Weiss + */ + +/dts-v1/; + +#define PMIV0104_SID 7 + +#include +#include +#include +#include "milos.dtsi" +#include "pm7550.dtsi" +#include "pm8550vs.dtsi" +#include "pmiv0104.dtsi" /* PMIV0108 */ +#include "pmk8550.dtsi" /* PMK7635 */ +#include "pmr735b.dtsi" + +/ { + model =3D "The Fairphone (Gen. 6)"; + compatible =3D "fairphone,fp6", "qcom,milos"; + chassis-type =3D "handset"; + + aliases { + serial0 =3D &uart5; + }; + + chosen { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + framebuffer0: framebuffer@e3940000 { + compatible =3D "simple-framebuffer"; + reg =3D <0x0 0xe3940000 0x0 (2484 * 1116 * 4)>; + width =3D <1116>; + height =3D <2484>; + stride =3D <(1116 * 4)>; + format =3D "a8r8g8b8"; + interconnects =3D <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + clocks =3D <&gcc GCC_DISP_HF_AXI_CLK>; + }; + }; + + gpio-keys { + compatible =3D "gpio-keys"; + + pinctrl-0 =3D <&volume_up_default>; + pinctrl-names =3D "default"; + + key-volume-up { + label =3D "Volume Up"; + gpios =3D <&pm7550_gpios 6 GPIO_ACTIVE_LOW>; + linux,code =3D ; + }; + + switch { + label =3D "Switch"; + gpios =3D <&tlmm 107 GPIO_ACTIVE_HIGH>; + linux,input-type =3D ; + linux,code =3D ; + }; + }; + + pmic-glink { + compatible =3D "qcom,milos-pmic-glink", + "qcom,sm8550-pmic-glink", + "qcom,pmic-glink"; + #address-cells =3D <1>; + #size-cells =3D <0>; + orientation-gpios =3D <&tlmm 131 GPIO_ACTIVE_HIGH>; + + connector@0 { + compatible =3D "usb-c-connector"; + reg =3D <0>; + + power-role =3D "dual"; + data-role =3D "dual"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + pmic_glink_hs_in: endpoint { + remote-endpoint =3D <&usb_1_dwc3_hs>; + }; + }; + }; + }; + }; + + vreg_ff_afvdd_2p8: regulator-ff-afvdd-2p8 { + compatible =3D "regulator-fixed"; + regulator-name =3D "ff_afvdd_2p8"; + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + startup-delay-us =3D <100>; + + gpio =3D <&tlmm 93 GPIO_ACTIVE_HIGH>; + enable-active-high; + + vin-supply =3D <&vreg_bob>; + }; + + vreg_uw_afvdd_2p8: regulator-uw-afvdd-2p8 { + compatible =3D "regulator-fixed"; + regulator-name =3D "uw_afvdd_2p8"; + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + startup-delay-us =3D <100>; + + gpio =3D <&tlmm 23 GPIO_ACTIVE_HIGH>; + enable-active-high; + + vin-supply =3D <&vreg_bob>; + }; + + vreg_uw_dvdd: regulator-uw-dvdd { + compatible =3D "regulator-fixed"; + regulator-name =3D "uw_dvdd"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + startup-delay-us =3D <100>; + + gpio =3D <&tlmm 28 GPIO_ACTIVE_HIGH>; + enable-active-high; + + vin-supply =3D <&vreg_s1b>; + }; + + vreg_ois_avdd0_1p8: regulator-ois-avdd0-1p8 { + compatible =3D "regulator-fixed"; + regulator-name =3D "ois_avdd0_1p8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + startup-delay-us =3D <100>; + + gpio =3D <&tlmm 27 GPIO_ACTIVE_HIGH>; + enable-active-high; + + vin-supply =3D <&vreg_bob>; + }; + + vreg_ois_vdd: regulator-ois-vdd { + compatible =3D "regulator-fixed"; + regulator-name =3D "ois_vdd"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + startup-delay-us =3D <100>; + + gpio =3D <&tlmm 24 GPIO_ACTIVE_HIGH>; + enable-active-high; + + vin-supply =3D <&vph_pwr>; + }; + + vreg_oled_dvdd_1p2: regulator-oled-dvdd-1p2 { + compatible =3D "regulator-fixed"; + regulator-name =3D "oled_dvdd_1p2"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + + gpio =3D <&tlmm 54 GPIO_ACTIVE_HIGH>; + enable-active-high; + + vin-supply =3D <&vreg_s2b>; + + regulator-boot-on; + }; + + vreg_s1j: regulator-pm3001a-s1j { + compatible =3D "regulator-fixed"; + regulator-name =3D "pm3001a_s1j"; + regulator-min-microvolt =3D <2200000>; + regulator-max-microvolt =3D <2200000>; + startup-delay-us =3D <1000>; + + gpio =3D <&pmr735b_gpios 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + + vin-supply =3D <&vph_pwr>; + + pinctrl-0 =3D <&s1j_enable_default>; + pinctrl-names =3D "default"; + }; + + vreg_vtof_ldo_3p3: regulator-vtof-ldo-3p3 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vtof_ldo_3p3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + startup-delay-us =3D <100>; + + gpio =3D <&tlmm 76 GPIO_ACTIVE_HIGH>; + enable-active-high; + + vin-supply =3D <&vph_pwr>; + }; + + vph_pwr: regulator-vph-pwr { + compatible =3D "regulator-fixed"; + + regulator-name =3D "vph_pwr"; + regulator-min-microvolt =3D <3700000>; + regulator-max-microvolt =3D <3700000>; + + regulator-always-on; + regulator-boot-on; + }; + + reserved-memory { + /* + * ABL is powering down display and controller if this node is + * not named exactly "splash_region". + */ + splash_region@e3940000 { + reg =3D <0x0 0xe3940000 0x0 0x2b00000>; + no-map; + }; + }; + + thermal-zones { + pm8008-thermal { + polling-delay-passive =3D <100>; + thermal-sensors =3D <&pm8008>; + + trips { + trip0 { + temperature =3D <95000>; + hysteresis =3D <0>; + type =3D "passive"; + }; + + trip1 { + temperature =3D <115000>; + hysteresis =3D <0>; + type =3D "critical"; + }; + }; + }; + }; +}; + +&apps_rsc { + regulators-0 { + compatible =3D "qcom,pm7550-rpmh-regulators"; + + vdd-l1-supply =3D <&vreg_s1b>; + vdd-l2-l3-supply =3D <&vreg_s3b>; + vdd-l4-l5-supply =3D <&vreg_s2b>; + vdd-l6-supply =3D <&vreg_s2b>; + vdd-l7-supply =3D <&vreg_s1b>; + vdd-l8-supply =3D <&vreg_s1b>; + vdd-l9-l10-supply =3D <&vreg_s1b>; + vdd-l11-supply =3D <&vreg_s1b>; + vdd-l12-l14-supply =3D <&vreg_bob>; + vdd-l13-l16-supply =3D <&vreg_bob>; + vdd-l15-l17-l18-l19-l20-l21-l22-l23-supply =3D <&vreg_bob>; + vdd-s1-supply =3D <&vph_pwr>; + vdd-s2-supply =3D <&vph_pwr>; + vdd-s3-supply =3D <&vph_pwr>; + vdd-s4-supply =3D <&vph_pwr>; + vdd-s5-supply =3D <&vph_pwr>; + vdd-s6-supply =3D <&vph_pwr>; + + qcom,pmic-id =3D "b"; + + vreg_s1b: smps1 { + regulator-name =3D "vreg_s1b"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <2080000>; + regulator-initial-mode =3D ; + }; + + vreg_s2b: smps2 { + regulator-name =3D "vreg_s2b"; + regulator-min-microvolt =3D <1256000>; + regulator-max-microvolt =3D <1408000>; + regulator-initial-mode =3D ; + }; + + vreg_s3b: smps3 { + regulator-name =3D "vreg_s3b"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <1040000>; + regulator-initial-mode =3D ; + }; + + vreg_l2b: ldo2 { + regulator-name =3D "vreg_l2b"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <912000>; + regulator-initial-mode =3D ; + }; + + vreg_l3b: ldo3 { + regulator-name =3D "vreg_l3b"; + regulator-min-microvolt =3D <880000>; + regulator-max-microvolt =3D <912000>; + regulator-initial-mode =3D ; + }; + + vreg_l4b: ldo4 { + regulator-name =3D "vreg_l4b"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + }; + + vreg_l5b: ldo5 { + regulator-name =3D "vreg_l5b"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + }; + + vreg_l7b: ldo7 { + regulator-name =3D "vreg_l7b"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + }; + + vreg_l8b: ldo8 { + regulator-name =3D "vreg_l8b"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + }; + + vreg_l9b: ldo9 { + regulator-name =3D "vreg_l9b"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + }; + + vreg_l10b: ldo10 { + regulator-name =3D "vreg_l10b"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + }; + + vreg_l11b: ldo11 { + regulator-name =3D "vreg_l11b"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + }; + + vreg_l12b: ldo12 { + regulator-name =3D "vreg_l12b"; + /* + * Skip voltage voting for UFS VCC. + */ + regulator-initial-mode =3D ; + }; + + vreg_l13b: ldo13 { + regulator-name =3D "vreg_l13b"; + regulator-min-microvolt =3D <2700000>; + regulator-max-microvolt =3D <3300000>; + regulator-initial-mode =3D ; + }; + + vreg_l14b: ldo14 { + regulator-name =3D "vreg_l14b"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3304000>; + regulator-initial-mode =3D ; + }; + + vreg_l15b: ldo15 { + regulator-name =3D "vreg_l15b"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3304000>; + regulator-initial-mode =3D ; + }; + + vreg_l16b: ldo16 { + regulator-name =3D "vreg_l16b"; + regulator-min-microvolt =3D <3008000>; + regulator-max-microvolt =3D <3008000>; + regulator-initial-mode =3D ; + }; + + vreg_l17b: ldo17 { + regulator-name =3D "vreg_l17b"; + regulator-min-microvolt =3D <3104000>; + regulator-max-microvolt =3D <3104000>; + regulator-initial-mode =3D ; + }; + + vreg_l18b: ldo18 { + regulator-name =3D "vreg_l18b"; + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + regulator-initial-mode =3D ; + }; + + vreg_l19b: ldo19 { + regulator-name =3D "vreg_l19b"; + regulator-min-microvolt =3D <3000000>; + regulator-max-microvolt =3D <3000000>; + regulator-initial-mode =3D ; + }; + + vreg_l20b: ldo20 { + regulator-name =3D "vreg_l20b"; + regulator-min-microvolt =3D <1620000>; + regulator-max-microvolt =3D <3544000>; + regulator-initial-mode =3D ; + }; + + vreg_l21b: ldo21 { + regulator-name =3D "vreg_l21b"; + regulator-min-microvolt =3D <1620000>; + regulator-max-microvolt =3D <3544000>; + regulator-initial-mode =3D ; + }; + + vreg_l22b: ldo22 { + regulator-name =3D "vreg_l22b"; + regulator-min-microvolt =3D <3200000>; + regulator-max-microvolt =3D <3200000>; + regulator-initial-mode =3D ; + }; + + vreg_l23b: ldo23 { + regulator-name =3D "vreg_l23b"; + regulator-min-microvolt =3D <1650000>; + regulator-max-microvolt =3D <3544000>; + regulator-initial-mode =3D ; + }; + + vreg_bob: bob { + regulator-name =3D "vreg_bob"; + regulator-min-microvolt =3D <3008000>; + regulator-max-microvolt =3D <3960000>; + regulator-initial-mode =3D ; + }; + }; + + regulators-1 { + compatible =3D "qcom,pm8550vs-rpmh-regulators"; + + vdd-l1-supply =3D <&vreg_s3b>; + vdd-l3-supply =3D <&vreg_s3b>; + + qcom,pmic-id =3D "c"; + + vreg_l2c: ldo2 { + regulator-name =3D "vreg_l2c"; + regulator-min-microvolt =3D <320000>; + regulator-max-microvolt =3D <650000>; + regulator-initial-mode =3D ; + }; + }; + + regulators-2 { + compatible =3D "qcom,pmr735b-rpmh-regulators"; + + vdd-l1-l2-supply=3D <&vreg_s3b>; + vdd-l3-supply=3D <&vreg_s3b>; + vdd-l4-supply=3D <&vreg_s1b>; + vdd-l5-supply=3D <&vreg_s2b>; + vdd-l6-supply=3D <&vreg_s2b>; + vdd-l7-l8-supply=3D <&vreg_s2b>; + vdd-l9-supply=3D <&vreg_s3b>; + vdd-l10-supply=3D <&vreg_s1b>; + vdd-l11-supply=3D <&vreg_s3b>; + vdd-l12-supply=3D <&vreg_s3b>; + + qcom,pmic-id =3D "f"; + + vreg_l1f: ldo1 { + regulator-name =3D "vreg_l1f"; + regulator-min-microvolt =3D <852000>; + regulator-max-microvolt =3D <950000>; + regulator-initial-mode =3D ; + }; + + vreg_l2f: ldo2 { + regulator-name =3D "vreg_l2f"; + regulator-min-microvolt =3D <751000>; + regulator-max-microvolt =3D <824000>; + regulator-initial-mode =3D ; + }; + + vreg_l3f: ldo3 { + regulator-name =3D "vreg_l3f"; + regulator-min-microvolt =3D <650000>; + regulator-max-microvolt =3D <880000>; + regulator-initial-mode =3D ; + }; + + vreg_l4f: ldo4 { + regulator-name =3D "vreg_l4f"; + regulator-min-microvolt =3D <1700000>; + regulator-max-microvolt =3D <1950000>; + regulator-initial-mode =3D ; + }; + + vreg_l5f: ldo5 { + regulator-name =3D "vreg_l5f"; + regulator-min-microvolt =3D <1140000>; + regulator-max-microvolt =3D <1260000>; + regulator-initial-mode =3D ; + }; + + vreg_l6f: ldo6 { + regulator-name =3D "vreg_l6f"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-initial-mode =3D ; + }; + + vreg_l7f: ldo7 { + regulator-name =3D "vreg_l7f"; + regulator-min-microvolt =3D <1080000>; + regulator-max-microvolt =3D <1350000>; + regulator-initial-mode =3D ; + }; + + vreg_l8f: ldo8 { + regulator-name =3D "vreg_l8f"; + regulator-min-microvolt =3D <1100000>; + regulator-max-microvolt =3D <1320000>; + regulator-initial-mode =3D ; + }; + + vreg_l9f: ldo9 { + regulator-name =3D "vreg_l9f"; + regulator-min-microvolt =3D <870000>; + regulator-max-microvolt =3D <970000>; + regulator-initial-mode =3D ; + }; + + vreg_l10f: ldo10 { + regulator-name =3D "vreg_l10f"; + regulator-min-microvolt =3D <1500000>; + regulator-max-microvolt =3D <1800000>; + regulator-initial-mode =3D ; + }; + + vreg_l11f: ldo11 { + regulator-name =3D "vreg_l11f"; + regulator-min-microvolt =3D <320000>; + regulator-max-microvolt =3D <864000>; + regulator-initial-mode =3D ; + }; + }; +}; + +&dispcc { + /* Disable for now so simple-framebuffer continues working */ + status =3D "disabled"; +}; + +&i2c1 { + /* Samsung NFC @ 0x27 */ + + status =3D "okay"; +}; + +&i2c3 { + /* AW88261FCR amplifier (top) @ 0x34 */ + /* AW88261FCR amplifier (bottom) @ 0x35 */ + + status =3D "okay"; +}; + +&i2c7 { + status =3D "okay"; + + pm8008: pmic@8 { + compatible =3D "qcom,pm8008"; + reg =3D <0x8>; + + interrupts-extended =3D <&tlmm 125 IRQ_TYPE_EDGE_RISING>; + reset-gpios =3D <&pmr735b_gpios 3 GPIO_ACTIVE_LOW>; + + vdd-l1-l2-supply =3D <&vreg_s2b>; + vdd-l3-l4-supply =3D <&vreg_bob>; + vdd-l5-supply =3D <&vreg_bob>; + vdd-l6-supply =3D <&vreg_s1b>; + vdd-l7-supply =3D <&vreg_bob>; + + pinctrl-0 =3D <&pm8008_int_default>, <&pm8008_reset_n_default>; + pinctrl-names =3D "default"; + + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&pm8008 0 0 2>; + + interrupt-controller; + #interrupt-cells =3D <2>; + + #thermal-sensor-cells =3D <0>; + + regulators { + vreg_l1p: ldo1 { + regulator-name =3D "vreg_l1p"; + regulator-min-microvolt =3D <1000000>; + regulator-max-microvolt =3D <1200000>; + }; + + vreg_l2p: ldo2 { + regulator-name =3D "vreg_l2p"; + regulator-min-microvolt =3D <950000>; + regulator-max-microvolt =3D <1144000>; + }; + + vreg_l3p: ldo3 { + regulator-name =3D "vreg_l3p"; + regulator-min-microvolt =3D <2700000>; + regulator-max-microvolt =3D <3000000>; + }; + + vreg_l4p: ldo4 { + regulator-name =3D "vreg_l4p"; + regulator-min-microvolt =3D <2700000>; + regulator-max-microvolt =3D <2900000>; + }; + + vreg_l5p: ldo5 { + regulator-name =3D "vreg_l5p"; + regulator-min-microvolt =3D <2704000>; + regulator-max-microvolt =3D <2900000>; + }; + + vreg_l6p: ldo6 { + regulator-name =3D "vreg_l6p"; + regulator-min-microvolt =3D <1700000>; + regulator-max-microvolt =3D <1896000>; + }; + + vreg_l7p: ldo7 { + regulator-name =3D "vreg_l7p"; + regulator-min-microvolt =3D <2700000>; + regulator-max-microvolt =3D <3400000>; + }; + }; + }; + + /* VL53L3 ToF @ 0x29 */ + /* AW86938FCR vibrator @ 0x5a */ +}; + +&pm8550vs_c { + status =3D "okay"; +}; + +&pmiv0104_eusb2_repeater { + vdd18-supply =3D <&vreg_l7b>; + vdd3-supply =3D <&vreg_l17b>; + + qcom,tune-res-fsdif =3D /bits/ 8 <0x5>; + qcom,tune-usb2-amplitude =3D /bits/ 8 <0x8>; + qcom,tune-usb2-disc-thres =3D /bits/ 8 <0x7>; + qcom,tune-usb2-preem =3D /bits/ 8 <0x6>; +}; + +&pmr735b_gpios { + s1j_enable_default: s1j-enable-default-state { + pins =3D "gpio1"; + function =3D PMIC_GPIO_FUNC_NORMAL; + power-source =3D <0>; + bias-disable; + output-low; + }; + + pm8008_reset_n_default: pm8008-reset-n-default-state { + pins =3D "gpio3"; + function =3D PMIC_GPIO_FUNC_NORMAL; + bias-pull-down; + }; +}; + +&pm7550_gpios { + volume_up_default: volume-up-default-state { + pins =3D "gpio6"; + function =3D PMIC_GPIO_FUNC_NORMAL; + power-source =3D <1>; + bias-pull-up; + }; +}; + +&pm7550_flash { + status =3D "okay"; + + led-0 { + function =3D LED_FUNCTION_FLASH; + color =3D ; + led-sources =3D <1>, <4>; + led-max-microamp =3D <350000>; + flash-max-microamp =3D <1500000>; + flash-max-timeout-us =3D <400000>; + }; +}; + +&pon_pwrkey { + status =3D "okay"; +}; + +&pon_resin { + linux,code =3D ; + + status =3D "okay"; +}; + +&qupv3_id_0 { + status =3D "okay"; +}; + +&qupv3_id_1 { + status =3D "okay"; +}; + +&remoteproc_adsp { + firmware-name =3D "qcom/milos/fairphone/fp6/adsp.mbn", + "qcom/milos/fairphone/fp6/adsp_dtb.mbn"; + + status =3D "okay"; +}; + +&remoteproc_cdsp { + firmware-name =3D "qcom/milos/fairphone/fp6/cdsp.mbn", + "qcom/milos/fairphone/fp6/cdsp_dtb.mbn"; + + status =3D "okay"; +}; + +&remoteproc_mpss { + firmware-name =3D "qcom/milos/fairphone/fp6/modem.mbn"; + + status =3D "okay"; +}; + +&remoteproc_wpss { + firmware-name =3D "qcom/milos/fairphone/fp6/wpss.mbn"; + + status =3D "okay"; +}; + +&sdhc_2 { + cd-gpios =3D <&tlmm 65 GPIO_ACTIVE_HIGH>; + + vmmc-supply =3D <&vreg_l13b>; + vqmmc-supply =3D <&vreg_l23b>; + no-sdio; + no-mmc; + + pinctrl-0 =3D <&sdc2_default>, <&sdc2_card_det_n>; + pinctrl-1 =3D <&sdc2_sleep>, <&sdc2_card_det_n>; + pinctrl-names =3D "default", "sleep"; + + status =3D "okay"; +}; + +&spi0 { + /* Eswin EPH8621 touchscreen @ 0 */ +}; + +&tlmm { + gpio-reserved-ranges =3D <8 4>, /* Fingerprint SPI */ + <13 1>, /* NC */ + <63 2>; /* WLAN UART */ + + sdc2_card_det_n: sdc2-card-det-state { + pins =3D "gpio65"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-up; + }; + + pm8008_int_default: pm8008-int-default-state { + pins =3D "gpio125"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; +}; + +&uart5 { + status =3D "okay"; +}; + +&usb_1 { + dr_mode =3D "otg"; + + /* USB 2.0 only, HW does not support USB 3.x */ + qcom,select-utmi-as-pipe-clk; + + status =3D "okay"; +}; + +&usb_1_dwc3_hs { + remote-endpoint =3D <&pmic_glink_hs_in>; +}; + +&usb_1_hsphy { + vdd-supply =3D <&vreg_l2b>; + vdda12-supply =3D <&vreg_l4b>; + + phys =3D <&pmiv0104_eusb2_repeater>; + + status =3D "okay"; +}; --=20 2.50.1