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[46.135.46.162]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ae6e7e90a42sm610876266b.27.2025.07.13.01.39.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Jul 2025 01:39:22 -0700 (PDT) From: Tomeu Vizoso Date: Sun, 13 Jul 2025 10:39:00 +0200 Subject: [PATCH v8 10/10] arm64: dts: rockchip: enable NPU on ROCK 5B Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250713-6-10-rocket-v8-10-64fa3115e910@tomeuvizoso.net> References: <20250713-6-10-rocket-v8-0-64fa3115e910@tomeuvizoso.net> In-Reply-To: <20250713-6-10-rocket-v8-0-64fa3115e910@tomeuvizoso.net> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Oded Gabbay , Jonathan Corbet , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Sumit Semwal , =?utf-8?q?Christian_K=C3=B6nig?= , Sebastian Reichel , Nicolas Frattaroli , Kever Yang , Robin Murphy , Daniel Stone , Da Xue , Philipp Zabel , Jeff Hugo Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-doc@vger.kernel.org, linux-media@vger.kernel.org, linaro-mm-sig@lists.linaro.org, Tomeu Vizoso X-Mailer: b4 0.14.2 From: Nicolas Frattaroli The NPU on the ROCK5B uses the same regulator for both the sram-supply and the npu's supply. Add this regulator, and enable all the NPU bits. Also add the regulator as a domain-supply to the pd_npu power domain. v8: - Remove notion of top core (Robin Murphy) Signed-off-by: Nicolas Frattaroli Tested-by: Heiko Stuebner Signed-off-by: Tomeu Vizoso --- arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dtsi | 57 ++++++++++++++++++++= ++++ 1 file changed, 57 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dtsi b/arch/arm64/= boot/dts/rockchip/rk3588-rock-5b.dtsi index 6052787d2560978d2bae6cfbeea5fc1d419d583a..06f73f16901026485c02cecf917= 6d0d7dc7a021a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dtsi @@ -309,6 +309,29 @@ regulator-state-mem { }; }; =20 +&i2c1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c1m2_xfer>; + status =3D "okay"; + + vdd_npu_s0: regulator@42 { + compatible =3D "rockchip,rk8602"; + reg =3D <0x42>; + fcs,suspend-voltage-selector =3D <1>; + regulator-name =3D "vdd_npu_s0"; + regulator-boot-on; + regulator-enable-ramp-delay =3D <500>; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <950000>; + regulator-ramp-delay =3D <2300>; + vin-supply =3D <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + &i2c6 { status =3D "okay"; =20 @@ -433,6 +456,10 @@ &pd_gpu { domain-supply =3D <&vdd_gpu_s0>; }; =20 +&pd_npu { + domain-supply =3D <&vdd_npu_s0>; +}; + &pinctrl { hdmirx { hdmirx_hpd: hdmirx-5v-detection { @@ -487,6 +514,36 @@ &pwm1 { status =3D "okay"; }; =20 +&rknn_core_0 { + npu-supply =3D <&vdd_npu_s0>; + sram-supply =3D <&vdd_npu_s0>; + status =3D "okay"; +}; + +&rknn_core_1 { + npu-supply =3D <&vdd_npu_s0>; + sram-supply =3D <&vdd_npu_s0>; + status =3D "okay"; +}; + +&rknn_core_2 { + npu-supply =3D <&vdd_npu_s0>; + sram-supply =3D <&vdd_npu_s0>; + status =3D "okay"; +}; + +&rknn_mmu_top { + status =3D "okay"; +}; + +&rknn_mmu_1 { + status =3D "okay"; +}; + +&rknn_mmu_2 { + status =3D "okay"; +}; + &saradc { vref-supply =3D <&avcc_1v8_s0>; status =3D "okay"; --=20 2.50.0