From nobody Tue Oct 7 06:57:52 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 63C83275851; Tue, 15 Jul 2025 08:31:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.19 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752568305; cv=none; b=g3iJ/RpX9D8F0OOyXZrkuh7x1p4sBXQ3q/ixgXcs0T/qG88rGRccVOLb1f50b24AI7J/iBvixkqH8kxmyrmasct2zGXph0aMibFNYSCKzAgj/gcpOknS5ZST4MytUNkn4TDL40b697Hdqoj67iwIX0qtDsM/jokvrdygXtUyE3g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752568305; c=relaxed/simple; bh=f/GBaWhzt8SY797GdaCdkYWcJqOPaoevRGjaBPfPDJM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=GCBQInjK3IgqB34jkqpv/ZBefwXBVRv0kk+8zlXhJ3cis28oBEbceq/RgUb8bm9K/3WKcTwxLS4XXXqUbdhW0yILFcb1zI836IYnKeCbQLaJvz2tDbul0gT4i0Uc9RU9vFUalIx1O+3iz62Mu4PXulXHA4KIHi1YgdLVzmlqZB0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=nk/RrHBK; arc=none smtp.client-ip=198.175.65.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="nk/RrHBK" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1752568304; x=1784104304; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=f/GBaWhzt8SY797GdaCdkYWcJqOPaoevRGjaBPfPDJM=; b=nk/RrHBKRc2Iwlv5LFjb3fFSsT1IyijXxZvj2btJoLjbZxt3vBkG8e+8 cGGAbhyWwWhuObwQl9BF97zIOlBtwAe9Bl7z+24wHt31hImAU7sD1kut3 2HMiH9i+cPp7bPRFUPzK/XxN0tpTGz52C32SJ5M/fcQ1DxU2Bs+kso6Bw COMl49p0bDCIksSEj9Jqsm15iNJTZWwonR03+VJ08Wecd1oClR1IWxQjY dRqwtDI0VC499pT8LUeAtR+2azZEtY5ZjeWtHjSl/bynrRlKHPmNQ1Em8 VLaStuNHsdzgmCPcbjWPaGnDvYD+Ju2/hU8UUsMYih68J2b0APa18yOuT w==; X-CSE-ConnectionGUID: CEWPwH6XStCBlDvwHU4ZAQ== X-CSE-MsgGUID: jivmdw4MRF2pcrpX8xhZ3w== X-IronPort-AV: E=McAfee;i="6800,10657,11491"; a="54632085" X-IronPort-AV: E=Sophos;i="6.16,313,1744095600"; d="scan'208";a="54632085" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Jul 2025 01:31:43 -0700 X-CSE-ConnectionGUID: 5irYBWQDSDqPdLui1GV4FA== X-CSE-MsgGUID: icVPE1kWQmCcCWHaa+yfBg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,313,1744095600"; d="scan'208";a="156572568" Received: from emr.sh.intel.com ([10.112.229.56]) by orviesa010.jf.intel.com with ESMTP; 15 Jul 2025 01:31:40 -0700 From: Dapeng Mi To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Jim Mattson , Mingwei Zhang , Zide Chen , Das Sandipan , Shukla Manali , Yi Lai , Dapeng Mi , dongsheng , Dapeng Mi Subject: [kvm-unit-tests patch 1/5] x86/pmu: Add helper to detect Intel overcount issues Date: Sat, 12 Jul 2025 17:49:11 +0000 Message-ID: <20250712174915.196103-2-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250712174915.196103-1-dapeng1.mi@linux.intel.com> References: <20250712174915.196103-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: dongsheng For Intel Atom CPUs, the PMU events "Instruction Retired" or "Branch Instruction Retired" may be overcounted for some certain instructions, like FAR CALL/JMP, RETF, IRET, VMENTRY/VMEXIT/VMPTRLD and complex SGX/SMX/CSTATE instructions/flows. The detailed information can be found in the errata (section SRF7): https://edc.intel.com/content/www/us/en/design/products-and-solutions/proce= ssors-and-chipsets/sierra-forest/xeon-6700-series-processor-with-e-cores-sp= ecification-update/errata-details/ For the Atom platforms before Sierra Forest (including Sierra Forest), Both 2 events "Instruction Retired" and "Branch Instruction Retired" would be overcounted on these certain instructions, but for Clearwater Forest only "Instruction Retired" event is overcounted on these instructions. So add a helper detect_inst_overcount_flags() to detect whether the platform has the overcount issue and the later patches would relax the precise count check by leveraging the gotten overcount flags from this helper. Signed-off-by: dongsheng [Rewrite comments and commit message - Dapeng] Signed-off-by: Dapeng Mi Tested-by: Yi Lai --- lib/x86/processor.h | 17 ++++++++++++++++ x86/pmu.c | 47 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 64 insertions(+) diff --git a/lib/x86/processor.h b/lib/x86/processor.h index 62f3d578..3f475c21 100644 --- a/lib/x86/processor.h +++ b/lib/x86/processor.h @@ -1188,4 +1188,21 @@ static inline bool is_lam_u57_enabled(void) return !!(read_cr3() & X86_CR3_LAM_U57); } =20 +static inline u32 x86_family(u32 eax) +{ + u32 x86; + + x86 =3D (eax >> 8) & 0xf; + + if (x86 =3D=3D 0xf) + x86 +=3D (eax >> 20) & 0xff; + + return x86; +} + +static inline u32 x86_model(u32 eax) +{ + return ((eax >> 12) & 0xf0) | ((eax >> 4) & 0x0f); +} + #endif diff --git a/x86/pmu.c b/x86/pmu.c index a6b0cfcc..87365aff 100644 --- a/x86/pmu.c +++ b/x86/pmu.c @@ -159,6 +159,14 @@ static struct pmu_event *gp_events; static unsigned int gp_events_size; static unsigned int fixed_counters_num; =20 +/* + * Flags for Intel "Instruction Retired" and "Branch Instruction Retired" + * overcount flaws. + */ +#define INST_RETIRED_OVERCOUNT BIT(0) +#define BR_RETIRED_OVERCOUNT BIT(1) +static u32 intel_inst_overcount_flags; + static int has_ibpb(void) { return this_cpu_has(X86_FEATURE_SPEC_CTRL) || @@ -959,6 +967,43 @@ static void check_invalid_rdpmc_gp(void) "Expected #GP on RDPMC(64)"); } =20 +/* + * For Intel Atom CPUs, the PMU events "Instruction Retired" or + * "Branch Instruction Retired" may be overcounted for some certain + * instructions, like FAR CALL/JMP, RETF, IRET, VMENTRY/VMEXIT/VMPTRLD + * and complex SGX/SMX/CSTATE instructions/flows. + * + * The detailed information can be found in the errata (section SRF7): + * https://edc.intel.com/content/www/us/en/design/products-and-solutions/p= rocessors-and-chipsets/sierra-forest/xeon-6700-series-processor-with-e-core= s-specification-update/errata-details/ + * + * For the Atom platforms before Sierra Forest (including Sierra Forest), + * Both 2 events "Instruction Retired" and "Branch Instruction Retired" wo= uld + * be overcounted on these certain instructions, but for Clearwater Forest + * only "Instruction Retired" event is overcounted on these instructions. + */ +static u32 detect_inst_overcount_flags(void) +{ + u32 flags =3D 0; + struct cpuid c =3D cpuid(1); + + if (x86_family(c.a) =3D=3D 0x6) { + switch (x86_model(c.a)) { + case 0xDD: /* Clearwater Forest */ + flags =3D INST_RETIRED_OVERCOUNT; + break; + + case 0xAF: /* Sierra Forest */ + case 0x4D: /* Avaton, Rangely */ + case 0x5F: /* Denverton */ + case 0x86: /* Jacobsville */ + flags =3D INST_RETIRED_OVERCOUNT | BR_RETIRED_OVERCOUNT; + break; + } + } + + return flags; +} + int main(int ac, char **av) { int instruction_idx; @@ -985,6 +1030,8 @@ int main(int ac, char **av) branch_idx =3D INTEL_BRANCHES_IDX; branch_miss_idx =3D INTEL_BRANCH_MISS_IDX; =20 + intel_inst_overcount_flags =3D detect_inst_overcount_flags(); + /* * For legacy Intel CPUS without clflush/clflushopt support, * there is no way to force to trigger a LLC miss, thus set --=20 2.43.0 From nobody Tue Oct 7 06:57:52 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 933BB1D5ABA; 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X-CSE-ConnectionGUID: wbENkD8LS32eWNHnlbs/fw== X-CSE-MsgGUID: xIFlVgp3Qn6+6JDI9qExJQ== X-IronPort-AV: E=McAfee;i="6800,10657,11491"; a="54632096" X-IronPort-AV: E=Sophos;i="6.16,313,1744095600"; d="scan'208";a="54632096" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Jul 2025 01:31:48 -0700 X-CSE-ConnectionGUID: Rx2ZMBYdTNu59D0IW2jJUQ== X-CSE-MsgGUID: yVPJKVXBRBa5/IimkzvJgA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,313,1744095600"; d="scan'208";a="156572579" Received: from emr.sh.intel.com ([10.112.229.56]) by orviesa010.jf.intel.com with ESMTP; 15 Jul 2025 01:31:44 -0700 From: Dapeng Mi To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Jim Mattson , Mingwei Zhang , Zide Chen , Das Sandipan , Shukla Manali , Yi Lai , Dapeng Mi , dongsheng , Dapeng Mi Subject: [kvm-unit-tests patch 2/5] x86/pmu: Relax precise count validation for Intel overcounted platforms Date: Sat, 12 Jul 2025 17:49:12 +0000 Message-ID: <20250712174915.196103-3-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250712174915.196103-1-dapeng1.mi@linux.intel.com> References: <20250712174915.196103-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: dongsheng As the VM-Exit/VM-Entry overcount issue on Intel Atom platforms, there is no way to validate the precise count for "instructions" and "branches" events on these overcounted Atom platforms. Thus relax the precise count validation on these overcounted platforms. Signed-off-by: dongsheng Signed-off-by: Dapeng Mi Tested-by: Yi Lai --- x86/pmu.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/x86/pmu.c b/x86/pmu.c index 87365aff..04946d10 100644 --- a/x86/pmu.c +++ b/x86/pmu.c @@ -237,10 +237,15 @@ static void adjust_events_range(struct pmu_event *gp_= events, * occur while running the measured code, e.g. if the host takes IRQs. */ if (pmu.is_intel && this_cpu_has_perf_global_ctrl()) { - gp_events[instruction_idx].min =3D LOOP_INSNS; - gp_events[instruction_idx].max =3D LOOP_INSNS; - gp_events[branch_idx].min =3D LOOP_BRANCHES; - gp_events[branch_idx].max =3D LOOP_BRANCHES; + if (!(intel_inst_overcount_flags & INST_RETIRED_OVERCOUNT)) { + gp_events[instruction_idx].min =3D LOOP_INSNS; + gp_events[instruction_idx].max =3D LOOP_INSNS; + } + + if (!(intel_inst_overcount_flags & BR_RETIRED_OVERCOUNT)) { + gp_events[branch_idx].min =3D LOOP_BRANCHES; + gp_events[branch_idx].max =3D LOOP_BRANCHES; + } } =20 /* --=20 2.43.0 From nobody Tue Oct 7 06:57:52 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 29D3926E70A; Tue, 15 Jul 2025 08:31:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.19 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752568317; cv=none; b=MCE6mKJELyOmsq9CFeTV10XXjA55JqE24Ij90jt31dAy6S4Qr8sRUWMF9E/u8EK5F40yywh/sVFnmhokyAhNcZny44sfvkzv0Q2wTpvQI6aFS0/HXsxVNTMs9X99owFRNJAWTfsh16dw+bbhRMrrBSwlNQG1YePPSY/YPZv1qh4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752568317; c=relaxed/simple; bh=1Ia/J3K9aclNh66KQEhyuyMRC7haQhAZD00golo2ytI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=aCL2VHlozL2Lc0/bo8+jM/BFJRzL0hJMv18M/VIjn2zrGC6Ax3jFzBaY/nBM1W/OaBnAJEstiY7KxNbbmRu/xpoV1fCkP9lN7b5eJYS/vnwDlflBPtl/iufHZ1+T2lxBspIK1J02q/W6OPGQMAoVmZl4ZtsbwUnszOMsH2jDIT0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=JSfrKqCy; arc=none smtp.client-ip=198.175.65.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="JSfrKqCy" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1752568316; x=1784104316; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=1Ia/J3K9aclNh66KQEhyuyMRC7haQhAZD00golo2ytI=; b=JSfrKqCy1OUSNCMoZqYW3Rumsr7/5MzhzFykQcJH484DIrECeYBUbqZr DgclKevEUiRnEpNQvU+26DrKSl5ssKUeGh+mHA+khtS/t+91mrKu1BiGA NRkkfmgu6CoobFnlvOseGS//SuxORaI4EV1QZRkMMSeHUuOTgPIAO8Sta AoVVE48qfvIBRXpCVxRwk37tMKyobEa8ZvSOaaVJp8rajD1RaZQjLO2zD ZO30WtPLtGp5rG5my3ZAOJVi4oDbTETt3MVJzuOwHFyLkhNH2TGZsu/cW 7v2DZD4LRPswQUS2ilcK/URs++0QVhrNevcl4v2MVcH870hwK4rJ2oNSP g==; X-CSE-ConnectionGUID: qrymY4bIQ7KFGGeENNI7YQ== X-CSE-MsgGUID: 4Jv7fa7eROus4vx6JKAGqw== X-IronPort-AV: E=McAfee;i="6800,10657,11491"; a="54632107" X-IronPort-AV: E=Sophos;i="6.16,313,1744095600"; d="scan'208";a="54632107" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Jul 2025 01:31:51 -0700 X-CSE-ConnectionGUID: lKA+n8ovSv6iHbxLFXJrng== X-CSE-MsgGUID: gsOMK/IYRrO3MVTbWZHMtw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,313,1744095600"; d="scan'208";a="156572586" Received: from emr.sh.intel.com ([10.112.229.56]) by orviesa010.jf.intel.com with ESMTP; 15 Jul 2025 01:31:48 -0700 From: Dapeng Mi To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Jim Mattson , Mingwei Zhang , Zide Chen , Das Sandipan , Shukla Manali , Yi Lai , Dapeng Mi , dongsheng , Dapeng Mi Subject: [kvm-unit-tests patch 3/5] x86/pmu: Fix incorrect masking of fixed counters Date: Sat, 12 Jul 2025 17:49:13 +0000 Message-ID: <20250712174915.196103-4-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250712174915.196103-1-dapeng1.mi@linux.intel.com> References: <20250712174915.196103-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: dongsheng The current implementation mistakenly limits the width of fixed counters to the width of GP counters. Corrects the logic to ensure fixed counters are properly masked according to their own width. Opportunistically refine the GP counter bitwidth processing code. Signed-off-by: dongsheng Co-developed-by: Dapeng Mi Signed-off-by: Dapeng Mi Tested-by: Yi Lai --- x86/pmu.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/x86/pmu.c b/x86/pmu.c index 04946d10..44c728a5 100644 --- a/x86/pmu.c +++ b/x86/pmu.c @@ -556,18 +556,16 @@ static void check_counter_overflow(void) int idx; =20 cnt.count =3D overflow_preset; - if (pmu_use_full_writes()) - cnt.count &=3D (1ull << pmu.gp_counter_width) - 1; - if (i =3D=3D pmu.nr_gp_counters) { if (!pmu.is_intel) break; =20 cnt.ctr =3D fixed_events[0].unit_sel; - cnt.count =3D measure_for_overflow(&cnt); - cnt.count &=3D (1ull << pmu.gp_counter_width) - 1; + cnt.count &=3D (1ull << pmu.fixed_counter_width) - 1; } else { cnt.ctr =3D MSR_GP_COUNTERx(i); + if (pmu_use_full_writes()) + cnt.count &=3D (1ull << pmu.gp_counter_width) - 1; } =20 if (i % 2) --=20 2.43.0 From nobody Tue Oct 7 06:57:52 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B2BEE2D3737; Tue, 15 Jul 2025 08:31:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.19 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752568319; cv=none; b=jdeyzEldweHGAtyO/5Esep1x5nDkbZL7TDfHEeASaTicEex99KXG3Zg7mnGqrZtPx8Vegoo9QdPE22949Wy9GrJx6KZ9TnlW3S8O3qb40v9sVaXOWpJHx4mBszQZNC8SqQ0C1Tr8Qoan1O2TX/oSWGx421ZJgODMtBlLZPghU+Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752568319; c=relaxed/simple; bh=u3ipQeeF+33UNym7RHJSoeJHycW2i7A3nLZ2wZJmLxM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=nWgCRgt9P8c3sL5TED/D5Ky0Mzj04ah8nVqv5rbEOBptwHnvoOH+/QasQdef+k0NTPHWRlQKY5YJa0cnNCb8Ulc3+roObPG1C3LtiaO1sm7SXJ7rTbt4b2jYlMnHr7FnR8wRrSDuxv6Ir6hbRpcH4Sp7rkgKAMMC8fP1QEzgzok= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=U68rNiPf; arc=none smtp.client-ip=198.175.65.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="U68rNiPf" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1752568318; x=1784104318; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=u3ipQeeF+33UNym7RHJSoeJHycW2i7A3nLZ2wZJmLxM=; b=U68rNiPfgeJf+O+mxo2snsUGm+qUDSHKy6o2DWEhiHFmMB3ab384NLi5 efgupjO4wYQln5npiGkv4N8H15K2uIb1FvAbFY2kN43YNU4ZSk/eQ8/+T 0ajHwtatFlNyJMZYdud15JiHbsPF3Vnhh9TW8Fyw/rIQHgMLpA5fuMndB Xn6vOThq2IGD+f4WEg75AuHJMkI2d9dJj3RD5OUsry5YDjAYO7n8kWPsU ccZ+JlRSLYhI2q9ZpZJKN/ZKflT4pk6gb8SNpaOpLTZY+E1i8czesApnX bsDgEOqa8zhg5dPog0HYqaJc/XZyXXEArg6qPS+TWbWeKBlAZRxQbRKvg w==; X-CSE-ConnectionGUID: uGFjuvdlQ5qGIFmaymOLpg== X-CSE-MsgGUID: ITZgW9qyQDmW9EJR+oSHcQ== X-IronPort-AV: E=McAfee;i="6800,10657,11491"; a="54632115" X-IronPort-AV: E=Sophos;i="6.16,313,1744095600"; d="scan'208";a="54632115" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Jul 2025 01:31:55 -0700 X-CSE-ConnectionGUID: wGviGYVxQFOSC56kLauAYA== X-CSE-MsgGUID: 6QQLg926TlyNN43MCJi3Qg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,313,1744095600"; d="scan'208";a="156572597" Received: from emr.sh.intel.com ([10.112.229.56]) by orviesa010.jf.intel.com with ESMTP; 15 Jul 2025 01:31:51 -0700 From: Dapeng Mi To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Jim Mattson , Mingwei Zhang , Zide Chen , Das Sandipan , Shukla Manali , Yi Lai , Dapeng Mi , dongsheng , Dapeng Mi Subject: [kvm-unit-tests patch 4/5] x86/pmu: Handle instruction overcount issue in overflow test Date: Sat, 12 Jul 2025 17:49:14 +0000 Message-ID: <20250712174915.196103-5-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250712174915.196103-1-dapeng1.mi@linux.intel.com> References: <20250712174915.196103-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: dongsheng During the execution of __measure(), VM exits (e.g., due to WRMSR/EXTERNAL_INTERRUPT) may occur. On systems affected by the instruction overcount issue, each VM-Exit/VM-Entry can erroneously increment the instruction count by one, leading to false failures in overflow tests. To address this, the patch introduces a range-based validation in place of precise instruction count checks. Additionally, overflow_preset is now statically set to 1 - LOOP_INSNS, rather than being dynamically determined via measure_for_overflow(). These changes ensure consistent and predictable behavior aligned with the intended loop instruction count, while avoiding modifications to the subsequent status and status-clear testing logic. The chosen validation range is empirically derived to maintain test reliability across hardware variations. Signed-off-by: dongsheng Signed-off-by: Dapeng Mi Tested-by: Yi Lai --- x86/pmu.c | 23 +++++++++++++++++++++-- 1 file changed, 21 insertions(+), 2 deletions(-) diff --git a/x86/pmu.c b/x86/pmu.c index 44c728a5..c54c0988 100644 --- a/x86/pmu.c +++ b/x86/pmu.c @@ -518,6 +518,21 @@ static void check_counters_many(void) =20 static uint64_t measure_for_overflow(pmu_counter_t *cnt) { + /* + * During the execution of __measure(), VM exits (e.g., due to + * WRMSR/EXTERNAL_INTERRUPT) may occur. On systems affected by the + * instruction overcount issue, each VM-Exit/VM-Entry can erroneously + * increment the instruction count by one, leading to false failures + * in overflow tests. + * + * To mitigate this, if the overcount issue is detected, we hardcode + * the overflow preset to (1 - LOOP_INSNS) instead of calculating it + * dynamically. This ensures that an overflow will reliably occur, + * regardless of any overcounting caused by VM exits. + */ + if (intel_inst_overcount_flags & INST_RETIRED_OVERCOUNT) + return 1 - LOOP_INSNS; + __measure(cnt, 0); /* * To generate overflow, i.e. roll over to '0', the initial count just @@ -574,8 +589,12 @@ static void check_counter_overflow(void) cnt.config &=3D ~EVNTSEL_INT; idx =3D event_to_global_idx(&cnt); __measure(&cnt, cnt.count); - if (pmu.is_intel) - report(cnt.count =3D=3D 1, "cntr-%d", i); + if (pmu.is_intel) { + if (intel_inst_overcount_flags & INST_RETIRED_OVERCOUNT) + report(cnt.count < 14, "cntr-%d", i); + else + report(cnt.count =3D=3D 1, "cntr-%d", i); + } else report(cnt.count =3D=3D 0xffffffffffff || cnt.count < 7, "cntr-%d", i); =20 --=20 2.43.0 From nobody Tue Oct 7 06:57:52 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4F1462D4B47; Tue, 15 Jul 2025 08:31:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.19 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752568320; cv=none; b=Pv2WpH8RathtqZoftQmrpDrQI6p1jTU2PM8feXyDv6VwlUwlxTyIUD7VU6nIW7+GQL1h66JiWLKhJQtjU4XlnQaWiyVEELdQzLhtif1H0Z2hDC+8kIXAoIuiSj7ho1YbT6L4c1vbmJeUEh9oB18Dl4P/Wer3nBjY2V9GLY4upRg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752568320; c=relaxed/simple; bh=wB6hEFFzvmOcnpBZLYTMSOsSPCn29ml9ZB1Zmap4zqg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=p5Af1NdwtliVSyfrBlrk+eDd0VTcmGxa6CMzFrzh1BhAXFiZAgbWkUnZJ9rDJPJaga+9Qj3deurBvDGNwFYJvFsuPOGxKYjvrVc1AK/gHPV8WhCmPxCQrj3LbCFS73DGKQnUymutecI60rKH2A/sH6eMOCJLQXzaD9OwfSfmc9w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=btkodKuJ; arc=none smtp.client-ip=198.175.65.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="btkodKuJ" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1752568320; x=1784104320; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=wB6hEFFzvmOcnpBZLYTMSOsSPCn29ml9ZB1Zmap4zqg=; b=btkodKuJJsBumquyM8UTsmY93elcYYG/LJhFN/kh0Bi3K/q/k5R/DZJg aEDOw5ETu7jte7P70rgmLC3ZMU1G26GWJOQzT/H9O2a3+TJDkPY0+wtBp uaAZSAYNC028W2ZyzkwY8g21jBGTklf+KqxVFH5Znva2YmeXvX56hVwG0 IAoXkYUpZqx6C8x0qbAKlTdo9n0On1VEiwncupeOP2yVzsa/zL5oP+4XW Jco2WYRsELYk2Z7QgU9YDDO7WR+drtJOEeeZnjogTfrZxGfQRcQTVOBtZ sOcFrp15PjfPxt7ntL9+xLlagzIWMgtKjnRfVcpdIsLulJZix0KSkxCJU w==; X-CSE-ConnectionGUID: 81rBu93kRRKJ36qGvrcZ/w== X-CSE-MsgGUID: Da+TjxOwSoyfHAfWbBkpxw== X-IronPort-AV: E=McAfee;i="6800,10657,11491"; a="54632125" X-IronPort-AV: E=Sophos;i="6.16,313,1744095600"; d="scan'208";a="54632125" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Jul 2025 01:31:59 -0700 X-CSE-ConnectionGUID: 85HYvWqASsWSDK7lGaxF2A== X-CSE-MsgGUID: SgsKgsojRpu7AnERVa8LMA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,313,1744095600"; d="scan'208";a="156572604" Received: from emr.sh.intel.com ([10.112.229.56]) by orviesa010.jf.intel.com with ESMTP; 15 Jul 2025 01:31:55 -0700 From: Dapeng Mi To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Jim Mattson , Mingwei Zhang , Zide Chen , Das Sandipan , Shukla Manali , Yi Lai , Dapeng Mi , dongsheng , Dapeng Mi Subject: [kvm-unit-tests patch 5/5] x86/pmu: Expand "llc references" upper limit for broader compatibility Date: Sat, 12 Jul 2025 17:49:15 +0000 Message-ID: <20250712174915.196103-6-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250712174915.196103-1-dapeng1.mi@linux.intel.com> References: <20250712174915.196103-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: dongsheng Increase the upper limit of the "llc references" test to accommodate results observed on additional Intel CPU models, including CWF and SRF. These CPUs exhibited higher reference counts that previously caused the test to fail. Signed-off-by: dongsheng Signed-off-by: Dapeng Mi Tested-by: Yi Lai --- x86/pmu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/x86/pmu.c b/x86/pmu.c index c54c0988..445ea6b4 100644 --- a/x86/pmu.c +++ b/x86/pmu.c @@ -116,7 +116,7 @@ struct pmu_event { {"core cycles", 0x003c, 1*N, 50*N}, {"instructions", 0x00c0, 10*N, 10.2*N}, {"ref cycles", 0x013c, 1*N, 30*N}, - {"llc references", 0x4f2e, 1, 2*N}, + {"llc references", 0x4f2e, 1, 2.5*N}, {"llc misses", 0x412e, 1, 1*N}, {"branches", 0x00c4, 1*N, 1.1*N}, {"branch misses", 0x00c5, 1, 0.1*N}, --=20 2.43.0