From nobody Tue Oct 7 08:55:45 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id CBA322F5466 for ; Fri, 11 Jul 2025 18:37:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752259072; cv=none; b=OeU4QVDl6zXzFccQxWBzwGUeJaEysa3v/reLlIXNFt9OoPnY1vZM5VWXkYQEPUUUV/7LzESmKdQEWlwUHdf2SPz9fk6rf0FMo5VQdKXQXKRGP59OHBznRDvdTgqM9ecB6tSn3KoVBG3NsTfqOlSNpo7FLvjomzCZwp4Mnm0a8cw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752259072; c=relaxed/simple; bh=BLdFERIskXXwtASjTDYJQcmyxahO7w3ejsvgTwN2m1Y=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=UYkbQzVzhG/wSa8nwdEEnMZrHajBm6u0GMGVpI7cH3wZoXJYAbRSdPNyiczWcDvd5IngtVkwZ7jyQJ0Az+5l0xLtSNmpYTjoZgpCv3U7THkBUq/YD5XF7RviYEsMX4ztGuxpq0d0yvnxeDbbISVsmFC/mZXZ2urrDYs4vyl00CU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9CEFD16F8; Fri, 11 Jul 2025 11:37:39 -0700 (PDT) Received: from merodach.members.linode.com (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id EE0033F694; Fri, 11 Jul 2025 11:37:46 -0700 (PDT) From: James Morse To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Rob Herring , Ben Horgan , Rohit Mathew , Shanker Donthineni , Zeng Heng , Lecopzer Chen , Carl Worth , shameerali.kolothum.thodi@huawei.com, D Scott Phillips OS , lcherian@marvell.com, bobo.shaobowang@huawei.com, tan.shaopeng@fujitsu.com, baolin.wang@linux.alibaba.com, Jamie Iles , Xin Hao , peternewman@google.com, dfustini@baylibre.com, amitsinght@marvell.com, David Hildenbrand , Rex Nie , Dave Martin , Koba Ko , James Morse Subject: [RFC PATCH 14/36] arm_mpam: Add support for memory controller MSC on DT platforms Date: Fri, 11 Jul 2025 18:36:26 +0000 Message-Id: <20250711183648.30766-15-james.morse@arm.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20250711183648.30766-1-james.morse@arm.com> References: <20250711183648.30766-1-james.morse@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Shanker Donthineni The device-tree binding has two examples for MSC associated with memory controllers. Add the support to discover the component_id from the device-tree and create 'memory' RIS. Signed-off-by: Shanker Donthineni [ morse: split out of a bigger patch, added affinity piece ] Signed-off-by: James Morse --- drivers/platform/arm64/mpam/mpam_devices.c | 67 +++++++++++++++------- 1 file changed, 47 insertions(+), 20 deletions(-) diff --git a/drivers/platform/arm64/mpam/mpam_devices.c b/drivers/platform/= arm64/mpam/mpam_devices.c index 5b886ba54ba8..f5abd5f0d41a 100644 --- a/drivers/platform/arm64/mpam/mpam_devices.c +++ b/drivers/platform/arm64/mpam/mpam_devices.c @@ -60,41 +60,63 @@ static int mpam_dt_parse_resource(struct mpam_msc *msc,= struct device_node *np, u32 ris_idx) { int err =3D 0; - u32 level =3D 0; - unsigned long cache_id; - struct device_node *cache; + u32 class_id =3D 0, component_id =3D 0; + struct device_node *cache =3D NULL, *memory =3D NULL; + enum mpam_class_types type =3D MPAM_CLASS_UNKNOWN; =20 do { + /* What kind of MSC is this? */ if (of_device_is_compatible(np, "arm,mpam-cache")) { cache =3D of_parse_phandle(np, "arm,mpam-device", 0); if (!cache) { pr_err("Failed to read phandle\n"); break; } + type =3D MPAM_CLASS_CACHE; } else if (of_device_is_compatible(np->parent, "cache")) { cache =3D of_node_get(np->parent); + type =3D MPAM_CLASS_CACHE; + } else if (of_device_is_compatible(np, "arm,mpam-memory")) { + memory =3D of_parse_phandle(np, "arm,mpam-device", 0); + if (!memory) { + pr_err("Failed to read phandle\n"); + break; + } + type =3D MPAM_CLASS_MEMORY; + } else if (of_device_is_compatible(np, "arm,mpam-memory-controller-msc")= ) { + memory =3D of_node_get(np->parent); + type =3D MPAM_CLASS_MEMORY; } else { - /* For now, only caches are supported */ - cache =3D NULL; + /* + * For now, only caches and memory controllers are + * supported. + */ break; } =20 - err =3D of_property_read_u32(cache, "cache-level", &level); - if (err) { - pr_err("Failed to read cache-level\n"); - break; - } - - cache_id =3D cache_of_calculate_id(cache); - if (cache_id =3D=3D ~0UL) { - err =3D -ENOENT; - break; + /* Determine the class and component ids, based on type. */ + if (type =3D=3D MPAM_CLASS_CACHE) { + err =3D of_property_read_u32(cache, "cache-level", &class_id); + if (err) { + pr_err("Failed to read cache-level\n"); + break; + } + component_id =3D cache_of_calculate_id(cache); + if (component_id =3D=3D ~0UL) { + err =3D -ENOENT; + break; + } + } else if (type =3D=3D MPAM_CLASS_MEMORY) { + err =3D of_node_to_nid(np); + component_id =3D (err =3D=3D NUMA_NO_NODE) ? 0 : err; + class_id =3D 255; } =20 - err =3D mpam_ris_create(msc, ris_idx, MPAM_CLASS_CACHE, level, - cache_id); + err =3D mpam_ris_create(msc, ris_idx, type, class_id, + component_id); } while (0); of_node_put(cache); + of_node_put(memory); =20 return err; } @@ -157,9 +179,14 @@ static int update_msc_accessibility(struct mpam_msc *m= sc) cpumask_copy(&msc->accessibility, cpu_possible_mask); err =3D 0; } else { - err =3D -EINVAL; - pr_err("Cannot determine accessibility of MSC: %s\n", - dev_name(&msc->pdev->dev)); + if (of_device_is_compatible(parent, "memory")) { + cpumask_copy(&msc->accessibility, cpu_possible_mask); + err =3D 0; + } else { + err =3D -EINVAL; + pr_err("Cannot determine accessibility of MSC: %s\n", + dev_name(&msc->pdev->dev)); + } } of_node_put(parent); =20 --=20 2.39.5