From nobody Tue Oct 7 08:55:46 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id AF96C2F50B8 for ; Fri, 11 Jul 2025 18:37:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752259062; cv=none; b=MSg8yGVpIm4cyn1SqPKjLaknCunE8I06nKBhDMmQSLWKesXGAddZygnyzY6X7svxeV62Py06JCOa1ABQ5/RIAaFABqSrz3AokAhJj73HxL8TqU1EMPu4I1hy+vtl+JknO5LokUTw6hkeLxDQzkL5PxsYVrCWiM2lFXEdayD3iKQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752259062; c=relaxed/simple; bh=OMRvewwMJMYwsyYU9JHyHJdF6zPulhOsmbssid/5oJk=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=pDdRwvqBRVy5Mu88PuKKnyV8cwd29/+GpMvRqkA1M+RBlW0UpbTN/v6EqY0pNTFGKd0t8ZLuLpDtOX8clOl2w701ab1vc+Zt54ftSoR/Srg2/1w4J8z4eXcGAj42xF3G5Kc9mDNi69TnGafUJXqOnmygogsBtnHf/NY5esNRROA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id AE6902682; Fri, 11 Jul 2025 11:37:29 -0700 (PDT) Received: from merodach.members.linode.com (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 25DE83F694; Fri, 11 Jul 2025 11:37:37 -0700 (PDT) From: James Morse To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Rob Herring , Ben Horgan , Rohit Mathew , Shanker Donthineni , Zeng Heng , Lecopzer Chen , Carl Worth , shameerali.kolothum.thodi@huawei.com, D Scott Phillips OS , lcherian@marvell.com, bobo.shaobowang@huawei.com, tan.shaopeng@fujitsu.com, baolin.wang@linux.alibaba.com, Jamie Iles , Xin Hao , peternewman@google.com, dfustini@baylibre.com, amitsinght@marvell.com, David Hildenbrand , Rex Nie , Dave Martin , Koba Ko , James Morse Subject: [RFC PATCH 11/36] dt-bindings: arm: Add MPAM MSC binding Date: Fri, 11 Jul 2025 18:36:23 +0000 Message-Id: <20250711183648.30766-12-james.morse@arm.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20250711183648.30766-1-james.morse@arm.com> References: <20250711183648.30766-1-james.morse@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Rob Herring The binding is designed around the assumption that an MSC will be a sub-block of something else such as a memory controller, cache controller, or IOMMU. However, it's certainly possible a design does not have that association or has a mixture of both, so the binding illustrates how we can support that with RIS child nodes. A key part of MPAM is we need to know about all of the MSCs in the system before it can be enabled. This drives the need for the genericish 'arm,mpam-msc' compatible. Though we can't assume an MSC is accessible until a h/w specific driver potentially enables the h/w. Cc: James Morse Signed-off-by: Rob Herring Signed-off-by: James Morse --- .../devicetree/bindings/arm/arm,mpam-msc.yaml | 227 ++++++++++++++++++ 1 file changed, 227 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/arm,mpam-msc.yaml diff --git a/Documentation/devicetree/bindings/arm/arm,mpam-msc.yaml b/Docu= mentation/devicetree/bindings/arm/arm,mpam-msc.yaml new file mode 100644 index 000000000000..9d542ecb1a7d --- /dev/null +++ b/Documentation/devicetree/bindings/arm/arm,mpam-msc.yaml @@ -0,0 +1,227 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/arm,mpam-msc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Arm Memory System Resource Partitioning and Monitoring (MPAM) + +description: | + The Arm MPAM specification can be found here: + + https://developer.arm.com/documentation/ddi0598/latest + +maintainers: + - Rob Herring + +properties: + compatible: + items: + - const: arm,mpam-msc # Further details are discov= erable + - const: arm,mpam-memory-controller-msc + + reg: + maxItems: 1 + description: A memory region containing registers as defined in the MP= AM + specification. + + interrupts: + minItems: 1 + items: + - description: error (optional) + - description: overflow (optional, only for monitoring) + + interrupt-names: + oneOf: + - items: + - enum: [ error, overflow ] + - items: + - const: error + - const: overflow + + arm,not-ready-us: + description: The maximum time in microseconds for monitoring data to be + accurate after a settings change. For more information, see the + Not-Ready (NRDY) bit description in the MPAM specification. + + numa-node-id: true # see NUMA binding + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + +patternProperties: + '^ris@[0-9a-f]$': + type: object + additionalProperties: false + description: | + RIS nodes for each RIS in an MSC. These nodes are required for each = RIS + implementing known MPAM controls + + properties: + compatible: + enum: + # Bulk storage for cache + - arm,mpam-cache + # Memory bandwidth + - arm,mpam-memory + + reg: + minimum: 0 + maximum: 0xf + + cpus: + $ref: '/schemas/types.yaml#/definitions/phandle-array' + description: + Phandle(s) to the CPU node(s) this RIS belongs to. By default, t= he parent + device's affinity is used. + + arm,mpam-device: + $ref: '/schemas/types.yaml#/definitions/phandle' + description: + By default, the MPAM enabled device associated with a RIS is the= MSC's + parent node. It is possible for each RIS to be associated with d= ifferent + devices in which case 'arm,mpam-device' should be used. + + required: + - compatible + - reg + +required: + - compatible + - reg + +dependencies: + interrupts: [ interrupt-names ] + +additionalProperties: false + +examples: + - | + /* + cpus { + cpu@0 { + next-level-cache =3D <&L2_0>; + }; + cpu@100 { + next-level-cache =3D <&L2_1>; + }; + }; + */ + L2_0: cache-controller-0 { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&L3>; + + }; + + L2_1: cache-controller-1 { + compatible =3D "cache"; + cache-level =3D <2>; + cache-unified; + next-level-cache =3D <&L3>; + + }; + + L3: cache-controller@30000000 { + compatible =3D "arm,dsu-l3-cache", "cache"; + cache-level =3D <3>; + cache-unified; + + ranges =3D <0x0 0x30000000 0x800000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + msc@10000 { + compatible =3D "arm,mpam-msc"; + + /* CPU affinity implied by parent cache node's */ + reg =3D <0x10000 0x2000>; + interrupts =3D <1>, <2>; + interrupt-names =3D "error", "overflow"; + arm,not-ready-us =3D <1>; + }; + }; + + mem: memory-controller@20000 { + compatible =3D "foo,a-memory-controller"; + reg =3D <0x20000 0x1000>; + + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges; + + msc@21000 { + compatible =3D "arm,mpam-memory-controller-msc", "arm,mpam-msc= "; + reg =3D <0x21000 0x1000>; + interrupts =3D <3>; + interrupt-names =3D "error"; + arm,not-ready-us =3D <1>; + numa-node-id =3D <1>; + }; + }; + + iommu@40000 { + reg =3D <0x40000 0x1000>; + + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + + msc@41000 { + compatible =3D "arm,mpam-msc"; + reg =3D <0 0x1000>; + interrupts =3D <5>, <6>; + interrupt-names =3D "error", "overflow"; + arm,not-ready-us =3D <1>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + ris@2 { + compatible =3D "arm,mpam-cache"; + reg =3D <0>; + // TODO: How to map to device(s)? + }; + }; + }; + + msc@80000 { + compatible =3D "foo,a-standalone-msc"; + reg =3D <0x80000 0x1000>; + + clocks =3D <&clks 123>; + + ranges; + #address-cells =3D <1>; + #size-cells =3D <1>; + + msc@10000 { + compatible =3D "arm,mpam-msc"; + + reg =3D <0x10000 0x2000>; + interrupts =3D <7>; + interrupt-names =3D "overflow"; + arm,not-ready-us =3D <1>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + ris@0 { + compatible =3D "arm,mpam-cache"; + reg =3D <0>; + arm,mpam-device =3D <&L2_0>; + }; + + ris@1 { + compatible =3D "arm,mpam-memory"; + reg =3D <1>; + arm,mpam-device =3D <&mem>; + }; + }; + }; + +... --=20 2.39.5