From nobody Tue Oct 7 07:20:53 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0512018A93F; Fri, 11 Jul 2025 16:53:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.19 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752252841; cv=none; b=tg2MTWNBIiJ1f32k8oa1DhSepztLGp0oBUIy5nvaYLk6T0dGRfURWjCbnYaeECOA+qY75L4ejsNDtLvZu3nkrCaMZEVoo9CMzRYYcuswTQ31m9meZxqAmpWRaLLgLtSa0SWVl/ZZNcne88F+wo9yDv4UpA98mQDyZBk/+/p3y08= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752252841; c=relaxed/simple; bh=QvKBgyb3p3TEAGFvOWbDNtNy2IXZ42X3NFk6SdztgYw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=iN15qZ127gCYkjvBEevRnlgYgiROquPdGbjH0J6+VDpUSfTHZhznIcmDfrsTxrIVqeM7ToDBm+4a9c3d6DSshpqcPaMLQO5tbxRcBd7BPpuT8BafqXtP+ye8WrRWksdtbVt4X9blDnoGNwR2YtDIbsZkuSgwO+u/8fk8YrVFTqs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=ehsKYFxQ; arc=none smtp.client-ip=192.198.163.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="ehsKYFxQ" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1752252840; x=1783788840; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=QvKBgyb3p3TEAGFvOWbDNtNy2IXZ42X3NFk6SdztgYw=; b=ehsKYFxQcHsGsM8EQ5LNcicts7pzoLcPv0TVDVaLAEoPL/8i7LEwTw+6 bK/md7CMoFEOnN6lA3clNUMj6EsaphivWIo/xQPAN2vZ7A3NUSlBRJemL YWct/gov3mK+7afSChzecilO76r1qy6bjrwJcn9Kzw3Hu/OlmZDOW0bjl +g/6cNpiDvEkmpgf9P8vO9K5S+pWpi5Tsz7eZOdGuXcn1HBmL5UB3iHB5 Y4M4IidfoFAuj+ZfrRdzBrZRVHUse/63NF07d45oG8cgOOk4q8EAVY+sb uceUcmFkBqm2KQE2qPkDOyWbt19vcKRoy4kx9VpqYref3aVMJUgLn85VB A==; X-CSE-ConnectionGUID: U3gobOW9TUSRPTUo3MSYBQ== X-CSE-MsgGUID: ude2z7mFQuulk9MJOSI5Pw== X-IronPort-AV: E=McAfee;i="6800,10657,11491"; a="53665438" X-IronPort-AV: E=Sophos;i="6.16,304,1744095600"; d="scan'208";a="53665438" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by fmvoesa113.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Jul 2025 09:52:41 -0700 X-CSE-ConnectionGUID: nnanUOyjSlWgX4mMMn86TQ== X-CSE-MsgGUID: wTP7K8KRQQWzPRmtTNY6ug== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,304,1744095600"; d="scan'208";a="187387773" Received: from lfiedoro-mobl.ger.corp.intel.com (HELO eresheto-mobl3.ger.corp.intel.com) ([10.245.245.49]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Jul 2025 09:52:36 -0700 From: Elena Reshetova To: dave.hansen@intel.com Cc: jarkko@kernel.org, seanjc@google.com, kai.huang@intel.com, mingo@kernel.org, linux-sgx@vger.kernel.org, linux-kernel@vger.kernel.org, x86@kernel.org, asit.k.mallick@intel.com, vincent.r.scarlata@intel.com, chongc@google.com, erdemaktas@google.com, vannapurve@google.com, dionnaglaze@google.com, bondarn@google.com, scott.raynor@intel.com, Elena Reshetova Subject: [PATCH v7 1/5] x86/sgx: Introduce a counter to count the sgx_(vepc_)open() Date: Fri, 11 Jul 2025 19:50:30 +0300 Message-ID: <20250711165212.1354943-2-elena.reshetova@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250711165212.1354943-1-elena.reshetova@intel.com> References: <20250711165212.1354943-1-elena.reshetova@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Currently SGX does not have a global counter to count the active users from userspace or hypervisor. Implement such a counter, sgx_usage_count. It will be used by the driver when attempting to call EUPDATESVN SGX instruction. Note: the sgx_inc_usage_count prototype is defined to return int for the cleanliness of the follow-up patches. When the EUPDATESVN SGX instruction will be enabled in the follow-up patch, the sgx_inc_usage_count will start to return int. Suggested-by: Sean Christopherson Signed-off-by: Elena Reshetova --- arch/x86/kernel/cpu/sgx/driver.c | 22 ++++++++++++++++------ arch/x86/kernel/cpu/sgx/encl.c | 1 + arch/x86/kernel/cpu/sgx/main.c | 14 ++++++++++++++ arch/x86/kernel/cpu/sgx/sgx.h | 3 +++ arch/x86/kernel/cpu/sgx/virt.c | 16 ++++++++++++++-- 5 files changed, 48 insertions(+), 8 deletions(-) diff --git a/arch/x86/kernel/cpu/sgx/driver.c b/arch/x86/kernel/cpu/sgx/dri= ver.c index 7f8d1e11dbee..a2994a74bdff 100644 --- a/arch/x86/kernel/cpu/sgx/driver.c +++ b/arch/x86/kernel/cpu/sgx/driver.c @@ -19,9 +19,15 @@ static int sgx_open(struct inode *inode, struct file *fi= le) struct sgx_encl *encl; int ret; =20 + ret =3D sgx_inc_usage_count(); + if (ret) + return ret; + encl =3D kzalloc(sizeof(*encl), GFP_KERNEL); - if (!encl) - return -ENOMEM; + if (!encl) { + ret =3D -ENOMEM; + goto err_usage_count; + } =20 kref_init(&encl->refcount); xa_init(&encl->page_array); @@ -31,14 +37,18 @@ static int sgx_open(struct inode *inode, struct file *f= ile) spin_lock_init(&encl->mm_lock); =20 ret =3D init_srcu_struct(&encl->srcu); - if (ret) { - kfree(encl); - return ret; - } + if (ret) + goto err_encl; =20 file->private_data =3D encl; =20 return 0; + +err_encl: + kfree(encl); +err_usage_count: + sgx_dec_usage_count(); + return ret; } =20 static int sgx_release(struct inode *inode, struct file *file) diff --git a/arch/x86/kernel/cpu/sgx/encl.c b/arch/x86/kernel/cpu/sgx/encl.c index 279148e72459..3b54889ae4a4 100644 --- a/arch/x86/kernel/cpu/sgx/encl.c +++ b/arch/x86/kernel/cpu/sgx/encl.c @@ -765,6 +765,7 @@ void sgx_encl_release(struct kref *ref) WARN_ON_ONCE(encl->secs.epc_page); =20 kfree(encl); + sgx_dec_usage_count(); } =20 /* diff --git a/arch/x86/kernel/cpu/sgx/main.c b/arch/x86/kernel/cpu/sgx/main.c index 2de01b379aa3..a018b01b8736 100644 --- a/arch/x86/kernel/cpu/sgx/main.c +++ b/arch/x86/kernel/cpu/sgx/main.c @@ -917,6 +917,20 @@ int sgx_set_attribute(unsigned long *allowed_attribute= s, } EXPORT_SYMBOL_GPL(sgx_set_attribute); =20 +/* Counter to count the active SGX users */ +static atomic64_t sgx_usage_count; + +int sgx_inc_usage_count(void) +{ + atomic64_inc(&sgx_usage_count); + return 0; +} + +void sgx_dec_usage_count(void) +{ + atomic64_dec(&sgx_usage_count); +} + static int __init sgx_init(void) { int ret; diff --git a/arch/x86/kernel/cpu/sgx/sgx.h b/arch/x86/kernel/cpu/sgx/sgx.h index d2dad21259a8..f5940393d9bd 100644 --- a/arch/x86/kernel/cpu/sgx/sgx.h +++ b/arch/x86/kernel/cpu/sgx/sgx.h @@ -102,6 +102,9 @@ static inline int __init sgx_vepc_init(void) } #endif =20 +int sgx_inc_usage_count(void); +void sgx_dec_usage_count(void); + void sgx_update_lepubkeyhash(u64 *lepubkeyhash); =20 #endif /* _X86_SGX_H */ diff --git a/arch/x86/kernel/cpu/sgx/virt.c b/arch/x86/kernel/cpu/sgx/virt.c index 7aaa3652e31d..6ce908ed51c9 100644 --- a/arch/x86/kernel/cpu/sgx/virt.c +++ b/arch/x86/kernel/cpu/sgx/virt.c @@ -255,22 +255,34 @@ static int sgx_vepc_release(struct inode *inode, stru= ct file *file) xa_destroy(&vepc->page_array); kfree(vepc); =20 + sgx_dec_usage_count(); return 0; } =20 static int sgx_vepc_open(struct inode *inode, struct file *file) { struct sgx_vepc *vepc; + int ret; + + ret =3D sgx_inc_usage_count(); + if (ret) + return ret; =20 vepc =3D kzalloc(sizeof(struct sgx_vepc), GFP_KERNEL); - if (!vepc) - return -ENOMEM; + if (!vepc) { + ret =3D -ENOMEM; + goto err_usage_count; + } mutex_init(&vepc->lock); xa_init(&vepc->page_array); =20 file->private_data =3D vepc; =20 return 0; + +err_usage_count: + sgx_dec_usage_count(); + return ret; } =20 static long sgx_vepc_ioctl(struct file *file, --=20 2.45.2 From nobody Tue Oct 7 07:20:53 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C7CAE2ED84E; Fri, 11 Jul 2025 16:54:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.19 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752252843; cv=none; b=W16ET81ddfpNRJpy1AzCzggUp5mTRHEizxI+P7Oai+ryTfR/gGrnDfEtUrQ9pGMTOEXoNh91aNO4oa0LZTx2/MDHvyUSx9SraUbnqsMqKDuT2beFWJrSzZoBqSrLMggIIkShfE7ddzwzBmhRDzUPVlZyxiTJiNHUsEEXltW4oj8= ARC-Message-Signature: i=1; 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d="scan'208";a="187387785" Received: from lfiedoro-mobl.ger.corp.intel.com (HELO eresheto-mobl3.ger.corp.intel.com) ([10.245.245.49]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Jul 2025 09:52:41 -0700 From: Elena Reshetova To: dave.hansen@intel.com Cc: jarkko@kernel.org, seanjc@google.com, kai.huang@intel.com, mingo@kernel.org, linux-sgx@vger.kernel.org, linux-kernel@vger.kernel.org, x86@kernel.org, asit.k.mallick@intel.com, vincent.r.scarlata@intel.com, chongc@google.com, erdemaktas@google.com, vannapurve@google.com, dionnaglaze@google.com, bondarn@google.com, scott.raynor@intel.com, Elena Reshetova Subject: [PATCH v7 2/5] x86/cpufeatures: Add X86_FEATURE_SGX_EUPDATESVN feature flag Date: Fri, 11 Jul 2025 19:50:31 +0300 Message-ID: <20250711165212.1354943-3-elena.reshetova@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250711165212.1354943-1-elena.reshetova@intel.com> References: <20250711165212.1354943-1-elena.reshetova@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a flag indicating whenever ENCLS[EUPDATESVN] SGX instruction is supported. This will be used by SGX driver to perform CPU SVN updates. Signed-off-by: Elena Reshetova --- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/kernel/cpu/cpuid-deps.c | 1 + arch/x86/kernel/cpu/scattered.c | 1 + tools/arch/x86/include/asm/cpufeatures.h | 1 + 4 files changed, 4 insertions(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpuf= eatures.h index 602957dd2609..830d24ff1ada 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -494,6 +494,7 @@ #define X86_FEATURE_TSA_SQ_NO (21*32+11) /* AMD CPU not vulnerable to TSA= -SQ */ #define X86_FEATURE_TSA_L1_NO (21*32+12) /* AMD CPU not vulnerable to TSA= -L1 */ #define X86_FEATURE_CLEAR_CPU_BUF_VM (21*32+13) /* Clear CPU buffers using= VERW before VMRUN */ +#define X86_FEATURE_SGX_EUPDATESVN (21*32+14) /* Support for ENCLS[EUPDATE= SVN] instruction */ =20 /* * BUG word(s) diff --git a/arch/x86/kernel/cpu/cpuid-deps.c b/arch/x86/kernel/cpu/cpuid-d= eps.c index 46efcbd6afa4..3d9f49ad0efd 100644 --- a/arch/x86/kernel/cpu/cpuid-deps.c +++ b/arch/x86/kernel/cpu/cpuid-deps.c @@ -79,6 +79,7 @@ static const struct cpuid_dep cpuid_deps[] =3D { { X86_FEATURE_SGX_LC, X86_FEATURE_SGX }, { X86_FEATURE_SGX1, X86_FEATURE_SGX }, { X86_FEATURE_SGX2, X86_FEATURE_SGX1 }, + { X86_FEATURE_SGX_EUPDATESVN, X86_FEATURE_SGX1 }, { X86_FEATURE_SGX_EDECCSSA, X86_FEATURE_SGX1 }, { X86_FEATURE_XFD, X86_FEATURE_XSAVES }, { X86_FEATURE_XFD, X86_FEATURE_XGETBV1 }, diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattere= d.c index b4a1f6732a3a..d13444d11ba0 100644 --- a/arch/x86/kernel/cpu/scattered.c +++ b/arch/x86/kernel/cpu/scattered.c @@ -42,6 +42,7 @@ static const struct cpuid_bit cpuid_bits[] =3D { { X86_FEATURE_PER_THREAD_MBA, CPUID_ECX, 0, 0x00000010, 3 }, { X86_FEATURE_SGX1, CPUID_EAX, 0, 0x00000012, 0 }, { X86_FEATURE_SGX2, CPUID_EAX, 1, 0x00000012, 0 }, + { X86_FEATURE_SGX_EUPDATESVN, CPUID_EAX, 10, 0x00000012, 0 }, { X86_FEATURE_SGX_EDECCSSA, CPUID_EAX, 11, 0x00000012, 0 }, { X86_FEATURE_HW_PSTATE, CPUID_EDX, 7, 0x80000007, 0 }, { X86_FEATURE_CPB, CPUID_EDX, 9, 0x80000007, 0 }, diff --git a/tools/arch/x86/include/asm/cpufeatures.h b/tools/arch/x86/incl= ude/asm/cpufeatures.h index ee176236c2be..78c3894c17c1 100644 --- a/tools/arch/x86/include/asm/cpufeatures.h +++ b/tools/arch/x86/include/asm/cpufeatures.h @@ -487,6 +487,7 @@ #define X86_FEATURE_PREFER_YMM (21*32+ 8) /* Avoid ZMM registers due to d= ownclocking */ #define X86_FEATURE_APX (21*32+ 9) /* Advanced Performance Extensions */ #define X86_FEATURE_INDIRECT_THUNK_ITS (21*32+10) /* Use thunk for indirec= t branches in lower half of cacheline */ +#define X86_FEATURE_SGX_EUPDATESVN (21*32+14) /* Support for ENCLS[EUPDATE= SVN] instruction */ =20 /* * BUG word(s) --=20 2.45.2 From nobody Tue Oct 7 07:20:53 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 830222EF66F; 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charset="utf-8" Add error codes for ENCLS[EUPDATESVN], then SGX CPUSVN update process can know the execution state of EUPDATESVN and notify userspace. Signed-off-by: Elena Reshetova --- arch/x86/include/asm/sgx.h | 37 ++++++++++++++++++++++--------------- 1 file changed, 22 insertions(+), 15 deletions(-) diff --git a/arch/x86/include/asm/sgx.h b/arch/x86/include/asm/sgx.h index 6a0069761508..1abf1461fab6 100644 --- a/arch/x86/include/asm/sgx.h +++ b/arch/x86/include/asm/sgx.h @@ -28,21 +28,22 @@ #define SGX_CPUID_EPC_MASK GENMASK(3, 0) =20 enum sgx_encls_function { - ECREATE =3D 0x00, - EADD =3D 0x01, - EINIT =3D 0x02, - EREMOVE =3D 0x03, - EDGBRD =3D 0x04, - EDGBWR =3D 0x05, - EEXTEND =3D 0x06, - ELDU =3D 0x08, - EBLOCK =3D 0x09, - EPA =3D 0x0A, - EWB =3D 0x0B, - ETRACK =3D 0x0C, - EAUG =3D 0x0D, - EMODPR =3D 0x0E, - EMODT =3D 0x0F, + ECREATE =3D 0x00, + EADD =3D 0x01, + EINIT =3D 0x02, + EREMOVE =3D 0x03, + EDGBRD =3D 0x04, + EDGBWR =3D 0x05, + EEXTEND =3D 0x06, + ELDU =3D 0x08, + EBLOCK =3D 0x09, + EPA =3D 0x0A, + EWB =3D 0x0B, + ETRACK =3D 0x0C, + EAUG =3D 0x0D, + EMODPR =3D 0x0E, + EMODT =3D 0x0F, + EUPDATESVN =3D 0x18, }; =20 /** @@ -73,6 +74,10 @@ enum sgx_encls_function { * public key does not match IA32_SGXLEPUBKEYHASH. * %SGX_PAGE_NOT_MODIFIABLE: The EPC page cannot be modified because it * is in the PENDING or MODIFIED state. + * %SGX_INSUFFICIENT_ENTROPY: Insufficient entropy in RNG. + * %SGX_NO_UPDATE: EUPDATESVN was successful, but CPUSVN was not + * updated because current SVN was not newer than + * CPUSVN. * %SGX_UNMASKED_EVENT: An unmasked event, e.g. INTR, was received */ enum sgx_return_code { @@ -81,6 +86,8 @@ enum sgx_return_code { SGX_CHILD_PRESENT =3D 13, SGX_INVALID_EINITTOKEN =3D 16, SGX_PAGE_NOT_MODIFIABLE =3D 20, + SGX_INSUFFICIENT_ENTROPY =3D 29, + SGX_NO_UPDATE =3D 31, SGX_UNMASKED_EVENT =3D 128, }; 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charset="utf-8" All running enclaves and cryptographic assets (such as internal SGX encryption keys) are assumed to be compromised whenever an SGX-related microcode update occurs. To mitigate this assumed compromise the new supervisor SGX instruction ENCLS[EUPDATESVN] can generate fresh cryptographic assets. Before executing EUPDATESVN, all SGX memory must be marked as unused. This requirement ensures that no potentially compromised enclave survives the update and allows the system to safely regenerate cryptographic assets. Add the method to perform ENCLS[EUPDATESVN]. Signed-off-by: Elena Reshetova --- arch/x86/kernel/cpu/sgx/encls.h | 5 +++ arch/x86/kernel/cpu/sgx/main.c | 61 +++++++++++++++++++++++++++++++++ 2 files changed, 66 insertions(+) diff --git a/arch/x86/kernel/cpu/sgx/encls.h b/arch/x86/kernel/cpu/sgx/encl= s.h index 99004b02e2ed..d9160c89a93d 100644 --- a/arch/x86/kernel/cpu/sgx/encls.h +++ b/arch/x86/kernel/cpu/sgx/encls.h @@ -233,4 +233,9 @@ static inline int __eaug(struct sgx_pageinfo *pginfo, v= oid *addr) return __encls_2(EAUG, pginfo, addr); } =20 +/* Attempt to update CPUSVN at runtime. */ +static inline int __eupdatesvn(void) +{ + return __encls_ret_1(EUPDATESVN, ""); +} #endif /* _X86_ENCLS_H */ diff --git a/arch/x86/kernel/cpu/sgx/main.c b/arch/x86/kernel/cpu/sgx/main.c index a018b01b8736..7615d92bb1ed 100644 --- a/arch/x86/kernel/cpu/sgx/main.c +++ b/arch/x86/kernel/cpu/sgx/main.c @@ -16,6 +16,7 @@ #include #include #include +#include #include "driver.h" #include "encl.h" #include "encls.h" @@ -920,6 +921,66 @@ EXPORT_SYMBOL_GPL(sgx_set_attribute); /* Counter to count the active SGX users */ static atomic64_t sgx_usage_count; =20 +/** + * sgx_update_svn() - Attempt to call ENCLS[EUPDATESVN]. + * This instruction attempts to update CPUSVN to the + * currently loaded microcode update SVN and generate new + * cryptographic assets. Must be called when EPC is empty. + * Most of the time, there will be no update and that's OK. + * If the failure is due to SGX_INSUFFICIENT_ENTROPY, the + * operation can be safely retried. In other failure cases, + * the retry should not be attempted. + * + * Return: + * 0: Success or not supported + * -EAGAIN: Can be safely retried, failure is due to lack of + * entropy in RNG. + * -EIO: Unexpected error, retries are not advisable. + */ +static int __maybe_unused sgx_update_svn(void) +{ + int ret; + + /* + * If EUPDATESVN is not available, it is ok to + * silently skip it to comply with legacy behavior. + */ + if (!cpu_feature_enabled(X86_FEATURE_SGX_EUPDATESVN)) + return 0; + + for (int i =3D 0; i < RDRAND_RETRY_LOOPS; i++) { + ret =3D __eupdatesvn(); + + /* Stop on success or unexpected errors: */ + if (ret !=3D SGX_INSUFFICIENT_ENTROPY) + break; + } + + /* + * SVN successfully updated. + * Let users know when the update was successful. + */ + if (!ret) + pr_info("SVN updated successfully\n"); + + if (!ret || ret =3D=3D SGX_NO_UPDATE) + return 0; + + /* + * SVN update failed due to lack of entropy in DRNG. + * Indicate to userspace that it should retry. + */ + if (ret =3D=3D SGX_INSUFFICIENT_ENTROPY) + return -EAGAIN; + + /* + * EUPDATESVN was called when EPC is empty, all other error + * codes are unexpected. + */ + ENCLS_WARN(ret, "EUPDATESVN"); + return -EIO; +} + int sgx_inc_usage_count(void) { atomic64_inc(&sgx_usage_count); --=20 2.45.2 From nobody Tue Oct 7 07:20:53 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9C0A32F004C; Fri, 11 Jul 2025 16:54:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.19 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752252846; cv=none; b=thn+wRzHqkLawHq3PdutqOkc7H9oAKkwm8GmZYZCEpiKDscgTkbUeY34PR4oguAxp773M4bMwI98Yjg0zkwbuoEdZquWIPfNXDSVG+3uj6YWIBNPDzgKx/spno1FI/2UIoB8R+eKlTN3S6ZieAMzyk6RJ8mnGN0g72N6OLbcu9M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752252846; c=relaxed/simple; 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d="scan'208";a="187387814" Received: from lfiedoro-mobl.ger.corp.intel.com (HELO eresheto-mobl3.ger.corp.intel.com) ([10.245.245.49]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Jul 2025 09:52:58 -0700 From: Elena Reshetova To: dave.hansen@intel.com Cc: jarkko@kernel.org, seanjc@google.com, kai.huang@intel.com, mingo@kernel.org, linux-sgx@vger.kernel.org, linux-kernel@vger.kernel.org, x86@kernel.org, asit.k.mallick@intel.com, vincent.r.scarlata@intel.com, chongc@google.com, erdemaktas@google.com, vannapurve@google.com, dionnaglaze@google.com, bondarn@google.com, scott.raynor@intel.com, Elena Reshetova Subject: [PATCH v7 5/5] x86/sgx: Enable automatic SVN updates for SGX enclaves Date: Fri, 11 Jul 2025 19:50:34 +0300 Message-ID: <20250711165212.1354943-6-elena.reshetova@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250711165212.1354943-1-elena.reshetova@intel.com> References: <20250711165212.1354943-1-elena.reshetova@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable =3D=3D Background =3D=3D ENCLS[EUPDATESVN] is a new SGX instruction [1] which allows enclave attestation to include information about updated microcode SVN without a reboot. Before an EUPDATESVN operation can be successful, all SGX memory (aka. EPC) must be marked as =E2=80=9Cunused=E2=80=9D in the SGX hardware m= etadata (aka.EPCM). This requirement ensures that no compromised enclave can survive the EUPDATESVN procedure and provides an opportunity to generate new cryptographic assets. =3D=3D Patch Contents =3D=3D Attempt to execute ENCLS[EUPDATESVN] every time the first file descriptor is obtained via sgx_(vepc_)open(). In the most common case the microcode SVN is already up-to-date, and the operation succeeds without updating SVN. If it fails with any other error code than SGX_INSUFFICIENT_ENTROPY, this is considered unexpected and the *open() returns an error. This should not happen in practice. On contrary, SGX_INSUFFICIENT_ENTROPY might happen due to a pressure on the system's DRNG (RDSEED) and therefore the *open() can be safely retried to allow normal enclave operation. [1] Runtime Microcode Updates with Intel Software Guard Extensions, https://cdrdv2.intel.com/v1/dl/getContent/648682 Signed-off-by: Elena Reshetova --- arch/x86/kernel/cpu/sgx/main.c | 37 +++++++++++++++++++++++++++++++--- 1 file changed, 34 insertions(+), 3 deletions(-) diff --git a/arch/x86/kernel/cpu/sgx/main.c b/arch/x86/kernel/cpu/sgx/main.c index 7615d92bb1ed..c3db49e6e967 100644 --- a/arch/x86/kernel/cpu/sgx/main.c +++ b/arch/x86/kernel/cpu/sgx/main.c @@ -920,6 +920,8 @@ EXPORT_SYMBOL_GPL(sgx_set_attribute); =20 /* Counter to count the active SGX users */ static atomic64_t sgx_usage_count; +/* Mutex to ensure no concurrent EPC accesses during EUPDATESVN */ +static DEFINE_MUTEX(sgx_svn_lock); =20 /** * sgx_update_svn() - Attempt to call ENCLS[EUPDATESVN]. @@ -937,7 +939,7 @@ static atomic64_t sgx_usage_count; * entropy in RNG. * -EIO: Unexpected error, retries are not advisable. */ -static int __maybe_unused sgx_update_svn(void) +static int sgx_update_svn(void) { int ret; =20 @@ -983,8 +985,37 @@ static int __maybe_unused sgx_update_svn(void) =20 int sgx_inc_usage_count(void) { - atomic64_inc(&sgx_usage_count); - return 0; + int ret; + + /* + * Increments from non-zero indicate potential other + * active EPC users and EUPDATESVN is not attempted. + */ + if (atomic64_inc_not_zero(&sgx_usage_count)) + return 0; + + /* + * Ensure no other concurrent threads can start + * touching EPC while EUPDATESVN is running. + */ + guard(mutex)(&sgx_svn_lock); + + if (atomic64_inc_not_zero(&sgx_usage_count)) + return 0; + + /* + * Attempt to call EUPDATESVN since EPC must be + * empty at this point. + */ + ret =3D sgx_update_svn(); + + /* + * If EUPDATESVN failed, return failure to sgx_(vepc_)open and + * do not increment the sgx_usage_count. + */ + if (!ret) + atomic64_inc(&sgx_usage_count); + return ret; } =20 void sgx_dec_usage_count(void) --=20 2.45.2