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Fri, 11 Jul 2025 08:42:37 -0700 (PDT) Received: from mail.broadcom.net ([192.19.144.250]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-74eb9dd5ccesm5762420b3a.27.2025.07.11.08.42.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Jul 2025 08:42:36 -0700 (PDT) From: Kamal Dasu To: andersson@kernel.org, baolin.wang@linux.alibaba.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, florian.fainelli@broadcom.com, ulf.hansson@linaro.org, adrian.hunter@intel.com Cc: bcm-kernel-feedback-list@broadcom.com, kamal.dasu@broadcom.com, linux-remoteproc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, Kamal Dasu Subject: [PATCH 1/4] dt-bindings: brcmstb-hwspinlock: support for hwspinlock Date: Fri, 11 Jul 2025 11:42:18 -0400 Message-Id: <20250711154221.928164-3-kamal.dasu@broadcom.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250711154221.928164-1-kamal.dasu@broadcom.com> References: <20250711154221.928164-1-kamal.dasu@broadcom.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Kamal Dasu Adding brcmstb_hwspinlock bindings. Signed-off-by: Kamal Dasu --- .../hwlock/brcm,brcmstb-hwspinlock.yaml | 36 +++++++++++++++++++ 1 file changed, 36 insertions(+) create mode 100644 Documentation/devicetree/bindings/hwlock/brcm,brcmstb-h= wspinlock.yaml diff --git a/Documentation/devicetree/bindings/hwlock/brcm,brcmstb-hwspinlo= ck.yaml b/Documentation/devicetree/bindings/hwlock/brcm,brcmstb-hwspinlock.= yaml new file mode 100644 index 000000000000..b49ead166b1e --- /dev/null +++ b/Documentation/devicetree/bindings/hwlock/brcm,brcmstb-hwspinlock.yaml @@ -0,0 +1,36 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/hwlock/brcm,brcmstb-hwspinlock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom settop Hardware Spinlock + +maintainers: + - Kamal Dasu + +properties: + "#hwlock-cells": + const: 1 + + compatible: + const: brcm,brcmstb-hwspinlock + + reg: + maxItems: 1 + +required: + - "#hwlock-cells" + - compatible + - reg + +additionalProperties: false + +examples: + - | + hwspinlock@8404038 { + compatible =3D "brcm,brcmstb-hwspinlock"; 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Fri, 11 Jul 2025 08:42:41 -0700 (PDT) Received: from mail.broadcom.net ([192.19.144.250]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-74eb9dd5ccesm5762420b3a.27.2025.07.11.08.42.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Jul 2025 08:42:40 -0700 (PDT) From: Kamal Dasu To: andersson@kernel.org, baolin.wang@linux.alibaba.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, florian.fainelli@broadcom.com, ulf.hansson@linaro.org, adrian.hunter@intel.com Cc: bcm-kernel-feedback-list@broadcom.com, kamal.dasu@broadcom.com, linux-remoteproc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, Kamal Dasu Subject: [PATCH 2/4] hwspinlock: brcmstb hardware semaphore support Date: Fri, 11 Jul 2025 11:42:19 -0400 Message-Id: <20250711154221.928164-4-kamal.dasu@broadcom.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250711154221.928164-1-kamal.dasu@broadcom.com> References: <20250711154221.928164-1-kamal.dasu@broadcom.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Kamal Dasu Added support for brmstb_hwspinlock driver that makes use of the hwspinlock framework. Driver uses SUN_TOP_CTRL_SEMAPHORE_[1:15] registers to implement the hardware semaphore. With this change other brcmstb drivers can use hwspin_trylock() and hwspin_unlock() apis and make use of this hwspinlock framework. Other driver dt nodes just need to use a reference to the &hwspinlock and the lock id they want to use. e.g. hwlocks =3D <&hwspinlock0 0>; Signed-off-by: Kamal Dasu --- drivers/hwspinlock/Kconfig | 9 +++ drivers/hwspinlock/Makefile | 1 + drivers/hwspinlock/brcmstb_hwspinlock.c | 98 +++++++++++++++++++++++++ 3 files changed, 108 insertions(+) create mode 100644 drivers/hwspinlock/brcmstb_hwspinlock.c diff --git a/drivers/hwspinlock/Kconfig b/drivers/hwspinlock/Kconfig index 3874d15b0e9b..551afa8df2d0 100644 --- a/drivers/hwspinlock/Kconfig +++ b/drivers/hwspinlock/Kconfig @@ -63,4 +63,13 @@ config HSEM_U8500 =20 If unsure, say N. =20 +config HWSPINLOCK_BRCMSTB + tristate "Broadcom Setttop Hardware Semaphore functionality" + depends on ARCH_BRCMSTB || COMPILE_TEST + help + Broadcom settop hwspinlock driver. + Say y here to support the Broadcom Hardware Semaphore functionality, wh= ich + provides a synchronisation mechanism on the SoC. + + If unsure, say N. endif # HWSPINLOCK diff --git a/drivers/hwspinlock/Makefile b/drivers/hwspinlock/Makefile index a0f16c9aaa82..4f5c05403209 100644 --- a/drivers/hwspinlock/Makefile +++ b/drivers/hwspinlock/Makefile @@ -10,3 +10,4 @@ obj-$(CONFIG_HWSPINLOCK_SPRD) +=3D sprd_hwspinlock.o obj-$(CONFIG_HWSPINLOCK_STM32) +=3D stm32_hwspinlock.o obj-$(CONFIG_HWSPINLOCK_SUN6I) +=3D sun6i_hwspinlock.o obj-$(CONFIG_HSEM_U8500) +=3D u8500_hsem.o +obj-$(CONFIG_HWSPINLOCK_BRCMSTB) +=3D brcmstb_hwspinlock.o diff --git a/drivers/hwspinlock/brcmstb_hwspinlock.c b/drivers/hwspinlock/b= rcmstb_hwspinlock.c new file mode 100644 index 000000000000..c27d53e06edf --- /dev/null +++ b/drivers/hwspinlock/brcmstb_hwspinlock.c @@ -0,0 +1,98 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * brcmstb HWSEM driver + * + * Copyright (C) 2025 Broadcom + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "hwspinlock_internal.h" + +#define BRCMSTB_MAX_SEMAPHORES 16 +#define RESET_SEMAPHORE 0 + +#define HWSPINLOCK_VAL 'L' + +static int brcmstb_hwspinlock_trylock(struct hwspinlock *lock) +{ + void __iomem *lock_addr =3D lock->priv; + + writel(HWSPINLOCK_VAL, lock_addr); + + return (readl(lock_addr) =3D=3D HWSPINLOCK_VAL); +} + +static void brcmstb_hwspinlock_unlock(struct hwspinlock *lock) +{ + void __iomem *lock_addr =3D lock->priv; + + /* release the lock by writing 0 to it */ + writel(RESET_SEMAPHORE, lock_addr); +} + +static void brcmstb_hwspinlock_relax(struct hwspinlock *lock) +{ + ndelay(50); +} + +static const struct hwspinlock_ops brcmstb_hwspinlock_ops =3D { + .trylock =3D brcmstb_hwspinlock_trylock, + .unlock =3D brcmstb_hwspinlock_unlock, + .relax =3D brcmstb_hwspinlock_relax, +}; + +static int brcmstb_hwspinlock_probe(struct platform_device *pdev) +{ + struct hwspinlock_device *bank; + struct hwspinlock *hwlock; + void __iomem *io_base; + int i, num_locks =3D BRCMSTB_MAX_SEMAPHORES; + + io_base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(io_base)) { + dev_err(&pdev->dev, "semaphore iobase mapping error\n"); + return PTR_ERR(io_base); + } + + bank =3D devm_kzalloc(&pdev->dev, struct_size(bank, lock, num_locks), + GFP_KERNEL); + if (!bank) + return -ENOMEM; + + platform_set_drvdata(pdev, bank); + + for (i =3D 0, hwlock =3D &bank->lock[0]; i < num_locks; i++, hwlock++) + hwlock->priv =3D io_base + sizeof(u32) * i; + + return devm_hwspin_lock_register(&pdev->dev, bank, + &brcmstb_hwspinlock_ops, + 0, num_locks); +} + +static const struct of_device_id brcmstb_hwspinlock_ids[] =3D { + { .compatible =3D "brcm,brcmstb-hwspinlock", }, + { /* end */ }, +}; +MODULE_DEVICE_TABLE(of, brcmstb_hwspinlock_ids); + +static struct platform_driver brcmstb_hwspinlock_driver =3D { + .probe =3D brcmstb_hwspinlock_probe, + .driver =3D { + .name =3D "brcmstb_hwspinlock", + .of_match_table =3D brcmstb_hwspinlock_ids, + }, +}; + +module_platform_driver(brcmstb_hwspinlock_driver); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Hardware Spinlock driver for brcmstb"); +MODULE_AUTHOR("Kamal Dasu "); --=20 2.34.1 From nobody Tue Oct 7 08:29:25 2025 Received: from mail-pf1-f173.google.com (mail-pf1-f173.google.com [209.85.210.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 119492EE616 for ; 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charset="utf-8" From: Kamal Dasu Adding optional controller share registers and hwspinlock reference fields to be used by sdhci-brcmstb driver. Signed-off-by: Kamal Dasu --- .../bindings/mmc/brcm,sdhci-brcmstb.yaml | 29 +++++++++++++++++-- 1 file changed, 27 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.yaml = b/Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.yaml index eee6be7a7867..fe9be7a7eca5 100644 --- a/Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.yaml +++ b/Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.yaml @@ -27,15 +27,20 @@ properties: - const: brcm,sdhci-brcmstb =20 reg: - maxItems: 2 + minItems: 2 + maxItems: 4 =20 reg-names: + minItems: 2 items: - const: host - const: cfg + - const: share # Optional reg + - const: flshr_ipis0 # Optional reg =20 interrupts: - maxItems: 1 + minItems: 1 + maxItems: 2 =20 clocks: minItems: 1 @@ -60,6 +65,9 @@ properties: type: boolean description: Specifies that controller should use auto CMD12 =20 + hwlocks: + maxItems: 1 + allOf: - $ref: mmc-controller.yaml# - if: @@ -115,3 +123,20 @@ examples: clocks =3D <&scmi_clk 245>; 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Fri, 11 Jul 2025 08:42:49 -0700 (PDT) Received: from mail.broadcom.net ([192.19.144.250]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-74eb9dd5ccesm5762420b3a.27.2025.07.11.08.42.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Jul 2025 08:42:48 -0700 (PDT) From: Kamal Dasu To: andersson@kernel.org, baolin.wang@linux.alibaba.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, florian.fainelli@broadcom.com, ulf.hansson@linaro.org, adrian.hunter@intel.com Cc: bcm-kernel-feedback-list@broadcom.com, kamal.dasu@broadcom.com, linux-remoteproc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, Kamal Dasu Subject: [PATCH 4/4] mmc: sdhci-brcmstb: rpmb sharing by claiming host for TZOS Date: Fri, 11 Jul 2025 11:42:21 -0400 Message-Id: <20250711154221.928164-6-kamal.dasu@broadcom.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250711154221.928164-1-kamal.dasu@broadcom.com> References: <20250711154221.928164-1-kamal.dasu@broadcom.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Kamal Dasu Adding sdio rpmb partition sharing support in brcmstb host driver. The sdhci-brcmstb controller driver uses SDIO_SHARE work registers along with use of brcmstb hwspinlock framework to synchronize access between linux and trusted zone firmware. The sdhci-brcmstb driver claims and releases host for TZOS only when it is requested to do via ipi0 interrupt. Signed-off-by: Kamal Dasu --- drivers/mmc/host/sdhci-brcmstb.c | 243 ++++++++++++++++++++++++++++++- 1 file changed, 242 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci-brcmstb.c b/drivers/mmc/host/sdhci-brcm= stb.c index 48cdcba0f39c..dd68fd512459 100644 --- a/drivers/mmc/host/sdhci-brcmstb.c +++ b/drivers/mmc/host/sdhci-brcmstb.c @@ -12,6 +12,10 @@ #include #include #include +#include +#include +#include +#include "../core/core.h" =20 #include "sdhci-cqhci.h" #include "sdhci-pltfm.h" @@ -34,6 +38,11 @@ #define SDIO_CFG_CQ_CAPABILITY 0x4c #define SDIO_CFG_CQ_CAPABILITY_FMUL GENMASK(13, 12) =20 +#define SDHCI_BRCMSTB_AGENT_LINUX 'L' +#define SDHCI_BRCMSTB_AGENT_TZOS 'A' +#define FLSHARE_IPIS0_INT_SEND_MASK BIT(17) +#define HWSPINLOCK_TIMEOUT_MS 100 + #define SDIO_CFG_CTRL 0x0 #define SDIO_CFG_CTRL_SDCD_N_TEST_EN BIT(31) #define SDIO_CFG_CTRL_SDCD_N_TEST_LEV BIT(30) @@ -46,9 +55,26 @@ /* Select all SD UHS type I SDR speed above 50MB/s */ #define MMC_CAP_UHS_I_SDR_MASK (MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104) =20 +#define BRCMSTB_SD_SHARE_REG_NEXT 0x0 /* Next Agent Register */ +#define BRCMSTB_SD_SHARE_REG_PMC 0x4 /* Work Agent1 Register */ +#define BRCMSTB_SD_SHARE_REG_TZOS 0x8 /* Work Agent2 Register */ +#define BRCMSTB_SD_SHARE_REG_LINUX 0xc /* Work Agent3 Register */ + +struct brcmstb_sdio_share_info { + void __iomem *share_reg; + void __iomem *ipis0_reg; + struct hwspinlock *hwlock; + struct sdhci_host *host; + int irq_recv; + int host_claimed; + wait_queue_head_t wq; + struct task_struct *claim_thread; +}; + struct sdhci_brcmstb_priv { void __iomem *cfg_regs; unsigned int flags; + struct brcmstb_sdio_share_info *si; struct clk *base_clk; u32 base_freq_hz; }; @@ -303,6 +329,218 @@ static const struct of_device_id __maybe_unused sdhci= _brcm_of_match[] =3D { {}, }; =20 +static void sdhci_brcmstb_dump_shr_regs(struct sdhci_host *host) +{ + struct sdhci_pltfm_host *pltfm_host =3D sdhci_priv(host); + struct sdhci_brcmstb_priv *priv =3D sdhci_pltfm_priv(pltfm_host); + struct brcmstb_sdio_share_info *si =3D priv->si; + + dev_dbg(mmc_dev(host->mmc), "wn:0x%x wa:0x%x wl:0x%x\n", + readl(si->share_reg + BRCMSTB_SD_SHARE_REG_NEXT), + readl(si->share_reg + BRCMSTB_SD_SHARE_REG_TZOS), + readl(si->share_reg + BRCMSTB_SD_SHARE_REG_LINUX)); +} + +static bool sdhci_brcmstb_linux_host_is_next(struct brcmstb_sdio_share_inf= o *si) +{ + u32 wn; + + /* check if linux is next */ + wn =3D readl(si->share_reg + BRCMSTB_SD_SHARE_REG_NEXT); + return ((wn =3D=3D SDHCI_BRCMSTB_AGENT_LINUX) ? true : false); +} + +static void sdhci_brcmstb_wait_for_linux_host(struct brcmstb_sdio_share_in= fo *si) +{ + int ret; + + while (1) { + /* put self in wait queue when host not available */ + ret =3D wait_event_interruptible(si->wq, + sdhci_brcmstb_linux_host_is_next(si)); + if (ret !=3D -ERESTARTSYS) + break; + }; +} + +static bool sdhci_brcmstb_tzos_is_waiting(struct brcmstb_sdio_share_info *= si) +{ + u32 wt; + + /* check if TZOS has put itself in the work queue */ + wt =3D readl(si->share_reg + BRCMSTB_SD_SHARE_REG_TZOS); + return ((wt =3D=3D SDHCI_BRCMSTB_AGENT_TZOS) ? true : false); +} + +static void sdhci_brcmstb_wait_for_tzos(struct brcmstb_sdio_share_info *si) +{ + int ret; + + while (1) { + /* wait in queue when tzos cannot use controller */ + ret =3D wait_event_interruptible(si->wq, + sdhci_brcmstb_tzos_is_waiting(si)); + if (ret !=3D -ERESTARTSYS) + break; + } +} + +static void sdhci_brcmstb_aquire_hwsem(struct brcmstb_sdio_share_info *si) +{ + u32 wl =3D SDHCI_BRCMSTB_AGENT_LINUX; + struct mmc_host *mmc =3D si->host->mmc; + int ret; + + /* + * aquire hw sem : + * 1. write linux agent id to work register WL + * 2. Aquire hw semaphore + * 2. clear next work register WN + */ + writel(wl, si->share_reg + BRCMSTB_SD_SHARE_REG_LINUX); + /* try hw semaphore lock, we should never have to wait here */ + ret =3D hwspin_lock_timeout(si->hwlock, HWSPINLOCK_TIMEOUT_MS); + WARN_ON(ret !=3D 0); + /* clear next register when holding the semaphore */ + writel(0, si->share_reg + BRCMSTB_SD_SHARE_REG_NEXT); + dev_dbg(mmc_dev(mmc), "hwsem aquire\n"); + sdhci_brcmstb_dump_shr_regs(si->host); +} + +static void sdhci_brcmstb_release_hwsem(struct brcmstb_sdio_share_info *si) +{ + u32 wt; + struct mmc_host *mmc =3D si->host->mmc; + int ret; + + /* + * release hw semphore + * 1. set the next work agent register WN before releasing hw sem + * 2. Release hw semaphore + * 3. send ipi to TZOS + */ + wt =3D readl(si->share_reg + BRCMSTB_SD_SHARE_REG_TZOS); + writel(wt, si->share_reg + BRCMSTB_SD_SHARE_REG_NEXT); + + /* release hw semaphore if we hold it and send IPI */ + ret =3D hwspin_trylock_raw(si->hwlock); + WARN_ON(ret !=3D 0); + hwspin_unlock(si->hwlock); + + if (wt =3D=3D SDHCI_BRCMSTB_AGENT_TZOS) + writel(FLSHARE_IPIS0_INT_SEND_MASK, si->ipis0_reg); + + dev_dbg(mmc_dev(mmc), "hwsem release\n"); + sdhci_brcmstb_dump_shr_regs(si->host); +} + +static irqreturn_t sdhci_brcmstb_recv_ipi0_irq(int irq, void *dev_id) +{ + struct sdhci_host *host =3D dev_id; + struct sdhci_pltfm_host *pltfm_host =3D sdhci_priv(host); + struct sdhci_brcmstb_priv *priv =3D sdhci_pltfm_priv(pltfm_host); + struct brcmstb_sdio_share_info *si =3D priv->si; + + dev_dbg(mmc_dev(host->mmc), "ipi irq %d next L:%d T:%d ch:%d\n", + irq, sdhci_brcmstb_linux_host_is_next(si), + sdhci_brcmstb_tzos_is_waiting(si), + si->host_claimed); + wake_up_interruptible(&si->wq); + return IRQ_HANDLED; +} + +static int sdhci_brcmstb_host_claim_thread(void *data) +{ + struct brcmstb_sdio_share_info *si =3D data; + struct mmc_host *mmc =3D si->host->mmc; + + do { + sdhci_brcmstb_wait_for_tzos(si); + /* claim host for TZOS */ + mmc_claim_host(mmc); + si->host_claimed +=3D 1; + sdhci_brcmstb_release_hwsem(si); + dev_dbg(mmc_dev(mmc), "host claimed %d\n", si->host_claimed); + sdhci_brcmstb_wait_for_linux_host(si); + sdhci_brcmstb_aquire_hwsem(si); + /* release host */ + mmc_release_host(mmc); + si->host_claimed -=3D 1; + dev_dbg(mmc_dev(mmc), "host released %d\n", si->host_claimed); + } while (!kthread_should_stop()); + + return 0; +} + +static int sdhci_brcmstb_sdio_share_init(struct platform_device *pdev) +{ + struct sdhci_host *host =3D dev_get_drvdata(&pdev->dev); + struct device_node *np =3D pdev->dev.of_node; + struct sdhci_pltfm_host *pltfm_host =3D sdhci_priv(host); + struct sdhci_brcmstb_priv *priv =3D sdhci_pltfm_priv(pltfm_host); + struct brcmstb_sdio_share_info *si; + void __iomem *sdio_sh_regs; + int ret; + + /* sdio_share block */ + sdio_sh_regs =3D devm_platform_ioremap_resource_byname(pdev, "share"); + if (IS_ERR(sdio_sh_regs)) + return 0; + + si =3D devm_kcalloc(&pdev->dev, 1, sizeof(struct brcmstb_sdio_share_info), + GFP_KERNEL); + if (!si) + return -ENOMEM; + + si->share_reg =3D sdio_sh_regs; + ret =3D of_hwspin_lock_get_id(np, 0); + if (ret < 0) { + dev_err(&pdev->dev, "failed to get hwspinlock id %d\n", ret); + return ret; + } + + si->hwlock =3D devm_hwspin_lock_request_specific(&pdev->dev, ret); + if (!si->hwlock) { + dev_err(&pdev->dev, "failed to request hwspinlock\n"); + return -ENXIO; + } + + si->irq_recv =3D platform_get_irq_byname_optional(pdev, "recv_ipi0"); + if (si->irq_recv < 0) { + ret =3D si->irq_recv; + dev_err(&pdev->dev, "recv_ipi0 IRQ not found\n"); + return ret; + } + + ret =3D devm_request_irq(&pdev->dev, si->irq_recv, + sdhci_brcmstb_recv_ipi0_irq, + 0, "mmc_recv_ipi0", host); + if (ret < 0) { + dev_err(&pdev->dev, "mmc_recv_ipi0 IRQ request_irq failed\n"); + return ret; + } + + si->ipis0_reg =3D devm_platform_ioremap_resource_byname(pdev, "flshr_ipis= 0"); + if (IS_ERR(si->ipis0_reg)) + return -ENXIO; + + priv->si =3D si; + si->host =3D host; + init_waitqueue_head(&si->wq); + /* acquire hwsem */ + sdhci_brcmstb_aquire_hwsem(si); + si->claim_thread =3D + kthread_run(sdhci_brcmstb_host_claim_thread, si, + "ksdshrthread/%s", mmc_hostname(host->mmc)); + if (IS_ERR(si->claim_thread)) { + ret =3D PTR_ERR(si->claim_thread); + dev_err(&pdev->dev, "failed to run claim thread\n"); + return -ENOEXEC; + } + + return 0; +} + static u32 sdhci_brcmstb_cqhci_irq(struct sdhci_host *host, u32 intmask) { int cmd_error =3D 0; @@ -482,8 +720,11 @@ static int sdhci_brcmstb_probe(struct platform_device = *pdev) goto err; =20 pltfm_host->clk =3D clk; - return res; + res =3D sdhci_brcmstb_sdio_share_init(pdev); + if (res) + dev_warn(&pdev->dev, "sdio share unavailable\n"); =20 + return 0; err: sdhci_pltfm_free(pdev); clk_disable_unprepare(base_clk); --=20 2.34.1