From nobody Tue Oct 7 10:12:34 2025 Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3E3902D46C2 for ; Fri, 11 Jul 2025 13:31:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.248.80.70 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752240684; cv=none; b=a60go4MgLkezblKO2zcy56LzD7aodswoprBJS3xsFDdpI98XO/PF039AaxEZg/YYhpIvP5+htAyVX2NKON3N2RoBsAnDJvNP/0YWmpZzQmf0bf7+V/McJJUnXCLlXIAm7H8SHGNltZajMMxn/uOURND2DHIJoS/cCxYJ9y7SHH4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752240684; c=relaxed/simple; bh=oht3bQ++0QRPkRveyTA2B93Nl48ShqbA5gGyZmWJLfU=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=R3VZUj1gmmDYsrx7RW4TGX2n4b8OIYfeRdaSI206V3xeUV9i7XhxrzpxOnb2LoCYvmXjT66owuSbRWG8h0BoW8X/RPZIQYxJObc8x5g5Ka1C2yUeGmkeGZ0vu06dbGoAU+y1ENd6NX8DewcCoyWdgA9OqbKrgKXjfmMgEZH2r/o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=andestech.com; spf=pass smtp.mailfrom=andestech.com; arc=none smtp.client-ip=60.248.80.70 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=andestech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=andestech.com Received: from mail.andestech.com (ATCPCS31.andestech.com [10.0.1.89]) by Atcsqr.andestech.com with ESMTPS id 56BDUafi013854 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 11 Jul 2025 21:30:36 +0800 (+08) (envelope-from ben717@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS31.andestech.com (10.0.1.89) with Microsoft SMTP Server id 14.3.498.0; Fri, 11 Jul 2025 21:30:36 +0800 From: Ben Zong-You Xie To: CC: , , , , , , , , , , , , , , , , Ben Zong-You Xie Subject: [PATCH v2 2/9] dt-bindings: riscv: add Andes QiLai SoC and the Voyager board bindings Date: Fri, 11 Jul 2025 21:30:18 +0800 Message-ID: <20250711133025.2192404-3-ben717@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250711133025.2192404-1-ben717@andestech.com> References: <20250711133025.2192404-1-ben717@andestech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-DKIM-Results: atcpcs31.andestech.com; dkim=none; X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL: Atcsqr.andestech.com 56BDUafi013854 Content-Type: text/plain; charset="utf-8" Add DT binding documentation for the Andes QiLai SoC and the Voyager development board. Reviewed-by: Rob Herring (Arm) Signed-off-by: Ben Zong-You Xie --- .../devicetree/bindings/riscv/andes.yaml | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 Documentation/devicetree/bindings/riscv/andes.yaml diff --git a/Documentation/devicetree/bindings/riscv/andes.yaml b/Documenta= tion/devicetree/bindings/riscv/andes.yaml new file mode 100644 index 000000000000..aa1edf1fdec7 --- /dev/null +++ b/Documentation/devicetree/bindings/riscv/andes.yaml @@ -0,0 +1,25 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/riscv/andes.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Andes SoC-based boards + +maintainers: + - Ben Zong-You Xie + +description: + Andes SoC-based boards + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - items: + - enum: + - andestech,voyager + - const: andestech,qilai + +additionalProperties: true --=20 2.34.1