From nobody Tue Oct 7 08:32:09 2025 Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5FF132D3EDD for ; Fri, 11 Jul 2025 13:31:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.248.80.70 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752240683; cv=none; b=tswQLvSNpwLVI7thOfQOAzo59uglr095UYFmB+ML02GFDHiaWUyE38RbC022xkCbLKkU5mS1E8+d5mrC/X/oz1YwlIFpAorHnmZJtrJP+zW1rVEodzP6Hs8fGrvBsbuPo1flqAdiq6ccKA4LMiNzlY6mWbgM+s0vsHtFRMqCmLQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752240683; c=relaxed/simple; bh=3dUZhMseYubF72GaRbNm60DBdOGIBHybqo+w48PR4t4=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=GtbkjDTkIv9cs8BWp/FpVqUDnRvUqoJOtJsGD2BcOXmwGhB1fJOML4Dn0PBAeSlKZ8+/c34IQIp3s6g+WiCZjij9qGlGms6/vLjtyfMJSZdTlnLvNkWi3i1e6458a51wkEOxxdtPpL0Leu6jk6wCUxdgHSJCbrzp1iY6XiKbtew= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=andestech.com; spf=pass smtp.mailfrom=andestech.com; arc=none smtp.client-ip=60.248.80.70 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=andestech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=andestech.com Received: from mail.andestech.com (ATCPCS31.andestech.com [10.0.1.89]) by Atcsqr.andestech.com with ESMTPS id 56BDUYF8013847 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 11 Jul 2025 21:30:34 +0800 (+08) (envelope-from ben717@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS31.andestech.com (10.0.1.89) with Microsoft SMTP Server id 14.3.498.0; Fri, 11 Jul 2025 21:30:34 +0800 From: Ben Zong-You Xie To: CC: , , , , , , , , , , , , , , , , Ben Zong-You Xie Subject: [PATCH v2 1/9] riscv: add Andes SoC family Kconfig support Date: Fri, 11 Jul 2025 21:30:17 +0800 Message-ID: <20250711133025.2192404-2-ben717@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250711133025.2192404-1-ben717@andestech.com> References: <20250711133025.2192404-1-ben717@andestech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-DKIM-Results: atcpcs31.andestech.com; dkim=none; X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL: Atcsqr.andestech.com 56BDUYF8013847 Content-Type: text/plain; charset="utf-8" The first SoC in the Andes series is QiLai. It includes a high-performance quad-core RISC-V AX45MP cluster and one NX27V vector processor. For further information, refer to [1]. [1] https://www.andestech.com/en/products-solutions/andeshape-platforms/qil= ai-chip/ Signed-off-by: Ben Zong-You Xie --- arch/riscv/Kconfig.socs | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index a9c3d2f6debc..61ceae0aa27a 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -1,5 +1,12 @@ menu "SoC selection" =20 +config ARCH_ANDES + bool "Andes SoCs" + depends on MMU && !XIP_KERNEL + select ERRATA_ANDES + help + This enables support for Andes SoC platform hardware. + config ARCH_MICROCHIP_POLARFIRE def_bool ARCH_MICROCHIP =20 --=20 2.34.1 From nobody Tue Oct 7 08:32:09 2025 Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3E3902D46C2 for ; Fri, 11 Jul 2025 13:31:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.248.80.70 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752240684; cv=none; b=a60go4MgLkezblKO2zcy56LzD7aodswoprBJS3xsFDdpI98XO/PF039AaxEZg/YYhpIvP5+htAyVX2NKON3N2RoBsAnDJvNP/0YWmpZzQmf0bf7+V/McJJUnXCLlXIAm7H8SHGNltZajMMxn/uOURND2DHIJoS/cCxYJ9y7SHH4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752240684; c=relaxed/simple; bh=oht3bQ++0QRPkRveyTA2B93Nl48ShqbA5gGyZmWJLfU=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=R3VZUj1gmmDYsrx7RW4TGX2n4b8OIYfeRdaSI206V3xeUV9i7XhxrzpxOnb2LoCYvmXjT66owuSbRWG8h0BoW8X/RPZIQYxJObc8x5g5Ka1C2yUeGmkeGZ0vu06dbGoAU+y1ENd6NX8DewcCoyWdgA9OqbKrgKXjfmMgEZH2r/o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=andestech.com; spf=pass smtp.mailfrom=andestech.com; arc=none smtp.client-ip=60.248.80.70 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=andestech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=andestech.com Received: from mail.andestech.com (ATCPCS31.andestech.com [10.0.1.89]) by Atcsqr.andestech.com with ESMTPS id 56BDUafi013854 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 11 Jul 2025 21:30:36 +0800 (+08) (envelope-from ben717@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS31.andestech.com (10.0.1.89) with Microsoft SMTP Server id 14.3.498.0; Fri, 11 Jul 2025 21:30:36 +0800 From: Ben Zong-You Xie To: CC: , , , , , , , , , , , , , , , , Ben Zong-You Xie Subject: [PATCH v2 2/9] dt-bindings: riscv: add Andes QiLai SoC and the Voyager board bindings Date: Fri, 11 Jul 2025 21:30:18 +0800 Message-ID: <20250711133025.2192404-3-ben717@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250711133025.2192404-1-ben717@andestech.com> References: <20250711133025.2192404-1-ben717@andestech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-DKIM-Results: atcpcs31.andestech.com; dkim=none; X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL: Atcsqr.andestech.com 56BDUafi013854 Content-Type: text/plain; charset="utf-8" Add DT binding documentation for the Andes QiLai SoC and the Voyager development board. Reviewed-by: Rob Herring (Arm) Signed-off-by: Ben Zong-You Xie --- .../devicetree/bindings/riscv/andes.yaml | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 Documentation/devicetree/bindings/riscv/andes.yaml diff --git a/Documentation/devicetree/bindings/riscv/andes.yaml b/Documenta= tion/devicetree/bindings/riscv/andes.yaml new file mode 100644 index 000000000000..aa1edf1fdec7 --- /dev/null +++ b/Documentation/devicetree/bindings/riscv/andes.yaml @@ -0,0 +1,25 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/riscv/andes.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Andes SoC-based boards + +maintainers: + - Ben Zong-You Xie + +description: + Andes SoC-based boards + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - items: + - enum: + - andestech,voyager + - const: andestech,qilai + +additionalProperties: true --=20 2.34.1 From nobody Tue Oct 7 08:32:09 2025 Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AAD3418C933 for ; Fri, 11 Jul 2025 13:31:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.248.80.70 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752240685; cv=none; b=G1C09Zn5wutHfClCWdm4KyFOrxhrfVeM3aesqBogmRF5LrtfXybFSW9D29+QxtMYENbwJySRHQbaDPvi82rZPJft42qkNcpnSf2+bT9f4UMmrxTSM3kLXAyOSMj1zp6BUmKAUHaiKV1R4h7ohTyLmtkHDa5q/Ev9st7LL3U9uMk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752240685; c=relaxed/simple; bh=tfivQdEPw+EfuvP9NQwvevYGfhSqWskGfENeczM1YzU=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=LTn73R15kRC+N6xRXbgIf+kb8fPuUNF5f2RoQPhNoC15is2fEr5Uysyq9W1zLbjm08AMjUTwleQWNsQE0yGwBXXwkzjfd+uh/+EVxCuc9Sz2oQEiP2UpnBNeQI49rYsGFFdEMHz65IWEhyx/JVh5bGuXyK2gBUC8IwMc+IwXbAY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=andestech.com; spf=pass smtp.mailfrom=andestech.com; arc=none smtp.client-ip=60.248.80.70 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=andestech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=andestech.com Received: from mail.andestech.com (ATCPCS31.andestech.com [10.0.1.89]) by Atcsqr.andestech.com with ESMTPS id 56BDUbOp013878 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 11 Jul 2025 21:30:37 +0800 (+08) (envelope-from ben717@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS31.andestech.com (10.0.1.89) with Microsoft SMTP Server id 14.3.498.0; Fri, 11 Jul 2025 21:30:37 +0800 From: Ben Zong-You Xie To: CC: , , , , , , , , , , , , , , , , Ben Zong-You Xie Subject: [PATCH v2 3/9] dt-bindings: interrupt-controller: add Andes QiLai PLIC Date: Fri, 11 Jul 2025 21:30:19 +0800 Message-ID: <20250711133025.2192404-4-ben717@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250711133025.2192404-1-ben717@andestech.com> References: <20250711133025.2192404-1-ben717@andestech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-DKIM-Results: atcpcs31.andestech.com; dkim=none; X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL: Atcsqr.andestech.com 56BDUbOp013878 Content-Type: text/plain; charset="utf-8" Add a new compatible string for Andes QiLai PLIC. Acked-by: Rob Herring (Arm) Reviewed-by: Lad Prabhakar Signed-off-by: Ben Zong-You Xie --- .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,= plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/si= five,plic-1.0.0.yaml index ffc4768bad06..5b827bc24301 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.= 0.0.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.= 0.0.yaml @@ -53,6 +53,7 @@ properties: oneOf: - items: - enum: + - andestech,qilai-plic - renesas,r9a07g043-plic - const: andestech,nceplic100 - items: --=20 2.34.1 From nobody Tue Oct 7 08:32:09 2025 Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AFA5A3A1CD for ; Fri, 11 Jul 2025 13:31:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.248.80.70 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752240694; cv=none; b=a1kL5wd9g/INaFuKWT+cRZvLotlKoBu9AzDvw7tNBeNMbB0IbkqVew27Vi1c2a8UzfFRj3jm8B/w/pHKtkxujxfpUkc1n8GxdKdWJqh07lt1OAQdzPl43mFq2RO8VOgkuJsvQfvAZ8+bWz0mg7Sg+eXlRJy5hvnwCl4Q63opCww= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752240694; c=relaxed/simple; bh=78SlwqOo1S3UzP+6/6pMeB/ujJsd3h62Dte053oiZgw=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Ke5eYTNMzKqNdEMd7Pf+UNd8rgPp4JzaiXCWkj86POc1E+U50bH30fmU/y218R67ZFtnBGSNAp4W2ZA8I0TFlbAcVNMqSZYjfDlRo+5pNOWr6V/PFal4QHsr0q4uPzSSWbFlr9ky8MMku5kSCXbjQjIpvy7LUN4odqZtV2SEZK8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=andestech.com; spf=pass smtp.mailfrom=andestech.com; arc=none smtp.client-ip=60.248.80.70 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=andestech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=andestech.com Received: from mail.andestech.com (ATCPCS31.andestech.com [10.0.1.89]) by Atcsqr.andestech.com with ESMTPS id 56BDUdai014106 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 11 Jul 2025 21:30:39 +0800 (+08) (envelope-from ben717@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS31.andestech.com (10.0.1.89) with Microsoft SMTP Server id 14.3.498.0; Fri, 11 Jul 2025 21:30:39 +0800 From: Ben Zong-You Xie To: CC: , , , , , , , , , , , , , , , , Ben Zong-You Xie , Conor Dooley Subject: [PATCH v2 4/9] dt-bindings: interrupt-controller: add Andes machine-level software interrupt controller Date: Fri, 11 Jul 2025 21:30:20 +0800 Message-ID: <20250711133025.2192404-5-ben717@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250711133025.2192404-1-ben717@andestech.com> References: <20250711133025.2192404-1-ben717@andestech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-DKIM-Results: atcpcs31.andestech.com; dkim=none; X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL: Atcsqr.andestech.com 56BDUdai014106 Content-Type: text/plain; charset="utf-8" Add the DT binding documentation for Andes machine-level software interrupt controller. In the Andes platform such as QiLai SoC, the PLIC module is instantiated a second time with all interrupt sources tied to zero as the software interrupt controller (PLICSW). PLICSW can generate machine-level software interrupts through programming its registers. Acked-by: Conor Dooley Signed-off-by: Ben Zong-You Xie --- .../andestech,plicsw.yaml | 54 +++++++++++++++++++ 1 file changed, 54 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/= andestech,plicsw.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/andeste= ch,plicsw.yaml b/Documentation/devicetree/bindings/interrupt-controller/and= estech,plicsw.yaml new file mode 100644 index 000000000000..eb2eb611ac09 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/andestech,plic= sw.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/andestech,plicsw.y= aml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Andes machine-level software interrupt controller + +description: + In the Andes platform such as QiLai SoC, the PLIC module is instantiated= a + second time with all interrupt sources tied to zero as the software inte= rrupt + controller (PLIC_SW). PLIC_SW directly connects to the machine-mode + inter-processor interrupt lines of CPUs, so RISC-V per-CPU local interru= pt + controller is the parent interrupt controller for PLIC_SW. PLIC_SW can + generate machine-mode inter-processor interrupts through programming its + registers. + +maintainers: + - Ben Zong-You Xie + +properties: + compatible: + items: + - enum: + - andestech,qilai-plicsw + - const: andestech,plicsw + + reg: + maxItems: 1 + + interrupts-extended: + minItems: 1 + maxItems: 15872 + description: + Specifies which harts are connected to the PLIC_SW. Each item must p= oints + to a riscv,cpu-intc node, which has a riscv cpu node as parent. + +additionalProperties: false + +required: + - compatible + - reg + - interrupts-extended + +examples: + - | + interrupt-controller@400000 { + compatible =3D "andestech,qilai-plicsw", "andestech,plicsw"; + reg =3D <0x400000 0x400000>; + interrupts-extended =3D <&cpu0intc 3>, + <&cpu1intc 3>, + <&cpu2intc 3>, + <&cpu3intc 3>; + }; --=20 2.34.1 From nobody Tue Oct 7 08:32:09 2025 Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 06707298997 for ; Fri, 11 Jul 2025 13:31:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.248.80.70 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752240695; cv=none; b=nai9IL4MrTgaXROQXlTSv4HBmn5OLmdtdK2jA0wSvyyPGGdFBU9XgfMFdfsb24nZKSfqX9ZZXdf4fzLBTuiVwihPeTnWMwp8SNruRtvWwgKU3voxd0Z1en9hhbYD2+qjHkr41URZDxkRbWk/yhKNnu8ezz8DK992HoBKxHi7Ld0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752240695; c=relaxed/simple; bh=gM3m9gQmTB2jzmhUd+teIX6Iygf3dzcTGIX5li5KFzA=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=iCWPv/NJTdDZwbYBi01B9EipSjSjFzI3pjt2jjyKZAz/3AZDOuf6UMPEUb1P9DpWZ+KFjMSE0P2m+2ZWBcZwGDvqWK46PA16Ctmfx7THUkN1OQYA4R0gInKyvOh8/u3JykiPDs7uUXae0TCSM12g/Tw9XQfwqCgrUYwSJkjbuSc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=andestech.com; spf=pass smtp.mailfrom=andestech.com; arc=none smtp.client-ip=60.248.80.70 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=andestech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=andestech.com Received: from mail.andestech.com (ATCPCS31.andestech.com [10.0.1.89]) by Atcsqr.andestech.com with ESMTPS id 56BDUepZ014252 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 11 Jul 2025 21:30:40 +0800 (+08) (envelope-from ben717@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS31.andestech.com (10.0.1.89) with Microsoft SMTP Server id 14.3.498.0; Fri, 11 Jul 2025 21:30:40 +0800 From: Ben Zong-You Xie To: CC: , , , , , , , , , , , , , , , , Ben Zong-You Xie , Conor Dooley Subject: [PATCH v2 5/9] dt-bindings: timer: add Andes machine timer Date: Fri, 11 Jul 2025 21:30:21 +0800 Message-ID: <20250711133025.2192404-6-ben717@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250711133025.2192404-1-ben717@andestech.com> References: <20250711133025.2192404-1-ben717@andestech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-DKIM-Results: atcpcs31.andestech.com; dkim=none; X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL: Atcsqr.andestech.com 56BDUepZ014252 Content-Type: text/plain; charset="utf-8" Add the DT binding documentation for Andes machine timer. The RISC-V architecture defines a machine timer that provides a real-time counter and generates timer interrupts. Andes machiner timer (PLMT0) is the implementation of the machine timer, and it contains memory-mapped registers (mtime and mtimecmp). This device supports up to 32 cores. Acked-by: Conor Dooley Signed-off-by: Ben Zong-You Xie --- .../bindings/timer/andestech,plmt0.yaml | 53 +++++++++++++++++++ 1 file changed, 53 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/andestech,plmt0= .yaml diff --git a/Documentation/devicetree/bindings/timer/andestech,plmt0.yaml b= /Documentation/devicetree/bindings/timer/andestech,plmt0.yaml new file mode 100644 index 000000000000..90b612096004 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/andestech,plmt0.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/andestech,plmt0.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Andes machine-level timer + +description: + The Andes machine-level timer device (PLMT0) provides machine-level timer + functionality for a set of HARTs on a RISC-V platform. It has a single + fixed-frequency monotonic time counter (MTIME) register and a time compa= re + register (MTIMECMP) for each HART connected to the PLMT0. A timer interr= upt is + generated if MTIME >=3D MTIMECMP. + +maintainers: + - Ben Zong-You Xie + +properties: + compatible: + items: + - enum: + - andestech,qilai-plmt + - const: andestech,plmt0 + + reg: + maxItems: 1 + + interrupts-extended: + minItems: 1 + maxItems: 32 + description: + Specifies which harts are connected to the PLMT0. Each item must poi= nts + to a riscv,cpu-intc node, which has a riscv cpu node as parent. The + PLMT0 supports 1 hart up to 32 harts. + +additionalProperties: false + +required: + - compatible + - reg + - interrupts-extended + +examples: + - | + interrupt-controller@100000 { + compatible =3D "andestech,qilai-plmt", "andestech,plmt0"; + reg =3D <0x100000 0x100000>; + interrupts-extended =3D <&cpu0intc 7>, + <&cpu1intc 7>, + <&cpu2intc 7>, + <&cpu3intc 7>; + }; --=20 2.34.1 From nobody Tue Oct 7 08:32:09 2025 Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 09EC02D46A0 for ; Fri, 11 Jul 2025 13:31:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.248.80.70 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752240696; cv=none; b=tUtmGqYihAQfVRZTiJRRwldpEucdkdDISKD1Bw1c3CIqaW6Uc3yak+1eQLcusHqeO8iarByhNJRODTivgIxLDJfjLCNdhs+SlwTW7x4id4CZNJHbsnW+wUp5u7vl8R/jkctB9XexaFJkb8svY7GyS7LT2oFQo+pIVUtHvplCYyY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752240696; c=relaxed/simple; bh=0s21+4Kk8VCpN5eT+5Fj7PEagUbETYGagxYwuhCKK8c=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=SG+dTkLtNGi+UkMLwxnQRXGQXawcpsxgPPuY0giM2L/SHsWAlQRRb68HAb5s717x0BkVH3bWH5gfC6uPGj8TQ1iAIDZ1aPDOy3qtEXhYz7R/84nW2fWXWLhmo62f4ZO7LgXs4morvdPsXQCS9Tj79wws4WG3BuwOhqkktYBjFM8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=andestech.com; spf=pass smtp.mailfrom=andestech.com; arc=none smtp.client-ip=60.248.80.70 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=andestech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=andestech.com Received: from mail.andestech.com (ATCPCS31.andestech.com [10.0.1.89]) by Atcsqr.andestech.com with ESMTPS id 56BDUfWl014492 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 11 Jul 2025 21:30:41 +0800 (+08) (envelope-from ben717@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS31.andestech.com (10.0.1.89) with Microsoft SMTP Server id 14.3.498.0; Fri, 11 Jul 2025 21:30:41 +0800 From: Ben Zong-You Xie To: CC: , , , , , , , , , , , , , , , , Ben Zong-You Xie Subject: [PATCH v2 6/9] riscv: dts: andes: add QiLai SoC device tree Date: Fri, 11 Jul 2025 21:30:22 +0800 Message-ID: <20250711133025.2192404-7-ben717@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250711133025.2192404-1-ben717@andestech.com> References: <20250711133025.2192404-1-ben717@andestech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-DKIM-Results: atcpcs31.andestech.com; dkim=none; X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL: Atcsqr.andestech.com 56BDUfWl014492 Content-Type: text/plain; charset="utf-8" Introduce the initial device tree support for the Andes QiLai SoC. For further information, you can refer to [1]. [1] https://www.andestech.com/en/products-solutions/andeshape-platforms/qil= ai-chip/ Signed-off-by: Ben Zong-You Xie --- arch/riscv/boot/dts/andes/qilai.dtsi | 186 +++++++++++++++++++++++++++ 1 file changed, 186 insertions(+) create mode 100644 arch/riscv/boot/dts/andes/qilai.dtsi diff --git a/arch/riscv/boot/dts/andes/qilai.dtsi b/arch/riscv/boot/dts/and= es/qilai.dtsi new file mode 100644 index 000000000000..de3de32f8c39 --- /dev/null +++ b/arch/riscv/boot/dts/andes/qilai.dtsi @@ -0,0 +1,186 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2025 Andes Technology Corporation. All rights reserved. + */ + +/dts-v1/; + +#include + +/ { + #address-cells =3D <2>; + #size-cells =3D <2>; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + timebase-frequency =3D <62500000>; + + cpu0: cpu@0 { + compatible =3D "andestech,ax45mp", "riscv"; + device_type =3D "cpu"; + reg =3D <0>; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm", "xandespmu"; + mmu-type =3D "riscv,sv39"; + clock-frequency =3D <100000000>; + i-cache-size =3D <0x8000>; + i-cache-sets =3D <256>; + i-cache-line-size =3D <64>; + d-cache-size =3D <0x8000>; + d-cache-sets =3D <128>; + d-cache-line-size =3D <64>; + next-level-cache =3D <&l2_cache>; + + cpu0_intc: interrupt-controller { + compatible =3D "andestech,cpu-intc", "riscv,cpu-intc"; + #interrupt-cells =3D <1>; + interrupt-controller; + }; + }; + + cpu1: cpu@1 { + compatible =3D "andestech,ax45mp", "riscv"; + device_type =3D "cpu"; + reg =3D <1>; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm", "xandespmu"; + mmu-type =3D "riscv,sv39"; + clock-frequency =3D <100000000>; + i-cache-size =3D <0x8000>; + i-cache-sets =3D <256>; + i-cache-line-size =3D <64>; + d-cache-size =3D <0x8000>; + d-cache-sets =3D <128>; + d-cache-line-size =3D <64>; + next-level-cache =3D <&l2_cache>; + + cpu1_intc: interrupt-controller { + compatible =3D "andestech,cpu-intc", + "riscv,cpu-intc"; + #interrupt-cells =3D <1>; + interrupt-controller; + }; + }; + + cpu2: cpu@2 { + compatible =3D "andestech,ax45mp", "riscv"; + device_type =3D "cpu"; + reg =3D <2>; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm", "xandespmu"; + mmu-type =3D "riscv,sv39"; + clock-frequency =3D <100000000>; + i-cache-size =3D <0x8000>; + i-cache-sets =3D <256>; + i-cache-line-size =3D <64>; + d-cache-size =3D <0x8000>; + d-cache-sets =3D <128>; + d-cache-line-size =3D <64>; + next-level-cache =3D <&l2_cache>; + + cpu2_intc: interrupt-controller { + compatible =3D "andestech,cpu-intc", + "riscv,cpu-intc"; + #interrupt-cells =3D <1>; + interrupt-controller; + }; + }; + + cpu3: cpu@3 { + compatible =3D "andestech,ax45mp", "riscv"; + device_type =3D "cpu"; + reg =3D <3>; + riscv,isa-base =3D "rv64i"; + riscv,isa-extensions =3D "i", "m", "a", "f", "d", "c", + "zicntr", "zicsr", "zifencei", + "zihpm", "xandespmu"; + mmu-type =3D "riscv,sv39"; + clock-frequency =3D <100000000>; + i-cache-size =3D <0x8000>; + i-cache-sets =3D <256>; + i-cache-line-size =3D <64>; + d-cache-size =3D <0x8000>; + d-cache-sets =3D <128>; + d-cache-line-size =3D <64>; + next-level-cache =3D <&l2_cache>; + + cpu3_intc: interrupt-controller { + compatible =3D "andestech,cpu-intc", + "riscv,cpu-intc"; + #interrupt-cells =3D <1>; + interrupt-controller; + }; + }; + }; + + soc { + compatible =3D "simple-bus"; + ranges; + interrupt-parent =3D <&plic>; + #address-cells =3D <2>; + #size-cells =3D <2>; + + plmt: timer@100000 { + compatible =3D "andestech,qilai-plmt", "andestech,plmt0"; + reg =3D <0x0 0x00100000 0x0 0x100000>; + interrupts-extended =3D <&cpu0_intc 7>, + <&cpu1_intc 7>, + <&cpu2_intc 7>, + <&cpu3_intc 7>; + }; + + l2_cache: cache-controller@200000 { + compatible =3D "andestech,qilai-ax45mp-cache", + "andestech,ax45mp-cache", "cache"; + reg =3D <0x0 0x00200000 0x0 0x100000>; + interrupts =3D <16 IRQ_TYPE_LEVEL_HIGH>; + cache-line-size =3D <64>; + cache-level =3D <2>; + cache-sets =3D <2048>; + cache-size =3D <0x200000>; + cache-unified; + }; + + plic_sw: interrupt-controller@400000 { + compatible =3D "andestech,qilai-plicsw", + "andestech,plicsw"; + reg =3D <0x0 0x00400000 0x0 0x400000>; + interrupts-extended =3D <&cpu0_intc 3>, + <&cpu1_intc 3>, + <&cpu2_intc 3>, + <&cpu3_intc 3>; + }; + + plic: interrupt-controller@2000000 { + compatible =3D "andestech,qilai-plic", + "andestech,nceplic100"; + reg =3D <0x0 0x02000000 0x0 0x2000000>; + #address-cells =3D <0>; + #interrupt-cells =3D <2>; + interrupt-controller; + interrupts-extended =3D <&cpu0_intc 11>, <&cpu0_intc 9>, + <&cpu1_intc 11>, <&cpu1_intc 9>, + <&cpu2_intc 11>, <&cpu2_intc 9>, + <&cpu3_intc 11>, <&cpu3_intc 9>; + riscv,ndev =3D <71>; + }; + + uart0: serial@30300000 { + compatible =3D "andestech,uart16550", "ns16550a"; + reg =3D <0x0 0x30300000 0x0 0x100000>; + interrupts =3D <9 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency =3D <50000000>; + reg-offset =3D <32>; + reg-shift =3D <2>; + reg-io-width =3D <4>; + no-loopback-test; + }; + }; +}; --=20 2.34.1 From nobody Tue Oct 7 08:32:09 2025 Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3438F2D77EB for ; Fri, 11 Jul 2025 13:31:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.248.80.70 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; 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Fri, 11 Jul 2025 21:30:43 +0800 (+08) (envelope-from ben717@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS31.andestech.com (10.0.1.89) with Microsoft SMTP Server id 14.3.498.0; Fri, 11 Jul 2025 21:30:42 +0800 From: Ben Zong-You Xie To: CC: , , , , , , , , , , , , , , , , Ben Zong-You Xie Subject: [PATCH v2 7/9] riscv: dts: andes: add Voyager board device tree Date: Fri, 11 Jul 2025 21:30:23 +0800 Message-ID: <20250711133025.2192404-8-ben717@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250711133025.2192404-1-ben717@andestech.com> References: <20250711133025.2192404-1-ben717@andestech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-DKIM-Results: atcpcs31.andestech.com; dkim=none; X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL: Atcsqr.andestech.com 56BDUhoV014685 Content-Type: text/plain; charset="utf-8" Introduce the device tree support for Voyager development board. Currently only support booting into console with only uart, other features will be added later. Signed-off-by: Ben Zong-You Xie --- arch/riscv/boot/dts/Makefile | 1 + arch/riscv/boot/dts/andes/Makefile | 2 ++ arch/riscv/boot/dts/andes/qilai-voyager.dts | 28 +++++++++++++++++++++ 3 files changed, 31 insertions(+) create mode 100644 arch/riscv/boot/dts/andes/Makefile create mode 100644 arch/riscv/boot/dts/andes/qilai-voyager.dts diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile index 64a898da9aee..3b99e91efa25 100644 --- a/arch/riscv/boot/dts/Makefile +++ b/arch/riscv/boot/dts/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 subdir-y +=3D allwinner +subdir-y +=3D andes subdir-y +=3D canaan subdir-y +=3D microchip subdir-y +=3D renesas diff --git a/arch/riscv/boot/dts/andes/Makefile b/arch/riscv/boot/dts/andes= /Makefile new file mode 100644 index 000000000000..c545c668ef70 --- /dev/null +++ b/arch/riscv/boot/dts/andes/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_ANDES) +=3D qilai-voyager.dtb diff --git a/arch/riscv/boot/dts/andes/qilai-voyager.dts b/arch/riscv/boot/= dts/andes/qilai-voyager.dts new file mode 100644 index 000000000000..fa7d2b32a9b4 --- /dev/null +++ b/arch/riscv/boot/dts/andes/qilai-voyager.dts @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2025 Andes Technology Corporation. All rights reserved. + */ + +#include "qilai.dtsi" + +/ { + model =3D "Voyager"; + compatible =3D "andestech,voyager", "andestech,qilai"; + + aliases { + serial0 =3D &uart0; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + memory@400000000 { + device_type =3D "memory"; + reg =3D <0x4 0x00000000 0x4 0x00000000>; + }; +}; + +&uart0 { + status =3D "okay"; +}; --=20 2.34.1 From nobody Tue Oct 7 08:32:09 2025 Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 939BD2D3A7C for ; Fri, 11 Jul 2025 13:31:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.248.80.70 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752240708; cv=none; b=H2M1EzCkviYQAl3SykGYf/kdZErePmwqQ4qWkzShH1b0Q9OQmsrkWNtzXACYacWTJP+LiLv48nz4rxr6YnvnWnASXRm4S4ljfP67JW21MBOmrcBklS3C9A6jNnVvnbN+nc/PAiHCiZLFtowh3gzYu+/xO+i5WGczs0gbAY8dSjo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752240708; c=relaxed/simple; bh=GI90PMG6oLQIFp7nu69CEzicczRXgBh1hr6PYZ2QH+4=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Fz+UUU11XonrMBIR0uihMzRF7o3NcH/uygxaHt+HTAu/VIRvLNrsspB4eRJyn+h8MuXYdPl4Yqf4YzQHHz0qpfS+FRGbp96nYSuNC58lVn88fGn4SYepxS3vruuRYoB7FB/ck1sodvfDD4YheCINolDMHtuhUwt3L1vC5irUJek= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=andestech.com; spf=pass smtp.mailfrom=andestech.com; arc=none smtp.client-ip=60.248.80.70 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=andestech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=andestech.com Received: from mail.andestech.com (ATCPCS31.andestech.com [10.0.1.89]) by Atcsqr.andestech.com with ESMTPS id 56BDUiZS014964 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 11 Jul 2025 21:30:44 +0800 (+08) (envelope-from ben717@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS31.andestech.com (10.0.1.89) with Microsoft SMTP Server id 14.3.498.0; Fri, 11 Jul 2025 21:30:44 +0800 From: Ben Zong-You Xie To: CC: , , , , , , , , , , , , , , , , Ben Zong-You Xie , Conor Dooley Subject: [PATCH v2 8/9] riscv: defconfig: enable Andes SoC Date: Fri, 11 Jul 2025 21:30:24 +0800 Message-ID: <20250711133025.2192404-9-ben717@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250711133025.2192404-1-ben717@andestech.com> References: <20250711133025.2192404-1-ben717@andestech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-DKIM-Results: atcpcs31.andestech.com; dkim=none; X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL: Atcsqr.andestech.com 56BDUiZS014964 Content-Type: text/plain; charset="utf-8" Enable Andes SoC config in defconfig to allow the default upstream kernel to boot on Voyager board. Acked-by: Conor Dooley Signed-off-by: Ben Zong-You Xie --- arch/riscv/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index fe8bd8afb418..12f5f6ec00fa 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -22,6 +22,7 @@ CONFIG_USER_NS=3Dy CONFIG_CHECKPOINT_RESTORE=3Dy CONFIG_BLK_DEV_INITRD=3Dy CONFIG_PROFILING=3Dy +CONFIG_ARCH_ANDES=3Dy CONFIG_ARCH_MICROCHIP=3Dy CONFIG_ARCH_SIFIVE=3Dy CONFIG_ARCH_SOPHGO=3Dy --=20 2.34.1 From nobody Tue Oct 7 08:32:09 2025 Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 282AF2E0B44 for ; Fri, 11 Jul 2025 13:31:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.248.80.70 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752240711; cv=none; b=rnez66jiI5jqv8bTXSAOQXkBd0oQUatYNFeRHRCF0hpULe/BSRzri1DT7CxAWKwPjjuR7aZr26NZczTPzaNnVXpnn/ZrnvZgDC/J4tz+vKf1wLBYY3E4w+CcsV7xBoJkqTHCkAZ3DX9gQ1dC4MFElNLSRZD2TIc5UNoxCq0kjdY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752240711; c=relaxed/simple; bh=rxJr4tpi6DEPFP82taMvG15uH3s3cawAV/8Tlt7o4EM=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=VNJiv8SjZskmMH/y9oRL1KsfL7vqBB0C8jvI6+B9uno6Lrf9YXpylRcaiHg22P5QfEp4vHmMcmvPcG0eJmUdAcUjX0c6EYZcglOHkpLw73/oN5wOev7U+Vxbw/dGp/tS4GZjt4uqMNR58yVQRmCvZNJRng4wHsmYn3XC5mrh3tg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=andestech.com; spf=pass smtp.mailfrom=andestech.com; arc=none smtp.client-ip=60.248.80.70 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=andestech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=andestech.com Received: from mail.andestech.com (ATCPCS31.andestech.com [10.0.1.89]) by Atcsqr.andestech.com with ESMTPS id 56BDUjes015105 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 11 Jul 2025 21:30:45 +0800 (+08) (envelope-from ben717@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS31.andestech.com (10.0.1.89) with Microsoft SMTP Server id 14.3.498.0; Fri, 11 Jul 2025 21:30:45 +0800 From: Ben Zong-You Xie To: CC: , , , , , , , , , , , , , , , , Ben Zong-You Xie Subject: [PATCH v2 9/9] MAINTAINERS: Add entry for Andes SoC Date: Fri, 11 Jul 2025 21:30:25 +0800 Message-ID: <20250711133025.2192404-10-ben717@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250711133025.2192404-1-ben717@andestech.com> References: <20250711133025.2192404-1-ben717@andestech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-DKIM-Results: atcpcs31.andestech.com; dkim=none; X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL: Atcsqr.andestech.com 56BDUjes015105 Content-Type: text/plain; charset="utf-8" Add entry for Andes SoC maintainer and related files Signed-off-by: Ben Zong-You Xie --- MAINTAINERS | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index d79d546c2f95..3e16da28de50 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -21318,6 +21318,15 @@ F: drivers/irqchip/irq-riscv-intc.c F: include/linux/irqchip/riscv-aplic.h F: include/linux/irqchip/riscv-imsic.h =20 +RISC-V ANDES SoC Support +M: Ben Zong-You Xie +S: Maintained +T: git: https://github.com/ben717-linux/linux +F: Documentation/devicetree/bindings/interrupt-controller/andestech,plicsw= .yaml +F: Documentation/devicetree/bindings/riscv/andes.yaml +F: Documentation/devicetree/bindings/timer/andestech,plmt0.yaml +F: arch/riscv/boot/dts/andes/ + RISC-V ARCHITECTURE M: Paul Walmsley M: Palmer Dabbelt --=20 2.34.1