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charset="utf-8" The vfe in qcs8300 is version 690, it is same as vfe used in sa8775p. vfe gen3 have support for vfe 690. Signed-off-by: Vikram Sharma --- .../platform/qcom/camss/camss-vfe-gen3.c | 4 +- drivers/media/platform/qcom/camss/camss-vfe.c | 2 + drivers/media/platform/qcom/camss/camss.c | 180 ++++++++++++++++++ 3 files changed, 185 insertions(+), 1 deletion(-) diff --git a/drivers/media/platform/qcom/camss/camss-vfe-gen3.c b/drivers/m= edia/platform/qcom/camss/camss-vfe-gen3.c index a5eddc8c76ae..92ee7c7b8a47 100644 --- a/drivers/media/platform/qcom/camss/camss-vfe-gen3.c +++ b/drivers/media/platform/qcom/camss/camss-vfe-gen3.c @@ -13,7 +13,9 @@ #include "camss-vfe.h" =20 #define IS_VFE_690(vfe) \ - (vfe->camss->res->version =3D=3D CAMSS_8775P ? true : false) + ((vfe->camss->res->version =3D=3D CAMSS_8775P) ||\ + (vfe->camss->res->version =3D=3D CAMSS_8300) ?\ + true : false) =20 #define BUS_REG_BASE_690 \ (vfe_is_lite(vfe) ? 0x480 : 0x400) diff --git a/drivers/media/platform/qcom/camss/camss-vfe.c b/drivers/media/= platform/qcom/camss/camss-vfe.c index 99cbe09343f2..1d40184d7d04 100644 --- a/drivers/media/platform/qcom/camss/camss-vfe.c +++ b/drivers/media/platform/qcom/camss/camss-vfe.c @@ -344,6 +344,7 @@ static u32 vfe_src_pad_code(struct vfe_line *line, u32 = sink_code, case CAMSS_8x96: case CAMSS_8250: case CAMSS_8280XP: + case CAMSS_8300: case CAMSS_845: case CAMSS_8550: case CAMSS_8775P: @@ -1974,6 +1975,7 @@ static int vfe_bpl_align(struct vfe_device *vfe) case CAMSS_7280: case CAMSS_8250: case CAMSS_8280XP: + case CAMSS_8300: case CAMSS_845: case CAMSS_8550: case CAMSS_8775P: diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/plat= form/qcom/camss/camss.c index b0fd5fd307a1..abfaa489cc0c 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -2623,6 +2623,186 @@ static const struct camss_subdev_resources csid_res= _8300[] =3D { }, }; =20 +static const struct camss_subdev_resources vfe_res_8300[] =3D { + /* VFE0 */ + { + .regulators =3D {}, + .clock =3D { "cpas_vfe0", "vfe0", "vfe0_fast_ahb", + "cpas_ahb", "gcc_axi_hf", "gcc_axi_sf", + "core_ahb", "cpas_fast_ahb_clk", "camnoc_axi", + "icp_ahb"}, + .clock_rate =3D { + { 0 }, + { 480000000 }, + { 300000000, 400000000 }, + { 300000000, 400000000 }, + { 0 }, + { 0 }, + { 0, 80000000 }, + { 300000000, 400000000 }, + { 400000000 }, + { 0 }, + }, + .reg =3D { "vfe0" }, + .interrupt =3D { "vfe0" }, + .vfe =3D { + .line_num =3D 3, + .is_lite =3D false, + .has_pd =3D false, + .pd_name =3D NULL, + .hw_ops =3D &vfe_ops_gen3, + .formats_rdi =3D &vfe_formats_rdi_845, + .formats_pix =3D &vfe_formats_pix_845 + } + }, + /* VFE1 */ + { + .regulators =3D {}, + .clock =3D { "cpas_vfe1", "vfe1", "vfe1_fast_ahb", + "cpas_ahb", "gcc_axi_hf", "gcc_axi_sf", + "core_ahb", "cpas_fast_ahb_clk", "camnoc_axi", + "icp_ahb"}, + .clock_rate =3D { + { 0 }, + { 480000000 }, + { 300000000, 400000000 }, + { 300000000, 400000000 }, + { 0 }, + { 0 }, + { 0, 80000000 }, + { 300000000, 400000000 }, + { 400000000 }, + { 0 }, + }, + .reg =3D { "vfe1" }, + .interrupt =3D { "vfe1" }, + .vfe =3D { + .line_num =3D 3, + .is_lite =3D false, + .has_pd =3D false, + .pd_name =3D NULL, + .hw_ops =3D &vfe_ops_gen3, + .formats_rdi =3D &vfe_formats_rdi_845, + .formats_pix =3D &vfe_formats_pix_845 + } + }, + /* VFE2 (lite) */ + { + .regulators =3D {}, + .clock =3D { "cpas_vfe_lite", "vfe_lite_ahb", + "vfe_lite_csid", "vfe_lite_cphy_rx", + "vfe_lite"}, + .clock_rate =3D { + { 0, 0, 0, 0 }, + { 300000000, 400000000, 400000000, 400000000 }, + { 400000000, 400000000, 400000000, 400000000 }, + { 400000000, 400000000, 400000000, 400000000 }, + { 480000000, 600000000, 600000000, 600000000 }, + }, + .reg =3D { "vfe_lite0" }, + .interrupt =3D { "vfe_lite0" }, + .vfe =3D { + .line_num =3D 4, + .is_lite =3D true, + .hw_ops =3D &vfe_ops_gen3, + .formats_rdi =3D &vfe_formats_rdi_845, + .formats_pix =3D &vfe_formats_pix_845 + } + }, + /* VFE3 (lite) */ + { + .regulators =3D {}, + .clock =3D { "cpas_vfe_lite", "vfe_lite_ahb", + "vfe_lite_csid", "vfe_lite_cphy_rx", + "vfe_lite"}, + .clock_rate =3D { + { 0, 0, 0, 0 }, + { 300000000, 400000000, 400000000, 400000000 }, + { 400000000, 400000000, 400000000, 400000000 }, + { 400000000, 400000000, 400000000, 400000000 }, + { 480000000, 600000000, 600000000, 600000000 }, + }, + .reg =3D { "vfe_lite1" }, + .interrupt =3D { "vfe_lite1" }, + .vfe =3D { + .line_num =3D 4, + .is_lite =3D true, + .hw_ops =3D &vfe_ops_gen3, + .formats_rdi =3D &vfe_formats_rdi_845, + .formats_pix =3D &vfe_formats_pix_845 + } + }, + /* VFE4 (lite) */ + { + .regulators =3D {}, + .clock =3D { "cpas_vfe_lite", "vfe_lite_ahb", + "vfe_lite_csid", "vfe_lite_cphy_rx", + "vfe_lite"}, + .clock_rate =3D { + { 0, 0, 0, 0 }, + { 300000000, 400000000, 400000000, 400000000 }, + { 400000000, 400000000, 400000000, 400000000 }, + { 400000000, 400000000, 400000000, 400000000 }, + { 480000000, 600000000, 600000000, 600000000 }, + }, + .reg =3D { "vfe_lite2" }, + .interrupt =3D { "vfe_lite2" }, + .vfe =3D { + .line_num =3D 4, + .is_lite =3D true, + .hw_ops =3D &vfe_ops_gen3, + .formats_rdi =3D &vfe_formats_rdi_845, + .formats_pix =3D &vfe_formats_pix_845 + } + }, + /* VFE5 (lite) */ + { + .regulators =3D {}, + .clock =3D { "cpas_vfe_lite", "vfe_lite_ahb", + "vfe_lite_csid", "vfe_lite_cphy_rx", + "vfe_lite"}, + .clock_rate =3D { + { 0, 0, 0, 0 }, + { 300000000, 400000000, 400000000, 400000000 }, + { 400000000, 400000000, 400000000, 400000000 }, + { 400000000, 400000000, 400000000, 400000000 }, + { 480000000, 600000000, 600000000, 600000000 }, + }, + .reg =3D { "vfe_lite3" }, + .interrupt =3D { "vfe_lite3" }, + .vfe =3D { + .line_num =3D 4, + .is_lite =3D true, + .hw_ops =3D &vfe_ops_gen3, + .formats_rdi =3D &vfe_formats_rdi_845, + .formats_pix =3D &vfe_formats_pix_845 + } + }, + /* VFE6 (lite) */ + { + .regulators =3D {}, + .clock =3D { "cpas_vfe_lite", "vfe_lite_ahb", + "vfe_lite_csid", "vfe_lite_cphy_rx", + "vfe_lite"}, + .clock_rate =3D { + { 0, 0, 0, 0 }, + { 300000000, 400000000, 400000000, 400000000 }, + { 400000000, 400000000, 400000000, 400000000 }, + { 400000000, 400000000, 400000000, 400000000 }, + { 480000000, 600000000, 600000000, 600000000 }, + }, + .reg =3D { "vfe_lite4" }, + .interrupt =3D { "vfe_lite4" }, + .vfe =3D { + .line_num =3D 4, + .is_lite =3D true, + .hw_ops =3D &vfe_ops_gen3, + .formats_rdi =3D &vfe_formats_rdi_845, + .formats_pix =3D &vfe_formats_pix_845 + } + }, +}; + static const struct camss_subdev_resources csiphy_res_8775p[] =3D { /* CSIPHY0 */ { --=20 2.25.1