From nobody Tue Oct 7 08:32:09 2025 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B99322E9EC3; Fri, 11 Jul 2025 14:58:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.112 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752245888; cv=pass; b=u+fp5BfQn+olsRJL9OlAq0WyiLzhWLjouWc/KZjkfu/TeL6CwNArPzsUmRBRgfaajtp3MfxQNQ8QPp8vvrGdU5diiEFy1ZnSbsuSDpKV7Da4quTFlqHNv+uxrjPdT8tESi/uHlZLDnqEivYFhnwgQJ97lXVGWWR3bVkhrFqFVqg= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752245888; c=relaxed/simple; bh=b3eBR1H4nBDi8jkofVxCLTt5N7YnGgYhoVIt7L4QLUM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=XI9uZp6oa5JHiSmd76tzAsB3fvBNkT9iOq60Pa/I194bMICV8W6U7kpm+p509n3eygKd7QmiRgmm5FNxQs07vnAu3n8mT9qS0M9jcZbnPDLUT+kLU9tWc04M1XbkR+O6M7QImYFZZrE8wRGZeftBnK6AUc880cxiC5fWqw3tLwg= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (1024-bit key) header.d=collabora.com header.i=nicolas.frattaroli@collabora.com header.b=NQrPo/RO; arc=pass smtp.client-ip=136.143.188.112 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=collabora.com header.i=nicolas.frattaroli@collabora.com header.b="NQrPo/RO" ARC-Seal: i=1; a=rsa-sha256; t=1752245869; cv=none; d=zohomail.com; s=zohoarc; b=gUISBzJNp/J3+ipDHhCGxFk4104DqECAChH3INJYk5klQJgaqZnvTQZqQYRzhxmCFyi9ncNOinnt9z6fuUJNaBpBhChpUH0BuuggJD2Rzhb1YoZxmqIxYHrTHzcBYkD6t2MlhJghqJHiB9kYl90rnzXloduKPJDo1rzEvUFjeyc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752245869; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=9PEARQKKf/9p+jlcrAMfNzhevLXRjyodsZ6OZ49W5QA=; b=evHJ8Cyt4Qe7MK595+5A40U0HWg91GOOuRU7UvGFDQzYQS+g+pyyetQ2GWgxfz5U7bN40GhgqP9rRTcg9XTIcfw6QP28voIZOJazGP/n8oy8F2GpO8wnUvDdBEN9K/4yGhvviEc3pex2ggfUrSO1/LJDLq/gY3BPrTQjNpsntqY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=collabora.com; spf=pass smtp.mailfrom=nicolas.frattaroli@collabora.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1752245869; s=zohomail; d=collabora.com; i=nicolas.frattaroli@collabora.com; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=9PEARQKKf/9p+jlcrAMfNzhevLXRjyodsZ6OZ49W5QA=; b=NQrPo/RO3TTaNvHv8m6D3Tbwyn+2J28Xf4GAYryCvri/oUV3aDFalTqMywaaoWH1 tgiw2SmmnMNEEdXCdVWCBAr0qJhYfTEP3U6DDCJdB8GUrUPYOGqo4JrdLjqN8ilYLa5 vFRpaJxp/Vb7/9mgrf4tVTaXO6YvwyWBUl/wgnPQ= Received: by mx.zohomail.com with SMTPS id 175224586740314.377934690162078; Fri, 11 Jul 2025 07:57:47 -0700 (PDT) From: Nicolas Frattaroli Date: Fri, 11 Jul 2025 16:57:33 +0200 Subject: [PATCH 1/5] dt-bindings: mfd: syscon: Add mt8196 fdvfs syscons Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250711-mt8196-cpufreq-v1-1-e1b0a3b4ac61@collabora.com> References: <20250711-mt8196-cpufreq-v1-0-e1b0a3b4ac61@collabora.com> In-Reply-To: <20250711-mt8196-cpufreq-v1-0-e1b0a3b4ac61@collabora.com> To: Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , "Rafael J. Wysocki" , Viresh Kumar , Hector Yuan Cc: kernel@collabora.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-pm@vger.kernel.org, Nicolas Frattaroli X-Mailer: b4 0.14.2 The MT8196 SoC uses two syscon ranges for CPU DVFS that are separate from each other. One, mt8196-fdvfs-config, is used to check for a magic number at that memory address to verify that fdvfs should be used. The other, mt8196-fdvfs, is used to configure the desired frequency for the DVFS controller for each CPU core. Signed-off-by: Nicolas Frattaroli --- Documentation/devicetree/bindings/mfd/syscon.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentat= ion/devicetree/bindings/mfd/syscon.yaml index 27672adeb1fedb7c81b8ae86c35f4f3b26d5516f..5ee49d2ba0cdb72dd697a0fd71c= 8416ad4fd2c1e 100644 --- a/Documentation/devicetree/bindings/mfd/syscon.yaml +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml @@ -88,6 +88,8 @@ select: - mediatek,mt8135-pctl-a-syscfg - mediatek,mt8135-pctl-b-syscfg - mediatek,mt8173-pctl-a-syscfg + - mediatek,mt8196-fdvfs + - mediatek,mt8196-fdvfs-config - mediatek,mt8365-syscfg - microchip,lan966x-cpu-syscon - microchip,mpfs-sysreg-scb @@ -194,6 +196,8 @@ properties: - mediatek,mt8135-pctl-a-syscfg - mediatek,mt8135-pctl-b-syscfg - mediatek,mt8173-pctl-a-syscfg + - mediatek,mt8196-fdvfs + - mediatek,mt8196-fdvfs-config - mediatek,mt8365-infracfg-nao - mediatek,mt8365-syscfg - microchip,lan966x-cpu-syscon --=20 2.50.0 From nobody Tue Oct 7 08:32:09 2025 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D3C342EA732; Fri, 11 Jul 2025 14:58:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.112 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752245892; cv=pass; b=eFMXdbTewklN16jxIjrJCyb1YZI5EWCoqwgxedxAQlgTh3mym3mc5tf+ltmbJBmz8MXohlzIuO2NHm+kXUuLO4w0eEDPqftqyWiF9j7/gEA5otm8aqCtdHtt86jXOH6non0WFqQgNLRBrKna/fdJAl89vexjJUOVeP4s9vTK8ro= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752245892; c=relaxed/simple; bh=YLtt44xoNziAwSpmKjypho6rCb1JDd9izmCr3ewXM9o=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=kSYgZCqIFlaAvOlLArpHQXywPI6y5v7BJdBZMTBZGNf5+IeOtpkv9+T/DbtxdJjNpgX6wgAVSxSyWC1mBwtcpiHy+Yr8nhnTATHnUzIcxosDtIh5bPDz2RiUAIgiIvmXeGglu++Vm0knm90K0sYnWkP6cRTqyYy/p3zM+cRjdrw= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (1024-bit key) header.d=collabora.com header.i=nicolas.frattaroli@collabora.com header.b=PLZ6DB7h; arc=pass smtp.client-ip=136.143.188.112 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=collabora.com header.i=nicolas.frattaroli@collabora.com header.b="PLZ6DB7h" ARC-Seal: i=1; a=rsa-sha256; t=1752245873; cv=none; d=zohomail.com; s=zohoarc; b=AJJvdNxsOEJnho+xtOqxoDRJ6EdIYlIACMEE+8Q0YPbliNKu8R04mSm0JxqYLdb92lVRrVKZ0LSKfeu0BmfzN9ccG1V5oKu83eL5OLYerMTgvc1YDkaPhSo9nAJjuEiUuDeORfHlYEMDLjArW3+u3gt73IeDLRU6dauhddme84w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752245873; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=Dzcn15vklIxbdKo0iUkTyzz8Nnt7ea8eiW8ExHt379E=; b=a5Spyo14Pjy3FFA+yOTDCdnu80+nBXs6Cpa6xblTxaxWgHjinAfcAJGHe58TY5nuLc5JXPvgXaqMPmiENdzHkIDx+JgdC889x12qaUmDKtsSiPOKksKyA3Gfk47am01/PKfCDTeKM88+bulkPYy0WrrDWG//dYviRJdZmZOWiXQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=collabora.com; spf=pass smtp.mailfrom=nicolas.frattaroli@collabora.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1752245873; s=zohomail; d=collabora.com; i=nicolas.frattaroli@collabora.com; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=Dzcn15vklIxbdKo0iUkTyzz8Nnt7ea8eiW8ExHt379E=; b=PLZ6DB7h7PY7nEQcuRD+SZKsEKlKQRMB9/mcbsENmfn4/MVD/ws2iJ3i9GSXYiFW JHMJO8IOAvylMVMC59BohWVwuVIg2ipJKmdxPXgw5zQek8q3j+pQamPBFCvE63jkczX vqn3TFTihMtyD7Q8O11p5WumdC7ZF6J8CPmG1yi0= Received: by mx.zohomail.com with SMTPS id 1752245870786939.833352414672; Fri, 11 Jul 2025 07:57:50 -0700 (PDT) From: Nicolas Frattaroli Date: Fri, 11 Jul 2025 16:57:34 +0200 Subject: [PATCH 2/5] dt-bindings: cpufreq: mediatek-hw: add mt8196 cpufreq binding Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250711-mt8196-cpufreq-v1-2-e1b0a3b4ac61@collabora.com> References: <20250711-mt8196-cpufreq-v1-0-e1b0a3b4ac61@collabora.com> In-Reply-To: <20250711-mt8196-cpufreq-v1-0-e1b0a3b4ac61@collabora.com> To: Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , "Rafael J. Wysocki" , Viresh Kumar , Hector Yuan Cc: kernel@collabora.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-pm@vger.kernel.org, Nicolas Frattaroli X-Mailer: b4 0.14.2 The MediaTek MT8196 SoC's cpufreq has three performance domains, each with their own reg item, compared to the existing mediatek,cpufreq-hw compatible that only uses two. In addition, the hardware requires special handling by driver implementations, so the new compatible is needed for more than just the difference in regs. Add the mediatek,mt8196-cpufreq-hw compatible, increase the maxItems of reg, and reduce it back down to 2 for mediatek,cpufreq-hw in an if condition. A second example is added to help verify the binding's correctness and document its use appropriately, though some awkward label names had to be chosen as dt-extract-example concatenates the entire list of examples for each binding into a single file, so naming conflicts between them can occur. Signed-off-by: Nicolas Frattaroli --- .../bindings/cpufreq/cpufreq-mediatek-hw.yaml | 64 ++++++++++++++++++= +++- 1 file changed, 62 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek-hw.= yaml b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek-hw.yaml index d0aecde2b89b1896c01ea8ae24f26032d8075a11..cee2678b926f845ab131cecef40= 3e127a63fabb2 100644 --- a/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek-hw.yaml +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek-hw.yaml @@ -16,11 +16,14 @@ description: =20 properties: compatible: - const: mediatek,cpufreq-hw + contains: + enum: + - mediatek,cpufreq-hw + - mediatek,mt8196-cpufreq-hw =20 reg: minItems: 1 - maxItems: 2 + maxItems: 3 description: Addresses and sizes for the memory of the HW bases in each frequency domain. Each entry corresponds to @@ -40,6 +43,18 @@ required: =20 additionalProperties: false =20 +allOf: + - if: + properties: + compatible: + contains: + enum: + - mediatek,cpufreq-hw + then: + properties: + regs: + maxItems: 2 + examples: - | cpus { @@ -68,3 +83,48 @@ examples: #performance-domain-cells =3D <1>; }; }; + - | + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + mt8196_cpu0: cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a720"; + enable-method =3D "psci"; + performance-domains =3D <&mt8196_performance 0>; + reg =3D <0x000>; + }; + + /* ... */ + + mt8196_cpu6: cpu@600 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-x4"; + enable-method =3D "psci"; + performance-domains =3D <&mt8196_performance 1>; + reg =3D <0x600>; + }; + + mt8196_cpu7: cpu@700 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-x925"; + enable-method =3D "psci"; + performance-domains =3D <&mt8196_performance 2>; + reg =3D <0x700>; + }; + }; + + /* ... */ + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + mt8196_performance: performance-controller@c2c0f20 { + compatible =3D "mediatek,mt8196-cpufreq-hw"; + reg =3D <0 0xc2c0f20 0 0x120>, <0 0xc2c1040 0 0x120>, + <0 0xc2c1160 0 0x120>; + #performance-domain-cells =3D <1>; + }; + }; --=20 2.50.0 From nobody Tue Oct 7 08:32:09 2025 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5240B2EA49C; Fri, 11 Jul 2025 14:58:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.112 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752245896; cv=pass; b=T6sLa0jWhpw3kQn5o45p/90Rc5UTSktqr99Wek4hxmxH4NOmpa/BAPwybTTL3K00svdcRcRbPtoWaN8KGyVewiZrykKnLI77Mc67NE+cF2Yvv3Io9KXBRaGEzCQvnU4L/gOrcQpSxYxmGes1A9ActphShAHZGa4TAp7KJHdg9nE= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752245896; c=relaxed/simple; bh=T/XZsQbQLrcIV9fFKHUv1e6mI5VjQpUWX7EjJia/LTU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ltYBRpRqAJKDuvg284XLHG9mZpfo24nSSzvYBN03WGFkN19M/S1A4KvmtarBq8updavDyNX+pduE4OibV8uNvjMiIr+Mo5UguHXG+OZKKnkY4wfsyUvsg/Y0lvu0b0A9ZembKVkMNiOuFym2xVahV7mg66cxI8aBU8uFlLN/VIA= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (1024-bit key) header.d=collabora.com header.i=nicolas.frattaroli@collabora.com header.b=dncZ4K9L; arc=pass smtp.client-ip=136.143.188.112 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=collabora.com header.i=nicolas.frattaroli@collabora.com header.b="dncZ4K9L" ARC-Seal: i=1; a=rsa-sha256; t=1752245875; cv=none; d=zohomail.com; s=zohoarc; b=Sbo7WLHYGAc49B5RUnp/nZKGY19T10UabJVAINX76rzQqrvbeqc237Ivdc2o8iTBsv6eSmGuuXKFBbbHIJSH3eujjCWEY57dOP2fpq5OtKH1hJFO1Ot1dwaBdk9DNyMUeOYrQRf7CRNPoypCq8cFM1QE47kd+zDVEjo/F050DqU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752245875; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=Rl4uSsmt0R6ta2ds9zDGarKw8XggCRJaKwQecyR3iSA=; b=lyWrtzxHomY1LT1lb/qyuScyIMV7gKCRPoE3c3Bx6CGpHjmvjPD0YIyWa0Zxepzx9yvjkOKGp2RTEl0Yyq3Rc1nXCD+TLExO2rnf25fssC0jUtv4yM8NI77cJzEXzp8cRLOxX2AdcMiPJArIk5ozi+BCZxDt7iAUhb+zUwQeWPc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=collabora.com; spf=pass smtp.mailfrom=nicolas.frattaroli@collabora.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1752245875; s=zohomail; d=collabora.com; i=nicolas.frattaroli@collabora.com; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=Rl4uSsmt0R6ta2ds9zDGarKw8XggCRJaKwQecyR3iSA=; b=dncZ4K9LDZnJZA9Kb6hls19yvSMJ8g8zlHpM+d4wvBeBhxAehFfmRJIRFRrJBzbT JXbY8eTvgJNDmWUUUDm7hbUZMSKnQnjXNMaHI1iIIzPYDGyfvffjk8Qz3fsTsZxvclx p/8TpHl04CH1dmgCA9S+sLBk0E5ozS+M4pXkflkI= Received: by mx.zohomail.com with SMTPS id 1752245874097527.3770039598888; Fri, 11 Jul 2025 07:57:54 -0700 (PDT) From: Nicolas Frattaroli Date: Fri, 11 Jul 2025 16:57:35 +0200 Subject: [PATCH 3/5] cpufreq: mediatek-hw: Refactor match data into struct Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250711-mt8196-cpufreq-v1-3-e1b0a3b4ac61@collabora.com> References: <20250711-mt8196-cpufreq-v1-0-e1b0a3b4ac61@collabora.com> In-Reply-To: <20250711-mt8196-cpufreq-v1-0-e1b0a3b4ac61@collabora.com> To: Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , "Rafael J. Wysocki" , Viresh Kumar , Hector Yuan Cc: kernel@collabora.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-pm@vger.kernel.org, Nicolas Frattaroli X-Mailer: b4 0.14.2 While the driver could get away with having the per-compatible match data just be an array of the reg offsets, the only thing it used it for right now, this doesn't really allow it to be extended in any meaningful way if some other per-variant information needs to be communicated. Refactor the code to make the DT match data a struct, which currently only contains a single member: the reg offsets. This will allow this struct to be extended with other members for other hardware variants. Signed-off-by: Nicolas Frattaroli --- drivers/cpufreq/mediatek-cpufreq-hw.c | 28 ++++++++++++++++++---------- 1 file changed, 18 insertions(+), 10 deletions(-) diff --git a/drivers/cpufreq/mediatek-cpufreq-hw.c b/drivers/cpufreq/mediat= ek-cpufreq-hw.c index 74f1b4c796e4cc9ebccf50dd4e165a1eba03136a..b2aba1842226c7d24a8b9599ea6= 2408cac9f803c 100644 --- a/drivers/cpufreq/mediatek-cpufreq-hw.c +++ b/drivers/cpufreq/mediatek-cpufreq-hw.c @@ -41,15 +41,22 @@ struct mtk_cpufreq_data { struct resource *res; void __iomem *base; int nr_opp; + const struct mtk_cpufreq_variant *variant; }; =20 -static const u16 cpufreq_mtk_offsets[REG_ARRAY_SIZE] =3D { - [REG_FREQ_LUT_TABLE] =3D 0x0, - [REG_FREQ_ENABLE] =3D 0x84, - [REG_FREQ_PERF_STATE] =3D 0x88, - [REG_FREQ_HW_STATE] =3D 0x8c, - [REG_EM_POWER_TBL] =3D 0x90, - [REG_FREQ_LATENCY] =3D 0x110, +struct mtk_cpufreq_variant { + const u16 reg_offsets[REG_ARRAY_SIZE]; +}; + +static const struct mtk_cpufreq_variant cpufreq_mtk_base_variant =3D { + .reg_offsets =3D { + [REG_FREQ_LUT_TABLE] =3D 0x0, + [REG_FREQ_ENABLE] =3D 0x84, + [REG_FREQ_PERF_STATE] =3D 0x88, + [REG_FREQ_HW_STATE] =3D 0x8c, + [REG_EM_POWER_TBL] =3D 0x90, + [REG_FREQ_LATENCY] =3D 0x110, + }, }; =20 static int __maybe_unused @@ -157,7 +164,7 @@ static int mtk_cpu_create_freq_table(struct platform_de= vice *pdev, =20 static int mtk_cpu_resources_init(struct platform_device *pdev, struct cpufreq_policy *policy, - const u16 *offsets) + const struct mtk_cpufreq_variant *variant) { struct mtk_cpufreq_data *data; struct device *dev =3D &pdev->dev; @@ -200,9 +207,10 @@ static int mtk_cpu_resources_init(struct platform_devi= ce *pdev, =20 data->base =3D base; data->res =3D res; + data->variant =3D variant; =20 for (i =3D REG_FREQ_LUT_TABLE; i < REG_ARRAY_SIZE; i++) - data->reg_bases[i] =3D base + offsets[i]; + data->reg_bases[i] =3D base + variant->reg_offsets[i]; =20 ret =3D mtk_cpu_create_freq_table(pdev, data); if (ret) { @@ -336,7 +344,7 @@ static void mtk_cpufreq_hw_driver_remove(struct platfor= m_device *pdev) } =20 static const struct of_device_id mtk_cpufreq_hw_match[] =3D { - { .compatible =3D "mediatek,cpufreq-hw", .data =3D &cpufreq_mtk_offsets }, + { .compatible =3D "mediatek,cpufreq-hw", .data =3D &cpufreq_mtk_base_vari= ant }, {} }; MODULE_DEVICE_TABLE(of, mtk_cpufreq_hw_match); --=20 2.50.0 From nobody Tue Oct 7 08:32:09 2025 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 318C02EAB78; Fri, 11 Jul 2025 14:58:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.112 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752245898; cv=pass; b=Aggz1MwRta6DOtxnRxOX5CNaS1ntNQEnB6YX/leOIs9zL7DMkOOpODChfCVWUS3fgPU3Yd4LCS85XzsrGn9k+luhMQ18CXzgTj6yzR9J6Q2g9+PMECIf2IRo+JoPs1REPFP3Amp74B5urfO4WhHVdjbDY6wqOwmdFr90Hg5bgiM= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752245898; c=relaxed/simple; bh=EjeP7OrDgKOt79C3FOGtxu/5R2W4xfEOnhRHSKf7BG8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=KBqJppNA4kW0nHf8AsPiPgNalxyyjats4ke2SE1otvpmDzApb66JyQp+m4m43AMEE7NfcUzOx+cTZ9DrZNAcqw5PIyCTQlFha2ulqdArHcgQ5gJaJH0guD7SCvF5kPkgWJcQeKkOvV2Y1AOCsh3w8bSlNMaGXZVO7IosrHh5OpA= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (1024-bit key) header.d=collabora.com header.i=nicolas.frattaroli@collabora.com header.b=aaqcBnF5; arc=pass smtp.client-ip=136.143.188.112 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=collabora.com header.i=nicolas.frattaroli@collabora.com header.b="aaqcBnF5" ARC-Seal: i=1; a=rsa-sha256; t=1752245879; cv=none; d=zohomail.com; s=zohoarc; b=mLT4odeGP3wtaLuuJNmMU4mcGOoofU0jqjV3UnHSpd9vUccGyc2MCwVWnfUY70ss4ksb32AtkbMcjzAt+vZd7EB8i9shS9RYaC5Qt8RjLb5pOFDfbVz9w9cFOw/w6y7fENObqG7ikgsgP1K+yZWgVsgKlHN9PPZ6vY/2IFGrnSA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752245879; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=kEyk9gUxmxGGqpdMez2kdxKmqgQQdyz75f8g3l8O+F0=; b=FYJPubdba2WS9Oxd+ltzCD+nVb4CVjmHzdoqQa3b1Ck/hUM1j7kIPSCgge51wfrr9KIp5wKdyA3VddFIMRYxsIK41Ie4NXNxmtZhtqDpSb0/0A7S0Y5v1exgUR2lr5ZaMdwoHA3mp/kXrKToFboZmq+kioffTDkxxM8N1kqXNUQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=collabora.com; spf=pass smtp.mailfrom=nicolas.frattaroli@collabora.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1752245879; s=zohomail; d=collabora.com; i=nicolas.frattaroli@collabora.com; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=kEyk9gUxmxGGqpdMez2kdxKmqgQQdyz75f8g3l8O+F0=; b=aaqcBnF5Xda15uuNKnHDj3Hd2rA3hsPqIm8XjzsJdb6WHPd4bF7K+v99IX3Js5gJ Qn1UlapnRbcJDp2ycM69mTk/A2n/Ncie4DqvBn7zNOZh5r7xL/Ip3dViuygldQedsVp WN5bhr5PgzCUCzHgtj9G+1mVEB0AqCaBmJwsNjzc= Received: by mx.zohomail.com with SMTPS id 1752245877398787.5849825391359; Fri, 11 Jul 2025 07:57:57 -0700 (PDT) From: Nicolas Frattaroli Date: Fri, 11 Jul 2025 16:57:36 +0200 Subject: [PATCH 4/5] cpufreq: mediatek-hw: Separate per-domain and per-instance data Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250711-mt8196-cpufreq-v1-4-e1b0a3b4ac61@collabora.com> References: <20250711-mt8196-cpufreq-v1-0-e1b0a3b4ac61@collabora.com> In-Reply-To: <20250711-mt8196-cpufreq-v1-0-e1b0a3b4ac61@collabora.com> To: Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , "Rafael J. Wysocki" , Viresh Kumar , Hector Yuan Cc: kernel@collabora.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-pm@vger.kernel.org, Nicolas Frattaroli X-Mailer: b4 0.14.2 As it stood, the mediatek cpufreq driver could get away with never really having a private driver instance struct. This is because all data was stored in the per-domain structs. However, this complicates matters when actual per-instance data like the variant struct is introduced. Instead of having a pointer to it for every domain, have a pointer to a global "priv" struct that can be extended over time, and rename the "data" struct to "domain" to distinguish its purpose better. Signed-off-by: Nicolas Frattaroli --- drivers/cpufreq/mediatek-cpufreq-hw.c | 42 ++++++++++++++++++++++---------= ---- 1 file changed, 27 insertions(+), 15 deletions(-) diff --git a/drivers/cpufreq/mediatek-cpufreq-hw.c b/drivers/cpufreq/mediat= ek-cpufreq-hw.c index b2aba1842226c7d24a8b9599ea62408cac9f803c..53611077d0d9a2d9865cf771568= ab71abc0e6fbd 100644 --- a/drivers/cpufreq/mediatek-cpufreq-hw.c +++ b/drivers/cpufreq/mediatek-cpufreq-hw.c @@ -35,13 +35,17 @@ enum { REG_ARRAY_SIZE, }; =20 -struct mtk_cpufreq_data { +struct mtk_cpufreq_priv { + const struct mtk_cpufreq_variant *variant; +}; + +struct mtk_cpufreq_domain { + struct mtk_cpufreq_priv *parent; struct cpufreq_frequency_table *table; void __iomem *reg_bases[REG_ARRAY_SIZE]; struct resource *res; void __iomem *base; int nr_opp; - const struct mtk_cpufreq_variant *variant; }; =20 struct mtk_cpufreq_variant { @@ -63,7 +67,7 @@ static int __maybe_unused mtk_cpufreq_get_cpu_power(struct device *cpu_dev, unsigned long *uW, unsigned long *KHz) { - struct mtk_cpufreq_data *data; + struct mtk_cpufreq_domain *data; struct cpufreq_policy *policy; int i; =20 @@ -90,7 +94,7 @@ mtk_cpufreq_get_cpu_power(struct device *cpu_dev, unsigne= d long *uW, static int mtk_cpufreq_hw_target_index(struct cpufreq_policy *policy, unsigned int index) { - struct mtk_cpufreq_data *data =3D policy->driver_data; + struct mtk_cpufreq_domain *data =3D policy->driver_data; =20 writel_relaxed(index, data->reg_bases[REG_FREQ_PERF_STATE]); =20 @@ -99,7 +103,7 @@ static int mtk_cpufreq_hw_target_index(struct cpufreq_po= licy *policy, =20 static unsigned int mtk_cpufreq_hw_get(unsigned int cpu) { - struct mtk_cpufreq_data *data; + struct mtk_cpufreq_domain *data; struct cpufreq_policy *policy; unsigned int index; =20 @@ -118,7 +122,7 @@ static unsigned int mtk_cpufreq_hw_get(unsigned int cpu) static unsigned int mtk_cpufreq_hw_fast_switch(struct cpufreq_policy *poli= cy, unsigned int target_freq) { - struct mtk_cpufreq_data *data =3D policy->driver_data; + struct mtk_cpufreq_domain *data =3D policy->driver_data; unsigned int index; =20 index =3D cpufreq_table_find_index_dl(policy, target_freq, false); @@ -129,7 +133,7 @@ static unsigned int mtk_cpufreq_hw_fast_switch(struct c= pufreq_policy *policy, } =20 static int mtk_cpu_create_freq_table(struct platform_device *pdev, - struct mtk_cpufreq_data *data) + struct mtk_cpufreq_domain *data) { struct device *dev =3D &pdev->dev; u32 temp, i, freq, prev_freq =3D 0; @@ -164,9 +168,9 @@ static int mtk_cpu_create_freq_table(struct platform_de= vice *pdev, =20 static int mtk_cpu_resources_init(struct platform_device *pdev, struct cpufreq_policy *policy, - const struct mtk_cpufreq_variant *variant) + struct mtk_cpufreq_priv *priv) { - struct mtk_cpufreq_data *data; + struct mtk_cpufreq_domain *data; struct device *dev =3D &pdev->dev; struct resource *res; struct of_phandle_args args; @@ -187,6 +191,8 @@ static int mtk_cpu_resources_init(struct platform_devic= e *pdev, index =3D args.args[0]; of_node_put(args.np); =20 + data->parent =3D priv; + res =3D platform_get_resource(pdev, IORESOURCE_MEM, index); if (!res) { dev_err(dev, "failed to get mem resource %d\n", index); @@ -207,10 +213,9 @@ static int mtk_cpu_resources_init(struct platform_devi= ce *pdev, =20 data->base =3D base; data->res =3D res; - data->variant =3D variant; =20 for (i =3D REG_FREQ_LUT_TABLE; i < REG_ARRAY_SIZE; i++) - data->reg_bases[i] =3D base + variant->reg_offsets[i]; + data->reg_bases[i] =3D base + priv->variant->reg_offsets[i]; =20 ret =3D mtk_cpu_create_freq_table(pdev, data); if (ret) { @@ -231,7 +236,7 @@ static int mtk_cpufreq_hw_cpu_init(struct cpufreq_polic= y *policy) { struct platform_device *pdev =3D cpufreq_get_driver_data(); int sig, pwr_hw =3D CPUFREQ_HW_STATUS | SVS_HW_STATUS; - struct mtk_cpufreq_data *data; + struct mtk_cpufreq_domain *data; unsigned int latency; int ret; =20 @@ -270,7 +275,7 @@ static int mtk_cpufreq_hw_cpu_init(struct cpufreq_polic= y *policy) =20 static void mtk_cpufreq_hw_cpu_exit(struct cpufreq_policy *policy) { - struct mtk_cpufreq_data *data =3D policy->driver_data; + struct mtk_cpufreq_domain *data =3D policy->driver_data; struct resource *res =3D data->res; void __iomem *base =3D data->base; =20 @@ -283,7 +288,7 @@ static void mtk_cpufreq_hw_cpu_exit(struct cpufreq_poli= cy *policy) static void mtk_cpufreq_register_em(struct cpufreq_policy *policy) { struct em_data_callback em_cb =3D EM_DATA_CB(mtk_cpufreq_get_cpu_power); - struct mtk_cpufreq_data *data =3D policy->driver_data; + struct mtk_cpufreq_domain *data =3D policy->driver_data; =20 em_dev_register_perf_domain(get_cpu_device(policy->cpu), data->nr_opp, &em_cb, policy->cpus, true); @@ -305,6 +310,7 @@ static struct cpufreq_driver cpufreq_mtk_hw_driver =3D { =20 static int mtk_cpufreq_hw_driver_probe(struct platform_device *pdev) { + struct mtk_cpufreq_priv *priv; const void *data; int ret, cpu; struct device *cpu_dev; @@ -328,7 +334,13 @@ static int mtk_cpufreq_hw_driver_probe(struct platform= _device *pdev) if (!data) return -EINVAL; =20 - platform_set_drvdata(pdev, (void *) data); + priv =3D devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->variant =3D data; + + platform_set_drvdata(pdev, priv); cpufreq_mtk_hw_driver.driver_data =3D pdev; =20 ret =3D cpufreq_register_driver(&cpufreq_mtk_hw_driver); --=20 2.50.0 From nobody Tue Oct 7 08:32:09 2025 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 749602EAB9A; Fri, 11 Jul 2025 14:58:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.112 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752245901; cv=pass; b=dB6vNQRGPbZCxKMHZukeISF+mq3aszOut6AwQIYdPxMU5z7F2fwGTT4lI6fdgyZykfE2pWmC+mvqwBUgPVHjvtyDIqHMr4+je3aYnA6pP5HVL7CdQABGe1H9flstzNup+qxghMtyJmHPPyQQtoRNrPCSFzunTia3lqE0N4lv3v8= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752245901; c=relaxed/simple; bh=qMclNpzGYbS+Q7USxYi/UnTZUg7gHMhWOtWCzSJYThk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=F0jzjkO6JZrqNXHuuQ7qus8y3TvvhFmCPlMm2WVpne283B37surivhXt34fVWfdwbQtDBJfl0tjqcwKRTeb5MeoieDORPIv52C4fbLjH7ByvJdgVg9LdQoA7eos13kyYC33OdWYIXhNgToMIOhZtUvevlzORLW8DjkpaPKAN0es= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (1024-bit key) header.d=collabora.com header.i=nicolas.frattaroli@collabora.com header.b=SPa+zi99; arc=pass smtp.client-ip=136.143.188.112 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=collabora.com header.i=nicolas.frattaroli@collabora.com header.b="SPa+zi99" ARC-Seal: i=1; a=rsa-sha256; t=1752245883; cv=none; d=zohomail.com; s=zohoarc; b=BzoeaZuSu+JRG0pFQ+xUn68OpDDvKtH+YKqA8bMHOW2fgc4hsVwy1m88p/+EEKqAi3V5roE+vslzi6X4WFspVCBGsV7r+QmHLhcQLg+qcSc37+tMjspP3MbK71OqpPOOWyk62CBjj/zpmZRuw9qytAwa/70Qe3uQV+Bk9KOgj6k= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1752245883; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=jAwpf6q1OAFUYW1t8tkYML5f6zAM037csqTvRpDmGTU=; b=eSow1R8+JV1i64Kz3PoE3U92JXsMO059EIf0pVQg3TMoeTgj4P2x1QYro6Opk/U6XjJEWmBPVAlkOlA0kWlsG/oJHuIYbY6hGtPtblevVBYBgkPaSAclF4lt+y/bFmEOTMiFstibAAzS4eG5S9I0TfWmDKGWv3zJXxRTa87ayeo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=collabora.com; spf=pass smtp.mailfrom=nicolas.frattaroli@collabora.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1752245883; s=zohomail; d=collabora.com; i=nicolas.frattaroli@collabora.com; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=jAwpf6q1OAFUYW1t8tkYML5f6zAM037csqTvRpDmGTU=; b=SPa+zi99oU6Unbg+q6UO0emr1sdI2hzr3J/zNeRtH/p6jGavSlY6l1E0p3c0+tW4 miDMp3nda+WdXis4P+pGaxefrbH87abt//RaAZwWZP46m96QZV//Aj6DsxPsiMEWIRn YI9NVge+junQ/IYbsIZ4bCad8GBb2gUd4hwXJm6A= Received: by mx.zohomail.com with SMTPS id 175224588104259.94795638566734; Fri, 11 Jul 2025 07:58:01 -0700 (PDT) From: Nicolas Frattaroli Date: Fri, 11 Jul 2025 16:57:37 +0200 Subject: [PATCH 5/5] cpufreq: mediatek-hw: Add support for MT8196 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250711-mt8196-cpufreq-v1-5-e1b0a3b4ac61@collabora.com> References: <20250711-mt8196-cpufreq-v1-0-e1b0a3b4ac61@collabora.com> In-Reply-To: <20250711-mt8196-cpufreq-v1-0-e1b0a3b4ac61@collabora.com> To: Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , "Rafael J. Wysocki" , Viresh Kumar , Hector Yuan Cc: kernel@collabora.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-pm@vger.kernel.org, Nicolas Frattaroli X-Mailer: b4 0.14.2 The MT8196 SoC uses DVFS to set a desired target frequency for each CPU core. It also uses slightly different register offsets. Add support for it, which necessitates acquiring some syscons as regmaps to both check for the FDVFS magic number and to set target frequencies for FDVFS. I've verified with both `sysbench cpu run` and `head -c 10G \ /dev/urandom | pigz -p 8 -c - | pv -ba > /dev/null` that we don't just get a higher reported clock frequency, but that the observed performance also increases, by a factor of 2.64 in an 8 thread sysbench test. Signed-off-by: Nicolas Frattaroli --- drivers/cpufreq/mediatek-cpufreq-hw.c | 78 +++++++++++++++++++++++++++++++= +++- 1 file changed, 77 insertions(+), 1 deletion(-) diff --git a/drivers/cpufreq/mediatek-cpufreq-hw.c b/drivers/cpufreq/mediat= ek-cpufreq-hw.c index 53611077d0d9a2d9865cf771568ab71abc0e6fbd..30cf038babb6d02a0666ed39b92= 6f3977a164236 100644 --- a/drivers/cpufreq/mediatek-cpufreq-hw.c +++ b/drivers/cpufreq/mediatek-cpufreq-hw.c @@ -9,10 +9,12 @@ #include #include #include +#include #include #include #include #include +#include #include #include =20 @@ -24,6 +26,8 @@ #define POLL_USEC 1000 #define TIMEOUT_USEC 300000 =20 +#define MT8196_FDVFS_MAGIC 0xABCD0001UL + enum { REG_FREQ_LUT_TABLE, REG_FREQ_ENABLE, @@ -36,7 +40,10 @@ enum { }; =20 struct mtk_cpufreq_priv { + struct device *dev; const struct mtk_cpufreq_variant *variant; + struct regmap *fdvfs_config; + struct regmap *fdvfs; }; =20 struct mtk_cpufreq_domain { @@ -49,7 +56,9 @@ struct mtk_cpufreq_domain { }; =20 struct mtk_cpufreq_variant { + int (*init)(struct mtk_cpufreq_priv *priv); const u16 reg_offsets[REG_ARRAY_SIZE]; + const unsigned int fdvfs_fdiv; }; =20 static const struct mtk_cpufreq_variant cpufreq_mtk_base_variant =3D { @@ -63,6 +72,38 @@ static const struct mtk_cpufreq_variant cpufreq_mtk_base= _variant =3D { }, }; =20 +static int mtk_cpufreq_hw_mt8196_init(struct mtk_cpufreq_priv *priv) +{ + u32 val; + + priv->fdvfs_config =3D syscon_regmap_lookup_by_compatible("mediatek,mt819= 6-fdvfs-config"); + if (!priv->fdvfs_config) + return dev_err_probe(priv->dev, PTR_ERR(priv->fdvfs_config), + "failed to get fdvfs-config syscon\n"); + + if (!regmap_read(priv->fdvfs_config, 0x0, &val) && val =3D=3D MT8196_FDVF= S_MAGIC) { + priv->fdvfs =3D syscon_regmap_lookup_by_compatible("mediatek,mt8196-fdvf= s"); + if (!priv->fdvfs) + return dev_err_probe(priv->dev, PTR_ERR(priv->fdvfs), + "failed to get fdvfs syscon\n"); + } + + return 0; +} + +static const struct mtk_cpufreq_variant cpufreq_mtk_mt8196_variant =3D { + .init =3D mtk_cpufreq_hw_mt8196_init, + .reg_offsets =3D { + [REG_FREQ_LUT_TABLE] =3D 0x0, + [REG_FREQ_ENABLE] =3D 0x84, + [REG_FREQ_PERF_STATE] =3D 0x88, + [REG_FREQ_HW_STATE] =3D 0x8c, + [REG_EM_POWER_TBL] =3D 0x90, + [REG_FREQ_LATENCY] =3D 0x114, + }, + .fdvfs_fdiv =3D 26000, +}; + static int __maybe_unused mtk_cpufreq_get_cpu_power(struct device *cpu_dev, unsigned long *uW, unsigned long *KHz) @@ -91,10 +132,34 @@ mtk_cpufreq_get_cpu_power(struct device *cpu_dev, unsi= gned long *uW, return 0; } =20 +static int mtk_cpufreq_hw_fdvfs_switch(unsigned int target_freq, + struct cpufreq_policy *policy) +{ + struct mtk_cpufreq_domain *data =3D policy->driver_data; + struct mtk_cpufreq_priv *priv =3D data->parent; + unsigned int cpu; + int ret; + + target_freq =3D DIV_ROUND_UP(target_freq, priv->variant->fdvfs_fdiv); + for_each_cpu(cpu, policy->real_cpus) { + ret =3D regmap_write(priv->fdvfs, cpu * 4, target_freq); + if (ret) + return ret; + } + + return 0; +} + static int mtk_cpufreq_hw_target_index(struct cpufreq_policy *policy, unsigned int index) { struct mtk_cpufreq_domain *data =3D policy->driver_data; + unsigned int target_freq; + + if (data->parent->fdvfs) { + target_freq =3D policy->freq_table[index].frequency; + return mtk_cpufreq_hw_fdvfs_switch(target_freq, policy); + } =20 writel_relaxed(index, data->reg_bases[REG_FREQ_PERF_STATE]); =20 @@ -127,7 +192,10 @@ static unsigned int mtk_cpufreq_hw_fast_switch(struct = cpufreq_policy *policy, =20 index =3D cpufreq_table_find_index_dl(policy, target_freq, false); =20 - writel_relaxed(index, data->reg_bases[REG_FREQ_PERF_STATE]); + if (data->parent->fdvfs) + mtk_cpufreq_hw_fdvfs_switch(target_freq, policy); + else + writel_relaxed(index, data->reg_bases[REG_FREQ_PERF_STATE]); =20 return policy->freq_table[index].frequency; } @@ -339,6 +407,13 @@ static int mtk_cpufreq_hw_driver_probe(struct platform= _device *pdev) return -ENOMEM; =20 priv->variant =3D data; + priv->dev =3D &pdev->dev; + + if (priv->variant->init) { + ret =3D priv->variant->init(priv); + if (ret) + return ret; + } =20 platform_set_drvdata(pdev, priv); cpufreq_mtk_hw_driver.driver_data =3D pdev; @@ -357,6 +432,7 @@ static void mtk_cpufreq_hw_driver_remove(struct platfor= m_device *pdev) =20 static const struct of_device_id mtk_cpufreq_hw_match[] =3D { { .compatible =3D "mediatek,cpufreq-hw", .data =3D &cpufreq_mtk_base_vari= ant }, + { .compatible =3D "mediatek,mt8196-cpufreq-hw", .data =3D &cpufreq_mtk_mt= 8196_variant }, {} }; MODULE_DEVICE_TABLE(of, mtk_cpufreq_hw_match); --=20 2.50.0