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[188.141.3.146]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3b5e8dc1f70sm4373648f8f.27.2025.07.11.05.58.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Jul 2025 05:58:09 -0700 (PDT) From: Bryan O'Donoghue Date: Fri, 11 Jul 2025 13:58:00 +0100 Subject: [PATCH v7 08/15] arm64: dts: qcom: x1e80100: Add MIPI CSI PHY nodes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250711-b4-linux-next-25-03-13-dtsi-x1e80100-camss-v7-8-0bc5da82f526@linaro.org> References: <20250711-b4-linux-next-25-03-13-dtsi-x1e80100-camss-v7-0-0bc5da82f526@linaro.org> In-Reply-To: <20250711-b4-linux-next-25-03-13-dtsi-x1e80100-camss-v7-0-0bc5da82f526@linaro.org> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Robert Foss , Todor Tomov , Mauro Carvalho Chehab , Konrad Dybcio , Vladimir Zapolskiy Cc: Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, Bryan O'Donoghue X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3307; i=bryan.odonoghue@linaro.org; h=from:subject:message-id; bh=Sk+XLN+fch0oWoINUVwniKgPhQoXp0xYBRIRNEdHrJU=; b=owEBbQKS/ZANAwAIASJxO7Ohjcg6AcsmYgBocQpTQnI8GFdMlYF+BdvI6MSWYnrPVcz1ZMzNp nn8o0Apj3uJAjMEAAEIAB0WIQTmk/sqq6Nt4Rerb7QicTuzoY3IOgUCaHEKUwAKCRAicTuzoY3I OqkyD/9cc5wBQgDeWieg156Wstei4KLNf4HtxNYf4TCZpkSaLTeXIa1o5ph6q+DoXlW8GtjO4fN TXzq7am0Ia+TI3rNVY+rJ6fESUFEr9v0SguWhS4rSOYJ7P1RM2OVZ4ylAtmcqloOG2jqIwCWne4 a3I9lOaWwhHNBO+E+HBB6lvw6HO9dkcFiPTBdX6gcfaMg0Md+tmAHdlQDv3Tl0roJdCrH3IOcws ulnVsm2x97Mo2CMI9T4CgVXT/ItpsDssz8wtei+UzjRiCufz+dM2aHYpBdncxfQzc6li4v8f/7J wGxtrSVAOCO8AeMLwzP7ytJ1SeXLm8btVLhpT6Z549FkvjCHkDnHCl8P4uKMgmC0wDLFJmkmKbr 3aIXBJIASWxxqov++QPyvLRLrqKaHIOvejrTXBkqqQ/1guTQ9IA7gQ/rD2W/Qv2DFa7aloGTD+F Tbob1qtO6C6dPGDmoSvdfKtUTWmVKGuZ+Oqp/7Kr+OPS9wRHyYKgD002ZzGkouEHJO+ZrjARi29 HMOzm2WNDImoY375zg4vfQn0vvvCVfgd5bH3twqsb5MUz/wZO5fUSo5DRzm8KV1SjDkVce7cvvc Y9uRf9BTvr6NvPgytVHgCTxVAr1yQUn19DgoTYVrGhCdpC+LU+KcgRiPNakH8Tv9JOILVnTCnhX SqkB8oXNcutBwcA== X-Developer-Key: i=bryan.odonoghue@linaro.org; a=openpgp; fpr=E693FB2AABA36DE117AB6FB422713BB3A18DC83A Add csiphy nodes for - csiphy0 - csiphy1 - csiphy2 - csiphy4 The irregular naming of the PHYs comes directly from the hardware which for whatever reason skipped csiphy3. Separating the nodes from CAMSS as we have done with the sensor I2C bus aka the CCI interface is justified since the CSIPHYs have their own pinouts and voltage rails. Signed-off-by: Bryan O'Donoghue --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 88 ++++++++++++++++++++++++++++++= ++++ 1 file changed, 88 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/q= com/x1e80100.dtsi index 41245e8592f78edf141141f2f5b7c5b841318f46..e385d6f329616360e089ba352be= 450c9eca6aab6 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -5244,6 +5244,94 @@ cci1_i2c1: i2c-bus@1 { }; }; =20 + csiphy0: csiphy@ace4000 { + compatible =3D "qcom,x1e80100-mipi-csi2-combo-phy"; + reg =3D <0 0x0ace4000 0 0x2000>; + + clocks =3D <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>; + clock-names =3D "camnoc_axi", + "cpas_ahb", + "csiphy", + "csiphy_timer"; + + interrupts =3D ; + + power-domains =3D <&camcc CAM_CC_TITAN_TOP_GDSC>; + + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + + csiphy1: csiphy@ace6000 { + compatible =3D "qcom,x1e80100-mipi-csi2-combo-phy"; + reg =3D <0 0x0ace6000 0 0x2000>; + + clocks =3D <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CSIPHY1_CLK>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK>; + clock-names =3D "camnoc_axi", + "cpas_ahb", + "csiphy", + "csiphy_timer"; + + interrupts =3D ; + + power-domains =3D <&camcc CAM_CC_TITAN_TOP_GDSC>; + + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + + csiphy2: csiphy@ace8000 { + compatible =3D "qcom,x1e80100-mipi-csi2-combo-phy"; + reg =3D <0 0x0ace8000 0 0x2000>; + + clocks =3D <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CSIPHY2_CLK>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK>; + clock-names =3D "camnoc_axi", + "cpas_ahb", + "csiphy", + "csiphy_timer"; + + interrupts =3D ; + + power-domains =3D <&camcc CAM_CC_TITAN_TOP_GDSC>; + + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + + csiphy4: csiphy@acec000 { + compatible =3D "qcom,x1e80100-mipi-csi2-combo-phy"; + reg =3D <0 0x0acec000 0 0x2000>; + + clocks =3D <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CSIPHY4_CLK>, + <&camcc CAM_CC_CSI4PHYTIMER_CLK>; + clock-names =3D "camnoc_axi", + "cpas_ahb", + "csiphy", + "csiphy_timer"; + + interrupts =3D ; + + power-domains =3D <&camcc CAM_CC_TITAN_TOP_GDSC>; + + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + camcc: clock-controller@ade0000 { compatible =3D "qcom,x1e80100-camcc"; reg =3D <0 0x0ade0000 0 0x20000>; --=20 2.49.0