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[188.141.3.146]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3b5e8dc1f70sm4373648f8f.27.2025.07.11.05.58.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Jul 2025 05:58:01 -0700 (PDT) From: Bryan O'Donoghue Date: Fri, 11 Jul 2025 13:57:54 +0100 Subject: [PATCH v7 02/15] dt-bindings: media: qcom,x1e80100-camss: Convert from inline PHY definitions to PHY handles Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250711-b4-linux-next-25-03-13-dtsi-x1e80100-camss-v7-2-0bc5da82f526@linaro.org> References: <20250711-b4-linux-next-25-03-13-dtsi-x1e80100-camss-v7-0-0bc5da82f526@linaro.org> In-Reply-To: <20250711-b4-linux-next-25-03-13-dtsi-x1e80100-camss-v7-0-0bc5da82f526@linaro.org> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Robert Foss , Todor Tomov , Mauro Carvalho Chehab , Konrad Dybcio , Vladimir Zapolskiy Cc: Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, Bryan O'Donoghue X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=8032; i=bryan.odonoghue@linaro.org; h=from:subject:message-id; bh=5gV/Pwg1WP+ZZILJzt3fi0xEnri4ukNILoHO+6sJ6I4=; b=owEBbQKS/ZANAwAIASJxO7Ohjcg6AcsmYgBocQpSlGQ68k1c1n3/pDUm2g4dycogVyIVjOB6y 1NLaf0nYJ+JAjMEAAEIAB0WIQTmk/sqq6Nt4Rerb7QicTuzoY3IOgUCaHEKUgAKCRAicTuzoY3I Om82EACBuKGAY/JgbJMmDmVaH2Rh8pL8YMvj9ofNzHmskTZtDg689vihLFJd0La1Jue4cufIwbJ ANlYFJSFB4faOegzSJx903gPuxv9i4FeC/NcpgN9b0u7OL/n8r4N7XOkXfjtzp4R48CoR6UoBUL UoxgGSbYQ/6MjAixE/oHDa4eLtc8kr3smvviYE0O7PXcbfwbpyy7qmQc8bcqFJdqB83yqwUi3Wx HCSpOmrOQFTlalutJbSdIHroTvH344929cMXtxv8F4MgOoh5zUL+reKft8PI049vpviCYE0iUe2 AXGm6+2QmvTankttf106TgXTsxlp//iRg5m1S/tnPD8f7CvxQkGWgpbwbQ3S6sANZHHgFOpSBNo COcp6l52FkLBX/uN5e0BoVjIn1GGBxHTlKfR9vdsjjb0PSmi30vDtBzkHKH5E2tUPvxytqi/9Se +Y/iLF2wxYy4zSexSvLaV8H27w/zTXqDbBobmdwbJ1qEqrEqXO8BzdcqmTSxS/3QInbyJpkfN3a CBSOgEP54Xw16hKHQ2RcNQ9b2R9jSHZY0WVvwDNu4fSfZ3bZOXKb3VESMVwPFirkvEgxunzXApq 3f4Z7Jxpk6kXsdlVKtRHiZjDH2NSYMFg0lwWoRvGC4FkSOy6TtAF5VkL1JPqin3g81UcWtosFLN G6IS7HvHR36DIHw== X-Developer-Key: i=bryan.odonoghue@linaro.org; a=openpgp; fpr=E693FB2AABA36DE117AB6FB422713BB3A18DC83A We currently do not have an upstream user of the x1e CAMSS schema which allows us to make this the first platform to treat the CSI PHYs as separate devices in much the same way as we treat the CCI block as separate devices. Convert the embedded CSIPHY node data to simple phys =3D <> removing all of the PHY specific stuff previously embedded. I gave some serious thought to making the Test Pattern Generators TPGs into PHY nodes also but, unlike the CSIPHYs the TPGs have no dedicated external pins nor regulators. The CSIPHYs OTOH have dedicated in-fact generally unmuxed pins on Qualcomm SoCs and each CSIPHY has its own set of input power rails usually 0p8 and 1p2. Instead of defining the CSIPHYs as children of the CAMSS block, we take the same approach as the CCI/I2C bus dedicated to CAMSS and define the CSIPHYs as their own nodes. Remove the embedded CSIPHY specific data and give CAMSS regular, bog-standard phys =3D <>; Signed-off-by: Bryan O'Donoghue --- .../bindings/media/qcom,x1e80100-camss.yaml | 80 +++++-------------= ---- 1 file changed, 16 insertions(+), 64 deletions(-) diff --git a/Documentation/devicetree/bindings/media/qcom,x1e80100-camss.ya= ml b/Documentation/devicetree/bindings/media/qcom,x1e80100-camss.yaml index 2438e08b894f4a3dc577cee4ab85184a3d7232b0..c130733887e39afe51f3d2df2a5= c943c6fc2ca9f 100644 --- a/Documentation/devicetree/bindings/media/qcom,x1e80100-camss.yaml +++ b/Documentation/devicetree/bindings/media/qcom,x1e80100-camss.yaml @@ -17,7 +17,7 @@ properties: const: qcom,x1e80100-camss =20 reg: - maxItems: 17 + maxItems: 13 =20 reg-names: items: @@ -27,10 +27,6 @@ properties: - const: csid2 - const: csid_lite0 - const: csid_lite1 - - const: csiphy0 - - const: csiphy1 - - const: csiphy2 - - const: csiphy4 - const: csitpg0 - const: csitpg1 - const: csitpg2 @@ -40,7 +36,7 @@ properties: - const: vfe_lite1 =20 clocks: - maxItems: 29 + maxItems: 21 =20 clock-names: items: @@ -55,14 +51,6 @@ properties: - const: cphy_rx_clk_src - const: csid - const: csid_csiphy_rx - - const: csiphy0 - - const: csiphy0_timer - - const: csiphy1 - - const: csiphy1_timer - - const: csiphy2 - - const: csiphy2_timer - - const: csiphy4 - - const: csiphy4_timer - const: gcc_axi_hf - const: gcc_axi_sf - const: vfe0 @@ -75,7 +63,7 @@ properties: - const: vfe_lite_csid =20 interrupts: - maxItems: 13 + maxItems: 9 =20 interrupt-names: items: @@ -84,15 +72,17 @@ properties: - const: csid2 - const: csid_lite0 - const: csid_lite1 - - const: csiphy0 - - const: csiphy1 - - const: csiphy2 - - const: csiphy4 - const: vfe0 - const: vfe1 - const: vfe_lite0 - const: vfe_lite1 =20 + phys: + maxItems: 4 + + phy-names: + maxItems: 4 + interconnects: maxItems: 4 =20 @@ -118,14 +108,6 @@ properties: - const: ife1 - const: top =20 - vdd-csiphy-0p8-supply: - description: - Phandle to a 0.8V regulator supply to a PHY. - - vdd-csiphy-1p2-supply: - description: - Phandle to 1.8V regulator supply to a PHY. - ports: $ref: /schemas/graph.yaml#/properties/ports =20 @@ -166,13 +148,13 @@ required: - clock-names - interrupts - interrupt-names + - phys + - phy-names - interconnects - interconnect-names - iommus - power-domains - power-domain-names - - vdd-csiphy-0p8-supply - - vdd-csiphy-1p2-supply - ports =20 additionalProperties: false @@ -199,10 +181,6 @@ examples: <0 0x0acbb000 0 0x2000>, <0 0x0acc6000 0 0x1000>, <0 0x0acca000 0 0x1000>, - <0 0x0ace4000 0 0x1000>, - <0 0x0ace6000 0 0x1000>, - <0 0x0ace8000 0 0x1000>, - <0 0x0acec000 0 0x4000>, <0 0x0acf6000 0 0x1000>, <0 0x0acf7000 0 0x1000>, <0 0x0acf8000 0 0x1000>, @@ -217,10 +195,6 @@ examples: "csid2", "csid_lite0", "csid_lite1", - "csiphy0", - "csiphy1", - "csiphy2", - "csiphy4", "csitpg0", "csitpg1", "csitpg2", @@ -240,14 +214,6 @@ examples: <&camcc CAM_CC_CPHY_RX_CLK_SRC>, <&camcc CAM_CC_CSID_CLK>, <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>, - <&camcc CAM_CC_CSIPHY0_CLK>, - <&camcc CAM_CC_CSI0PHYTIMER_CLK>, - <&camcc CAM_CC_CSIPHY1_CLK>, - <&camcc CAM_CC_CSI1PHYTIMER_CLK>, - <&camcc CAM_CC_CSIPHY2_CLK>, - <&camcc CAM_CC_CSI2PHYTIMER_CLK>, - <&camcc CAM_CC_CSIPHY4_CLK>, - <&camcc CAM_CC_CSI4PHYTIMER_CLK>, <&gcc GCC_CAMERA_HF_AXI_CLK>, <&gcc GCC_CAMERA_SF_AXI_CLK>, <&camcc CAM_CC_IFE_0_CLK>, @@ -270,14 +236,6 @@ examples: "cphy_rx_clk_src", "csid", "csid_csiphy_rx", - "csiphy0", - "csiphy0_timer", - "csiphy1", - "csiphy1_timer", - "csiphy2", - "csiphy2_timer", - "csiphy4", - "csiphy4_timer", "gcc_axi_hf", "gcc_axi_sf", "vfe0", @@ -294,10 +252,6 @@ examples: , , , - , - , - , - , , , , @@ -308,15 +262,16 @@ examples: "csid2", "csid_lite0", "csid_lite1", - "csiphy0", - "csiphy1", - "csiphy2", - "csiphy4", "vfe0", "vfe1", "vfe_lite0", "vfe_lite1"; =20 + phys =3D <&csiphy0>, <&csiphy1>, + <&csiphy2>, <&csiphy4>; + phy-names =3D "csiphy0", "csiphy1", + "csiphy2", "csiphy4"; + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACT= IVE_ONLY &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACT= IVE_ONLY>, <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS @@ -348,9 +303,6 @@ examples: "ife1", "top"; =20 - vdd-csiphy-0p8-supply =3D <&csiphy_0p8_supply>; - vdd-csiphy-1p2-supply =3D <&csiphy_1p2_supply>; - ports { #address-cells =3D <1>; #size-cells =3D <0>; --=20 2.49.0