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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-23de4341d51sm30479615ad.189.2025.07.10.15.46.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Jul 2025 15:46:01 -0700 (PDT) From: Anjelique Melendez To: amitk@kernel.org, thara.gopinath@gmail.com, rafael@kernel.org, daniel.lezcano@linaro.org Cc: rui.zhang@intel.com, lukasz.luba@arm.com, david.collins@oss.qualcomm.com, stefan.schmidt@linaro.org, quic_tsoni@quicinc.com, konrad.dybcio@oss.qualcomm.com, linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dmitry.baryshkov@linaro.org, dmitry.baryshkov@oss.qualcomm.com Subject: [PATCH v6 4/5] thermal: qcom-spmi-temp-alarm: add support for GEN2 rev 2 PMIC peripherals Date: Thu, 10 Jul 2025 15:45:54 -0700 Message-Id: <20250710224555.3047790-5-anjelique.melendez@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250710224555.3047790-1-anjelique.melendez@oss.qualcomm.com> References: <20250710224555.3047790-1-anjelique.melendez@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=GdQXnRXL c=1 sm=1 tr=0 ts=687042ac cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=Wb1JkmetP80A:10 a=EUspDBNiAAAA:8 a=N9IR0GguogMVy2wE49AA:9 a=uG9DUKGECoFWVXl0Dc02:22 X-Proofpoint-GUID: BbT0_QTnf5-vjTXoamp-NDr6oEngyQch X-Proofpoint-ORIG-GUID: BbT0_QTnf5-vjTXoamp-NDr6oEngyQch X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzEwMDE5MSBTYWx0ZWRfX5iagU03w1KFh nU/k3r9zadsKIqDtxe4m4x7vCT0yIp7JZN1w2vOLX3xNawmmMl/PHTJdz37HR3ROCEjVuAF+Iwj YjvLeU5l5lWMjhEC1jGosJQexUEoL5QdPR+xlUedOQqOmPK56PB4pPGMBr10FY6GNp86r9V3G76 T01ntfkKDpk3QBDWxnocj5XnBASEImo+SWCTeeoPpnbcTJwL2JuwfAulEsXGxHtJJoNtd6I+kks uPE6J2HRvFkucptve+G/SJJ9i+l3OBomE6uKQZ+aIXE7lsgL1mN8ygrFAe0xUo9NeQVAkcQ23r3 ZftpqU1F/9M32oO+JFN0CfP2muzy01qFoFDZ53uCDl39uGGO7aceTaIP0dY7zxbNAzn7dn9P/gH 1hKd2omCQiznWOdfHupAIu4RHCPKJq4YEyoelOatWKzsD1WOWcowGx9/n5ckG/mbWbIrkvHA X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.7,FMLib:17.12.80.40 definitions=2025-07-10_05,2025-07-09_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 phishscore=0 adultscore=0 bulkscore=0 clxscore=1015 spamscore=0 suspectscore=0 mlxlogscore=999 priorityscore=1501 impostorscore=0 malwarescore=0 mlxscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507100191 Content-Type: text/plain; charset="utf-8" Add support for TEMP_ALARM GEN2 PMIC peripherals with digital major revision 2. This revision utilizes individual temp DAC registers to set the threshold temperature for over-temperature stages 1 (warning), 2 (system shutdown), and 3 (emergency shutdown) instead of a single register to specify a set of thresholds. Co-developed-by: David Collins Signed-off-by: David Collins Signed-off-by: Anjelique Melendez --- drivers/thermal/qcom/qcom-spmi-temp-alarm.c | 138 +++++++++++++++++++- 1 file changed, 137 insertions(+), 1 deletion(-) diff --git a/drivers/thermal/qcom/qcom-spmi-temp-alarm.c b/drivers/thermal/= qcom/qcom-spmi-temp-alarm.c index c8e4db585d2b..9fbfd192017d 100644 --- a/drivers/thermal/qcom/qcom-spmi-temp-alarm.c +++ b/drivers/thermal/qcom/qcom-spmi-temp-alarm.c @@ -26,6 +26,11 @@ #define QPNP_TM_REG_SHUTDOWN_CTRL1 0x40 #define QPNP_TM_REG_ALARM_CTRL 0x46 =20 +/* TEMP_DAC_STGx registers are only present for TEMP_GEN2 v2.0 */ +#define QPNP_TM_REG_TEMP_DAC_STG1 0x47 +#define QPNP_TM_REG_TEMP_DAC_STG2 0x48 +#define QPNP_TM_REG_TEMP_DAC_STG3 0x49 + #define QPNP_TM_TYPE 0x09 #define QPNP_TM_SUBTYPE_GEN1 0x08 #define QPNP_TM_SUBTYPE_GEN2 0x09 @@ -71,6 +76,25 @@ static const long temp_map_gen2_v1[THRESH_COUNT][STAGE_C= OUNT] =3D { =20 #define TEMP_STAGE_HYSTERESIS 2000 =20 +/* + * For TEMP_GEN2 v2.0, TEMP_DAC_STG1/2/3 registers are used to set the thr= eshold + * for each stage independently. + * TEMP_DAC_STG* =3D 0 --> 80 C + * Each 8 step increase in TEMP_DAC_STG* value corresponds to 5 C (5000 mC= ). + */ +#define TEMP_DAC_MIN 80000 +#define TEMP_DAC_SCALE_NUM 8 +#define TEMP_DAC_SCALE_DEN 5000 + +#define TEMP_DAC_TEMP_TO_REG(temp) \ + (((temp) - TEMP_DAC_MIN) * TEMP_DAC_SCALE_NUM / TEMP_DAC_SCALE_DEN) +#define TEMP_DAC_REG_TO_TEMP(reg) \ + (TEMP_DAC_MIN + (reg) * TEMP_DAC_SCALE_DEN / TEMP_DAC_SCALE_NUM) + +static const long temp_dac_max[STAGE_COUNT] =3D { + 119375, 159375, 159375 +}; + /* Temperature in Milli Celsius reported during stage 0 if no ADC is prese= nt */ #define DEFAULT_TEMP 37000 =20 @@ -93,6 +117,7 @@ struct qpnp_tm_chip { long temp; unsigned int stage; unsigned int base; + unsigned int ntrips; /* protects .thresh, .stage and chip registers */ struct mutex lock; bool initialized; @@ -310,6 +335,54 @@ static const struct thermal_zone_device_ops qpnp_tm_se= nsor_ops =3D { .set_trip_temp =3D qpnp_tm_set_trip_temp, }; =20 +static int qpnp_tm_gen2_rev2_set_temp_thresh(struct qpnp_tm_chip *chip, un= signed int trip, int temp) +{ + int ret, temp_cfg; + u8 reg; + + WARN_ON(!mutex_is_locked(&chip->lock)); + + if (trip >=3D STAGE_COUNT) { + dev_err(chip->dev, "invalid TEMP_DAC trip =3D %d\n", trip); + return -EINVAL; + } else if (temp < TEMP_DAC_MIN || temp > temp_dac_max[trip]) { + dev_err(chip->dev, "invalid TEMP_DAC temp =3D %d\n", temp); + return -EINVAL; + } + + reg =3D TEMP_DAC_TEMP_TO_REG(temp); + temp_cfg =3D TEMP_DAC_REG_TO_TEMP(reg); + + ret =3D qpnp_tm_write(chip, QPNP_TM_REG_TEMP_DAC_STG1 + trip, reg); + if (ret < 0) { + dev_err(chip->dev, "TEMP_DAC_STG write failed, ret=3D%d\n", ret); + return ret; + } + + chip->temp_thresh_map[trip] =3D temp_cfg; + + return 0; +} + +static int qpnp_tm_gen2_rev2_set_trip_temp(struct thermal_zone_device *tz, + const struct thermal_trip *trip, int temp) +{ + unsigned int trip_index =3D THERMAL_TRIP_PRIV_TO_INT(trip->priv); + struct qpnp_tm_chip *chip =3D thermal_zone_device_priv(tz); + int ret; + + mutex_lock(&chip->lock); + ret =3D qpnp_tm_gen2_rev2_set_temp_thresh(chip, trip_index, temp); + mutex_unlock(&chip->lock); + + return ret; +} + +static const struct thermal_zone_device_ops qpnp_tm_gen2_rev2_sensor_ops = =3D { + .get_temp =3D qpnp_tm_get_temp, + .set_trip_temp =3D qpnp_tm_gen2_rev2_set_trip_temp, +}; + static irqreturn_t qpnp_tm_isr(int irq, void *data) { struct qpnp_tm_chip *chip =3D data; @@ -351,6 +424,60 @@ static int qpnp_tm_configure_trip_temp(struct qpnp_tm_= chip *chip) return ret; } =20 +/* Configure TEMP_DAC registers based on DT thermal_zone trips */ +static int qpnp_tm_gen2_rev2_configure_trip_temps_cb(struct thermal_trip *= trip, void *data) +{ + struct qpnp_tm_chip *chip =3D data; + int ret; + + mutex_lock(&chip->lock); + trip->priv =3D THERMAL_INT_TO_TRIP_PRIV(chip->ntrips); + ret =3D qpnp_tm_gen2_rev2_set_temp_thresh(chip, chip->ntrips, trip->tempe= rature); + chip->ntrips++; + mutex_unlock(&chip->lock); + + return ret; +} + +static int qpnp_tm_gen2_rev2_configure_trip_temps(struct qpnp_tm_chip *chi= p) +{ + int ret, i; + + ret =3D thermal_zone_for_each_trip(chip->tz_dev, + qpnp_tm_gen2_rev2_configure_trip_temps_cb, chip); + if (ret < 0) + return ret; + + /* Verify that trips are strictly increasing. */ + for (i =3D 1; i < STAGE_COUNT; i++) { + if (chip->temp_thresh_map[i] <=3D chip->temp_thresh_map[i - 1]) { + dev_err(chip->dev, "Threshold %d=3D%ld <=3D threshold %d=3D%ld\n", + i, chip->temp_thresh_map[i], i - 1, + chip->temp_thresh_map[i - 1]); + return -EINVAL; + } + } + + return 0; +} + +/* Read the hardware default TEMP_DAC stage threshold temperatures */ +static int qpnp_tm_gen2_rev2_sync_thresholds(struct qpnp_tm_chip *chip) +{ + int ret, i; + u8 reg =3D 0; + + for (i =3D 0; i < STAGE_COUNT; i++) { + ret =3D qpnp_tm_read(chip, QPNP_TM_REG_TEMP_DAC_STG1 + i, ®); + if (ret < 0) + return ret; + + chip->temp_thresh_map[i] =3D TEMP_DAC_REG_TO_TEMP(reg); + } + + return 0; +} + static const struct spmi_temp_alarm_data spmi_temp_alarm_data =3D { .ops =3D &qpnp_tm_sensor_ops, .temp_map =3D &temp_map_gen1, @@ -375,6 +502,13 @@ static const struct spmi_temp_alarm_data spmi_temp_ala= rm_gen2_rev1_data =3D { .get_temp_stage =3D qpnp_tm_gen2_get_temp_stage, }; =20 +static const struct spmi_temp_alarm_data spmi_temp_alarm_gen2_rev2_data = =3D { + .ops =3D &qpnp_tm_gen2_rev2_sensor_ops, + .sync_thresholds =3D qpnp_tm_gen2_rev2_sync_thresholds, + .configure_trip_temps =3D qpnp_tm_gen2_rev2_configure_trip_temps, + .get_temp_stage =3D qpnp_tm_gen2_get_temp_stage, +}; + /* * This function initializes the internal temp value based on only the * current thermal stage and threshold. @@ -491,8 +625,10 @@ static int qpnp_tm_probe(struct platform_device *pdev) chip->data =3D &spmi_temp_alarm_data; else if (subtype =3D=3D QPNP_TM_SUBTYPE_GEN2 && dig_major =3D=3D 0) chip->data =3D &spmi_temp_alarm_gen2_data; - else if (subtype =3D=3D QPNP_TM_SUBTYPE_GEN2 && dig_major >=3D 1) + else if (subtype =3D=3D QPNP_TM_SUBTYPE_GEN2 && dig_major =3D=3D 1) chip->data =3D &spmi_temp_alarm_gen2_rev1_data; + else if (subtype =3D=3D QPNP_TM_SUBTYPE_GEN2 && dig_major >=3D 2) + chip->data =3D &spmi_temp_alarm_gen2_rev2_data; else return -ENODEV; =20 --=20 2.34.1