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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-23de4341d51sm30479615ad.189.2025.07.10.15.45.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Jul 2025 15:46:00 -0700 (PDT) From: Anjelique Melendez To: amitk@kernel.org, thara.gopinath@gmail.com, rafael@kernel.org, daniel.lezcano@linaro.org Cc: rui.zhang@intel.com, lukasz.luba@arm.com, david.collins@oss.qualcomm.com, stefan.schmidt@linaro.org, quic_tsoni@quicinc.com, konrad.dybcio@oss.qualcomm.com, linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dmitry.baryshkov@linaro.org, dmitry.baryshkov@oss.qualcomm.com Subject: [PATCH v6 3/5] thermal: qcom-spmi-temp-alarm: Prepare to support additional Temp Alarm subtypes Date: Thu, 10 Jul 2025 15:45:53 -0700 Message-Id: <20250710224555.3047790-4-anjelique.melendez@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250710224555.3047790-1-anjelique.melendez@oss.qualcomm.com> References: <20250710224555.3047790-1-anjelique.melendez@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=dYuA3WXe c=1 sm=1 tr=0 ts=687042aa cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=Wb1JkmetP80A:10 a=EUspDBNiAAAA:8 a=EDJ0a-WMmjN7NLPDzUkA:9 a=1OuFwYUASf3TG4hYMiVC:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzEwMDE5MSBTYWx0ZWRfX6xnbzCc3qubA 8C6irDRIn1TxqbSEC9uncEl1kGl+bmkKJE/obof2bro1lsx3RuiYqDfcUonxmzVuTED2xqtHSvC 5MAk8Dg8Hu+IeP79iNqPNpmLWZtu4VKvxlK/CV+wKKGnKF/FgQp4Eh8qpTowzcjPHZbXEW/PSZf H5cfDmrVnQWbvNfphikjFxgrNE6eVZIcc3TPSZ0qmBkdZkQ9Gpm5xrKRSc+EOLmsYlj5JprvWQw qcAckLoieMbizInWCWeeK/6o0CXGNso6Mq0qUsmsfV540zhNqasMBTmK6C1XAIfOI+dK7QwCWMO YP7grqzEbnyd8YvMlrCV819g0ci55oiLOuKKgp1qkSSPUi+cLYOkjx2XBb0zgsXIE+zFs5OIUpX r59edhynLlFR8jDoYx6HTqwUWQGKNXdlwtSiG16KoLYUa6ZopmLUt+BK3n+S7esGfTyXxlhL X-Proofpoint-GUID: PkcYwzzLDeftFq391nzBck8z6WhMoY_G X-Proofpoint-ORIG-GUID: PkcYwzzLDeftFq391nzBck8z6WhMoY_G X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.7,FMLib:17.12.80.40 definitions=2025-07-10_05,2025-07-09_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 suspectscore=0 clxscore=1015 impostorscore=0 lowpriorityscore=0 priorityscore=1501 spamscore=0 adultscore=0 mlxlogscore=999 malwarescore=0 mlxscore=0 bulkscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507100191 Content-Type: text/plain; charset="utf-8" In preparation to support newer temp alarm subtypes, add the "ops", "sync_thresholds" and "configure_trip_temps" references to spmi_temp_alarm_data. This will allow for each Temp Alarm subtype to define its own thermal_zone_device_ops and properly initialize and configure thermal trip temperature. Signed-off-by: Anjelique Melendez Acked-by: Konrad Dybcio --- drivers/thermal/qcom/qcom-spmi-temp-alarm.c | 92 ++++++++++++++------- 1 file changed, 64 insertions(+), 28 deletions(-) diff --git a/drivers/thermal/qcom/qcom-spmi-temp-alarm.c b/drivers/thermal/= qcom/qcom-spmi-temp-alarm.c index 607838162c7d..c8e4db585d2b 100644 --- a/drivers/thermal/qcom/qcom-spmi-temp-alarm.c +++ b/drivers/thermal/qcom/qcom-spmi-temp-alarm.c @@ -77,8 +77,11 @@ static const long temp_map_gen2_v1[THRESH_COUNT][STAGE_C= OUNT] =3D { struct qpnp_tm_chip; =20 struct spmi_temp_alarm_data { + const struct thermal_zone_device_ops *ops; const long (*temp_map)[THRESH_COUNT][STAGE_COUNT]; + int (*sync_thresholds)(struct qpnp_tm_chip *chip); int (*get_temp_stage)(struct qpnp_tm_chip *chip); + int (*configure_trip_temps)(struct qpnp_tm_chip *chip); }; =20 struct qpnp_tm_chip { @@ -316,64 +319,95 @@ static irqreturn_t qpnp_tm_isr(int irq, void *data) return IRQ_HANDLED; } =20 +/* Read the hardware default stage threshold temperatures */ +static int qpnp_tm_sync_thresholds(struct qpnp_tm_chip *chip) +{ + u8 reg, threshold; + int ret; + + ret =3D qpnp_tm_read(chip, QPNP_TM_REG_SHUTDOWN_CTRL1, ®); + if (ret < 0) + return ret; + + threshold =3D reg & SHUTDOWN_CTRL1_THRESHOLD_MASK; + memcpy(chip->temp_thresh_map, chip->data->temp_map[threshold], + sizeof(chip->temp_thresh_map)); + + return ret; +} + +static int qpnp_tm_configure_trip_temp(struct qpnp_tm_chip *chip) +{ + int crit_temp, ret; + + ret =3D thermal_zone_get_crit_temp(chip->tz_dev, &crit_temp); + if (ret) + crit_temp =3D THERMAL_TEMP_INVALID; + + mutex_lock(&chip->lock); + ret =3D qpnp_tm_update_critical_trip_temp(chip, crit_temp); + mutex_unlock(&chip->lock); + + return ret; +} + static const struct spmi_temp_alarm_data spmi_temp_alarm_data =3D { + .ops =3D &qpnp_tm_sensor_ops, .temp_map =3D &temp_map_gen1, + .sync_thresholds =3D qpnp_tm_sync_thresholds, + .configure_trip_temps =3D qpnp_tm_configure_trip_temp, .get_temp_stage =3D qpnp_tm_gen1_get_temp_stage, }; =20 static const struct spmi_temp_alarm_data spmi_temp_alarm_gen2_data =3D { + .ops =3D &qpnp_tm_sensor_ops, .temp_map =3D &temp_map_gen1, + .sync_thresholds =3D qpnp_tm_sync_thresholds, + .configure_trip_temps =3D qpnp_tm_configure_trip_temp, .get_temp_stage =3D qpnp_tm_gen2_get_temp_stage, }; =20 static const struct spmi_temp_alarm_data spmi_temp_alarm_gen2_rev1_data = =3D { + .ops =3D &qpnp_tm_sensor_ops, .temp_map =3D &temp_map_gen2_v1, + .sync_thresholds =3D qpnp_tm_sync_thresholds, + .configure_trip_temps =3D qpnp_tm_configure_trip_temp, .get_temp_stage =3D qpnp_tm_gen2_get_temp_stage, }; =20 /* * This function initializes the internal temp value based on only the - * current thermal stage and threshold. Setup threshold control and - * disable shutdown override. + * current thermal stage and threshold. */ -static int qpnp_tm_init(struct qpnp_tm_chip *chip) +static int qpnp_tm_threshold_init(struct qpnp_tm_chip *chip) { - int crit_temp; - u8 threshold; int ret; - u8 reg; =20 - mutex_lock(&chip->lock); - - ret =3D qpnp_tm_read(chip, QPNP_TM_REG_SHUTDOWN_CTRL1, ®); + ret =3D chip->data->sync_thresholds(chip); if (ret < 0) - goto out; - - threshold =3D reg & SHUTDOWN_CTRL1_THRESHOLD_MASK; - memcpy(chip->temp_thresh_map, chip->data->temp_map[threshold], - sizeof(chip->temp_thresh_map)); - - chip->temp =3D DEFAULT_TEMP; + return ret; =20 ret =3D chip->data->get_temp_stage(chip); if (ret < 0) - goto out; + return ret; chip->stage =3D ret; + chip->temp =3D DEFAULT_TEMP; =20 if (chip->stage) chip->temp =3D qpnp_tm_decode_temp(chip, chip->stage); =20 - mutex_unlock(&chip->lock); - - ret =3D thermal_zone_get_crit_temp(chip->tz_dev, &crit_temp); - if (ret) - crit_temp =3D THERMAL_TEMP_INVALID; + return ret; +} =20 - mutex_lock(&chip->lock); +/* This function initializes threshold control and disables shutdown overr= ide. */ +static int qpnp_tm_init(struct qpnp_tm_chip *chip) +{ + int ret; + u8 reg; =20 - ret =3D qpnp_tm_update_critical_trip_temp(chip, crit_temp); + ret =3D chip->data->configure_trip_temps(chip); if (ret < 0) - goto out; + return ret; =20 /* Enable the thermal alarm PMIC module in always-on mode. */ reg =3D ALARM_CTRL_FORCE_ENABLE; @@ -381,8 +415,6 @@ static int qpnp_tm_init(struct qpnp_tm_chip *chip) =20 chip->initialized =3D true; =20 -out: - mutex_unlock(&chip->lock); return ret; } =20 @@ -481,13 +513,17 @@ static int qpnp_tm_probe(struct platform_device *pdev) } } =20 + ret =3D qpnp_tm_threshold_init(chip); + if (ret < 0) + return dev_err_probe(&pdev->dev, ret, "threshold init failed\n"); + /* * Register the sensor before initializing the hardware to be able to * read the trip points. get_temp() returns the default temperature * before the hardware initialization is completed. */ chip->tz_dev =3D devm_thermal_of_zone_register( - &pdev->dev, 0, chip, &qpnp_tm_sensor_ops); + &pdev->dev, 0, chip, chip->data->ops); if (IS_ERR(chip->tz_dev)) return dev_err_probe(&pdev->dev, PTR_ERR(chip->tz_dev), "failed to register sensor\n"); --=20 2.34.1