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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-23de4341d51sm30479615ad.189.2025.07.10.15.45.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Jul 2025 15:45:57 -0700 (PDT) From: Anjelique Melendez To: amitk@kernel.org, thara.gopinath@gmail.com, rafael@kernel.org, daniel.lezcano@linaro.org Cc: rui.zhang@intel.com, lukasz.luba@arm.com, david.collins@oss.qualcomm.com, stefan.schmidt@linaro.org, quic_tsoni@quicinc.com, konrad.dybcio@oss.qualcomm.com, linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dmitry.baryshkov@linaro.org, dmitry.baryshkov@oss.qualcomm.com Subject: [PATCH v6 1/5] thermal: qcom-spmi-temp-alarm: enable stage 2 shutdown when required Date: Thu, 10 Jul 2025 15:45:51 -0700 Message-Id: <20250710224555.3047790-2-anjelique.melendez@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250710224555.3047790-1-anjelique.melendez@oss.qualcomm.com> References: <20250710224555.3047790-1-anjelique.melendez@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzEwMDE5MSBTYWx0ZWRfXzrmpsll4NuF1 NwkeipieOVzYCv7BlFkgt63alv3IC+8opzRMW3gfP+TpXbV0G17VfdxKMTPycFrT7nFkEgOGMFk Qnp+fhl0ToGpwtfESf2jaMT87jDsPEfrjC0HVtPqH+J59tZSglojq3lzc6akv5K9AbH/ZD8jqlZ FuMyYVvhQfnM6MGICItxpvxNZoC1QgfE0I7xyj94WXHZLtN3y3wG1VI+B+OemJqPWFJ9MV9awbT RNcSVRZYpHxtaJmLyXYNJDXhySBablwt0xL5D8T9/q1GpRbCti6xuwfJJGHjJsgiEViNtosV5Au YPd2+0IrOjOi4Y9MbOu5Xng/vo4eEhuGLvVBPxLlMPEns/p4DcOTb3TUZj2pbwD5YPv4m+DN7O3 73LWohqS19b0ymjMHN1fRuqm8sa+AYqmfL/6iDZb+s8B2pRgGntvBGFiO+2haZDBoov5ccsw X-Proofpoint-GUID: R18P7Vd8B95mTiFtN8_UPZVMFZCxPBEE X-Authority-Analysis: v=2.4 cv=Xuf6OUF9 c=1 sm=1 tr=0 ts=687042a7 cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=Wb1JkmetP80A:10 a=EUspDBNiAAAA:8 a=2ebS6B6wQDVqfW-kuUgA:9 a=uG9DUKGECoFWVXl0Dc02:22 X-Proofpoint-ORIG-GUID: R18P7Vd8B95mTiFtN8_UPZVMFZCxPBEE X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.7,FMLib:17.12.80.40 definitions=2025-07-10_05,2025-07-09_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 bulkscore=0 spamscore=0 lowpriorityscore=0 impostorscore=0 clxscore=1015 priorityscore=1501 malwarescore=0 adultscore=0 mlxscore=0 phishscore=0 mlxlogscore=999 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507100191 Content-Type: text/plain; charset="utf-8" From: David Collins Certain TEMP_ALARM GEN2 PMIC peripherals need over-temperature stage 2 automatic PMIC partial shutdown. This will ensure that in the event of reaching the hotter stage 3 over-temperature threshold, repeated faults will be avoided during the automatic PMIC hardware full shutdown. Modify the stage 2 shutdown control logic to ensure that stage 2 shutdown is enabled on all affected PMICs. Read the digital major and minor revision registers to identify these PMICs. Signed-off-by: David Collins Signed-off-by: Anjelique Melendez --- drivers/thermal/qcom/qcom-spmi-temp-alarm.c | 43 ++++++++++++++++----- 1 file changed, 34 insertions(+), 9 deletions(-) diff --git a/drivers/thermal/qcom/qcom-spmi-temp-alarm.c b/drivers/thermal/= qcom/qcom-spmi-temp-alarm.c index a81e7d6e865f..4b91cc13ce34 100644 --- a/drivers/thermal/qcom/qcom-spmi-temp-alarm.c +++ b/drivers/thermal/qcom/qcom-spmi-temp-alarm.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2011-2015, 2017, 2020, The Linux Foundation. All rights r= eserved. + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ =20 #include @@ -16,6 +17,7 @@ =20 #include "../thermal_hwmon.h" =20 +#define QPNP_TM_REG_DIG_MINOR 0x00 #define QPNP_TM_REG_DIG_MAJOR 0x01 #define QPNP_TM_REG_TYPE 0x04 #define QPNP_TM_REG_SUBTYPE 0x05 @@ -31,7 +33,7 @@ #define STATUS_GEN2_STATE_MASK GENMASK(6, 4) #define STATUS_GEN2_STATE_SHIFT 4 =20 -#define SHUTDOWN_CTRL1_OVERRIDE_S2 BIT(6) +#define SHUTDOWN_CTRL1_OVERRIDE_STAGE2 BIT(6) #define SHUTDOWN_CTRL1_THRESHOLD_MASK GENMASK(1, 0) =20 #define SHUTDOWN_CTRL1_RATE_25HZ BIT(3) @@ -78,6 +80,7 @@ struct qpnp_tm_chip { /* protects .thresh, .stage and chip registers */ struct mutex lock; bool initialized; + bool require_stage2_shutdown; =20 struct iio_channel *adc; const long (*temp_map)[THRESH_COUNT][STAGE_COUNT]; @@ -220,13 +223,13 @@ static int qpnp_tm_update_critical_trip_temp(struct q= pnp_tm_chip *chip, { long stage2_threshold_min =3D (*chip->temp_map)[THRESH_MIN][1]; long stage2_threshold_max =3D (*chip->temp_map)[THRESH_MAX][1]; - bool disable_s2_shutdown =3D false; + bool disable_stage2_shutdown =3D false; u8 reg; =20 WARN_ON(!mutex_is_locked(&chip->lock)); =20 /* - * Default: S2 and S3 shutdown enabled, thresholds at + * Default: Stage 2 and Stage 3 shutdown enabled, thresholds at * lowest threshold set, monitoring at 25Hz */ reg =3D SHUTDOWN_CTRL1_RATE_25HZ; @@ -241,12 +244,12 @@ static int qpnp_tm_update_critical_trip_temp(struct q= pnp_tm_chip *chip, chip->thresh =3D THRESH_MAX - ((stage2_threshold_max - temp) / TEMP_THRESH_STEP); - disable_s2_shutdown =3D true; + disable_stage2_shutdown =3D true; } else { chip->thresh =3D THRESH_MAX; =20 if (chip->adc) - disable_s2_shutdown =3D true; + disable_stage2_shutdown =3D true; else dev_warn(chip->dev, "No ADC is configured and critical temperature %d mC is above the max= imum stage 2 threshold of %ld mC! Configuring stage 2 shutdown at %ld mC.\n= ", @@ -255,8 +258,8 @@ static int qpnp_tm_update_critical_trip_temp(struct qpn= p_tm_chip *chip, =20 skip: reg |=3D chip->thresh; - if (disable_s2_shutdown) - reg |=3D SHUTDOWN_CTRL1_OVERRIDE_S2; + if (disable_stage2_shutdown && !chip->require_stage2_shutdown) + reg |=3D SHUTDOWN_CTRL1_OVERRIDE_STAGE2; =20 return qpnp_tm_write(chip, QPNP_TM_REG_SHUTDOWN_CTRL1, reg); } @@ -350,8 +353,8 @@ static int qpnp_tm_probe(struct platform_device *pdev) { struct qpnp_tm_chip *chip; struct device_node *node; - u8 type, subtype, dig_major; - u32 res; + u8 type, subtype, dig_major, dig_minor; + u32 res, dig_revision; int ret, irq; =20 node =3D pdev->dev.of_node; @@ -402,6 +405,11 @@ static int qpnp_tm_probe(struct platform_device *pdev) return dev_err_probe(&pdev->dev, ret, "could not read dig_major\n"); =20 + ret =3D qpnp_tm_read(chip, QPNP_TM_REG_DIG_MINOR, &dig_minor); + if (ret < 0) + return dev_err_probe(&pdev->dev, ret, + "could not read dig_minor\n"); + if (type !=3D QPNP_TM_TYPE || (subtype !=3D QPNP_TM_SUBTYPE_GEN1 && subtype !=3D QPNP_TM_SUBTYPE_GEN2)) { dev_err(&pdev->dev, "invalid type 0x%02x or subtype 0x%02x\n", @@ -415,6 +423,23 @@ static int qpnp_tm_probe(struct platform_device *pdev) else chip->temp_map =3D &temp_map_gen1; =20 + if (chip->subtype =3D=3D QPNP_TM_SUBTYPE_GEN2) { + dig_revision =3D (dig_major << 8) | dig_minor; + /* + * Check if stage 2 automatic partial shutdown must remain + * enabled to avoid potential repeated faults upon reaching + * over-temperature stage 3. + */ + switch (dig_revision) { + case 0x0001: + case 0x0002: + case 0x0100: + case 0x0101: + chip->require_stage2_shutdown =3D true; + break; + } + } + /* * Register the sensor before initializing the hardware to be able to * read the trip points. get_temp() returns the default temperature --=20 2.34.1