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[93.70.53.177]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-454d50df125sm60871005e9.19.2025.07.10.09.28.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Jul 2025 09:28:10 -0700 (PDT) From: Stefano Radaelli To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Stefano Radaelli , Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 1/3] dt-bindings: arm: ti: Add bindings for Variscite VAR-SOM-AM62P Date: Thu, 10 Jul 2025 18:27:26 +0200 Message-ID: <20250710162737.49679-2-stefano.radaelli21@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250710162737.49679-1-stefano.radaelli21@gmail.com> References: <20250710162737.49679-1-stefano.radaelli21@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add devicetree bindings for Variscite VAR-SOM-AM62P System on Module and its carrier boards. Signed-off-by: Stefano Radaelli Acked-by: Rob Herring (Arm) --- v3: - Change compatible string to match existing mainline format v2: - Add symphony carrier board compatible Documentation/devicetree/bindings/arm/ti/k3.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/ti/k3.yaml b/Documentati= on/devicetree/bindings/arm/ti/k3.yaml index bf6003d8fb76..d56046e439e9 100644 --- a/Documentation/devicetree/bindings/arm/ti/k3.yaml +++ b/Documentation/devicetree/bindings/arm/ti/k3.yaml @@ -100,6 +100,12 @@ properties: - const: toradex,verdin-am62p # Verdin AM62P Module - const: ti,am62p5 =20 + - description: K3 AM62P5 SoC Variscite SOM and Carrier Boards + items: + - const: variscite,var-som-am62p-symphony + - const: variscite,var-som-am62p + - const: ti,am62p5 + - description: K3 AM642 SoC items: - enum: --=20 2.43.0 From nobody Thu Dec 18 03:26:08 2025 Received: from mail-wr1-f42.google.com (mail-wr1-f42.google.com [209.85.221.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9AC0B2EFDA2; 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[93.70.53.177]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-454d50df125sm60871005e9.19.2025.07.10.09.28.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Jul 2025 09:28:15 -0700 (PDT) From: Stefano Radaelli To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Stefano Radaelli , Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 2/3] arm64: dts: ti: Add support for Variscite VAR-SOM-AM62P Date: Thu, 10 Jul 2025 18:27:27 +0200 Message-ID: <20250710162737.49679-3-stefano.radaelli21@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250710162737.49679-1-stefano.radaelli21@gmail.com> References: <20250710162737.49679-1-stefano.radaelli21@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add device tree support for the Variscite VAR-SOM-AM62P system on module. This SOM is designed to be used with various carrier boards. The module includes: - AM62P Sitara MPU processor - Up to 8GB of DDR4-3733 memory - eMMC storage memory - PS6522430 chip as a Power Management Integrated circuit (PMIC) - Integrated 10/100/1000 Mbps Ethernet Transceiver Analog Devices ADIN1300 - Resistive touch panel interface controller TI TSC2046 - I2C interfaces Only SOM-specific peripherals are enabled by default. Carrier board specific interfaces are left disabled to be enabled in the respective carrier board device trees. Link: https://www.variscite.it/product/system-on-module-som/cortex-a53-krai= t/var-som-am62p-ti-sitara-am62px/ Signed-off-by: Stefano Radaelli --- v3: - Change compatible string to match existing mainline format - Lower case hex digits - Generic node names v2: - Fixed warnings and cleanup arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi | 370 ++++++++++++++++++ 1 file changed, 370 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi b/arch/arm64/boo= t/dts/ti/k3-am62p5-var-som.dtsi new file mode 100644 index 000000000000..7a93f37ac266 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi @@ -0,0 +1,370 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Common dtsi for Variscite VAR-SOM-AM62P + * + * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti= .com/ + * Copyright (C) 2025 Variscite Ltd. - https://www.variscite.com/ + * + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include "k3-am62p5.dtsi" + +/ { + compatible =3D "variscite,var-som-am62p", "ti,am62p5"; + + wifi_pwrseq: wifi-pwrseq { + compatible =3D "mmc-pwrseq-simple"; + post-power-on-delay-ms =3D <100>; + power-off-delay-us =3D <10000>; + reset-gpios =3D <&main_gpio0 54 GPIO_ACTIVE_LOW>, /* WIFI_PWR_EN */ + <&main_gpio0 59 GPIO_ACTIVE_LOW>; /* WIFI_EN */ + }; + + mmc_pwrseq: mmc-pwrseq { + compatible =3D "mmc-pwrseq-emmc"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_mmc_pwrseq>; + reset-gpios =3D <&main_gpio0 49 GPIO_ACTIVE_LOW>; + }; + + memory@80000000 { + /* 8G RAM */ + reg =3D <0x00000000 0x80000000 0x00000000 0x80000000>, + <0x00000008 0x80000000 0x00000001 0x80000000>; + device_type =3D "memory"; + bootph-pre-ram; + }; + + opp-table { + /* Add 1.4GHz OPP for am62p5-sk board. Requires VDD_CORE at 0v85 */ + opp-1400000000 { + opp-hz =3D /bits/ 64 <1400000000>; + opp-supported-hw =3D <0x01 0x0004>; + clock-latency-ns =3D <6000000>; + }; + }; + + reserved_memory: reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + rtos_ipc_memory_region: rtos-ipc-memory@9b500000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x9b500000 0x00 0x00300000>; + no-map; + }; + + mcu_r5fss0_core0_dma_memory_region: mcu-r5fss-dma-memory-region@9b800000= { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x9b800000 0x00 0x00100000>; + no-map; + }; + + mcu_r5fss0_core0_memory_region: mcu-r5fss-memory-region@9b900000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x9b900000 0x00 0x00f00000>; + no-map; + }; + + wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9c800000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x9c800000 0x00 0x00100000>; + no-map; + }; + + wkup_r5fss0_core0_memory_region: r5f-memory@9c900000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x9c900000 0x00 0x01e00000>; + no-map; + }; + + secure_tfa_ddr: tfa@9e780000 { + reg =3D <0x00 0x9e780000 0x00 0x80000>; + no-map; + }; + + secure_ddr: optee@9e800000 { + reg =3D <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ + no-map; + }; + }; + + reg_3v3: regulator-3v3 { + compatible =3D "regulator-fixed"; + regulator-name =3D "On-module +V3.3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_1v8: regulator-1v8 { + compatible =3D "regulator-fixed"; + regulator-name =3D "On-module +V1.8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + vin-supply =3D <®_3v3>; + regulator-always-on; + regulator-boot-on; + }; + + reg_3v3_phy: regulator-3v3-phy { + compatible =3D "regulator-fixed"; + regulator-name =3D "On-module +V3.3_PHY"; + gpios =3D <&main_gpio0 45 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + status=3D"okay"; + }; +}; + +&cpsw3g { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_rgmii1>; +}; + +&cpsw3g_mdio { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_mdio1>; + cpsw3g_phy0: ethernet-phy@4 { + reg =3D <4>; + compatible =3D "ethernet-phy-id0283.bc30"; + reset-gpios =3D <&main_gpio0 46 GPIO_ACTIVE_LOW>; + reset-assert-us =3D <10000>; + reset-deassert-us =3D <100000>; + }; +}; + +&cpsw_port1 { + /* + * The required RGMII TX and RX 2ns delays are implemented directly + * in hardware via passive delay elements on the SOM PCB. + * No delay configuration is needed in software via PHY driver. + */ + phy-mode =3D "rgmii"; + phy-handle =3D <&cpsw3g_phy0>; + status =3D "okay"; +}; + +&main_i2c2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_i2c2>; + clock-frequency =3D <400000>; + status =3D "okay"; +}; + +&main_i2c3 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_i2c3>; + clock-frequency =3D <400000>; + status =3D "okay"; +}; + +&main_pmx0 { + pinctrl_mmc_pwrseq: main-emmc-pwrseq-pins { + pinctrl-single,pins =3D < + AM62PX_IOPAD(0x00c8, PIN_OUTPUT, 7) /* (AB23) VOUT0_DATA4.GPIO0_49 */ + >; + }; + + pinctrl_i2c2: main-i2c2-default-pins { + pinctrl-single,pins =3D < + AM62PX_IOPAD(0x00b0, PIN_INPUT_PULLUP, 1) /* (T22) GPMC0_CSn2.I2C2_SCL = */ + AM62PX_IOPAD(0x00b4, PIN_INPUT_PULLUP, 1) /* (U25) GPMC0_CSn3.I2C2_SDA = */ + >; + }; + + pinctrl_i2c3: main-i2c3-default-pins { + pinctrl-single,pins =3D < + AM62PX_IOPAD(0x01d0, PIN_INPUT_PULLUP, 2) /* (A23) UART0_CTSn.I2C3_SCL = */ + AM62PX_IOPAD(0x01d4, PIN_INPUT_PULLUP, 2) /* (C22) UART0_RTSn.I2C3_SDA = */ + >; + }; + + pinctrl_mcasp1: main-mcasp1-default-pins { + pinctrl-single,pins =3D < + AM62PX_IOPAD(0x0090, PIN_INPUT, 2) /* (U24) GPMC0_BE0n_CLE.MCASP1_ACLKX= */ + AM62PX_IOPAD(0x0098, PIN_INPUT, 2) /* (AA24) GPMC0_WAIT0.MCASP1_AFSX */ + AM62PX_IOPAD(0x008c, PIN_OUTPUT, 2) /* (T25) GPMC0_WEn.MCASP1_AXR0 */ + AM62PX_IOPAD(0x0084, PIN_INPUT, 2) /* (R25) GPMC0_ADVn_ALE.MCASP1_AXR2 = */ + AM62PX_IOPAD(0x00a0, PIN_OUTPUT, 1) /* (P24) GPMC0_WPn.AUDIO_EXT_REFCLK= 1 */ + >; + }; + + pinctrl_mdio1: main-mdio1-default-pins { + pinctrl-single,pins =3D < + AM62PX_IOPAD(0x0160, PIN_OUTPUT, 0) /* (F17) MDIO0_MDC */ + AM62PX_IOPAD(0x015c, PIN_INPUT, 0) /* (F16) MDIO0_MDIO */ + >; + }; + + pinctrl_mmc2: main-mmc2-default-pins { + pinctrl-single,pins =3D < + AM62PX_IOPAD(0x0120, PIN_INPUT_PULLUP, 0) /* (K24) MMC2_CMD */ + AM62PX_IOPAD(0x0118, PIN_INPUT_PULLDOWN, 0) /* (K21) MMC2_CLK */ + AM62PX_IOPAD(0x011c, PIN_INPUT_PULLUP, 0) /* () MMC2_CLKLB */ + AM62PX_IOPAD(0x0114, PIN_INPUT_PULLUP, 0) /* (K23) MMC2_DAT0 */ + AM62PX_IOPAD(0x0110, PIN_INPUT_PULLUP, 0) /* (K22) MMC2_DAT1 */ + AM62PX_IOPAD(0x010c, PIN_INPUT_PULLUP, 0) /* (L20) MMC2_DAT2 */ + AM62PX_IOPAD(0x0108, PIN_INPUT_PULLUP, 0) /* (L21) MMC2_DAT3 */ + >; + }; + + pinctrl_rgmii1: main-rgmii1-default-pins { + pinctrl-single,pins =3D < + AM62PX_IOPAD(0x014c, PIN_INPUT, 0) /* (B15) RGMII1_RD0 */ + AM62PX_IOPAD(0x0150, PIN_INPUT, 0) /* (B16) RGMII1_RD1 */ + AM62PX_IOPAD(0x0154, PIN_INPUT, 0) /* (A14) RGMII1_RD2 */ + AM62PX_IOPAD(0x0158, PIN_INPUT, 0) /* (B14) RGMII1_RD3 */ + AM62PX_IOPAD(0x0148, PIN_INPUT, 0) /* (A16) RGMII1_RXC */ + AM62PX_IOPAD(0x0144, PIN_INPUT, 0) /* (A15) RGMII1_RX_CTL */ + AM62PX_IOPAD(0x0134, PIN_INPUT, 0) /* (A18) RGMII1_TD0 */ + AM62PX_IOPAD(0x0138, PIN_INPUT, 0) /* (C17) RGMII1_TD1 */ + AM62PX_IOPAD(0x013c, PIN_INPUT, 0) /* (A17) RGMII1_TD2 */ + AM62PX_IOPAD(0x0140, PIN_INPUT, 0) /* (C16) RGMII1_TD3 */ + AM62PX_IOPAD(0x0130, PIN_INPUT, 0) /* (B17) RGMII1_TXC */ + AM62PX_IOPAD(0x012c, PIN_INPUT, 0) /* (B18) RGMII1_TX_CTL */ + >; + bootph-all; + }; + + pinctrl_spi0: main-spi0-default-pins { + pinctrl-single,pins =3D < + AM62PX_IOPAD(0x01bc, PIN_OUTPUT, 0) /* (B21) SPI0_CLK */ + AM62PX_IOPAD(0x01b4, PIN_OUTPUT, 0) /* (D20) SPI0_CS0 */ + AM62PX_IOPAD(0x01c0, PIN_OUTPUT, 0) /* (B20) SPI0_D0 */ + AM62PX_IOPAD(0x01c4, PIN_INPUT, 0) /* (C21) SPI0_D1 */ + >; + }; + + pinctrl_uart5: main-uart5-default-pins { + pinctrl-single,pins =3D < + AM62PX_IOPAD(0x00ec, PIN_INPUT, 4) /* (AC21) VOUT0_DATA13.UART5_CTSn */ + AM62PX_IOPAD(0x00e8, PIN_OUTPUT, 4) /* (AD21) VOUT0_DATA12.UART5_RTSn */ + AM62PX_IOPAD(0x00d0, PIN_INPUT, 4) /* (AC23) VOUT0_DATA6.UART5_RXD */ + AM62PX_IOPAD(0x00d4, PIN_OUTPUT, 4) /* (AE23) VOUT0_DATA7.UART5_TXD */ + >; + }; + + pinctrl_bt: main-btgrp-pins { + pinctrl-single,pins =3D < + AM62PX_IOPAD(0x00f4, PIN_OUTPUT, 7) /* (Y20) VOUT0_DATA15.GPIO0_60 (BT_= EN) */ + >; + }; + + pinctrl_restouch: main-restouch-pins { + pinctrl-single,pins =3D < + AM62PX_IOPAD(0x00c4, PIN_INPUT_PULLUP, 7) /* (Y23) VOUT0_DATA3.GPIO0_48= */ + >; + }; + + pinctrl_wifi: main-wifi-default-pins { + pinctrl-single,pins =3D < + AM62PX_IOPAD(0x00dc, PIN_OUTPUT, 7) /* (AC22) VOUT0_DATA9.GPIO0_54 - WI= FI_PWR_EN - */ + AM62PX_IOPAD(0x00f0, PIN_OUTPUT, 7) /* (AA20) VOUT0_DATA14.GPIO0_59 - W= IFI_EN - */ + >; + }; +}; + +&mcu_pmx0 { + pinctrl_wkup_clkout0: wkup-clkout0-default-pins { + pinctrl-single,pins =3D < + AM62PX_MCU_IOPAD(0x0084, PIN_OUTPUT, 0) /* (F13) WKUP_CLKOUT0 */ + >; + }; +}; + +&main_spi0 { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_spi0>; + ti,pindir-d0-out-d1-in; + + touchscreen@0 { + compatible =3D "ti,ads7846"; + reg =3D <0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_restouch>; + interrupt-parent =3D <&main_gpio0>; + interrupts =3D <48 IRQ_TYPE_EDGE_FALLING>; + spi-max-frequency =3D <1500000>; + pendown-gpio =3D <&main_gpio0 48 GPIO_ACTIVE_LOW>; + ti,x-min =3D /bits/ 16 <125>; + ti,x-max =3D /bits/ 16 <4008>; + ti,y-min =3D /bits/ 16 <282>; + ti,y-max =3D /bits/ 16 <3864>; + ti,x-plate-ohms =3D /bits/ 16 <180>; + ti,pressure-max =3D /bits/ 16 <255>; + ti,debounce-max =3D /bits/ 16 <10>; + ti,debounce-tol =3D /bits/ 16 <3>; + ti,debounce-rep =3D /bits/ 16 <1>; + ti,settle-delay-usec =3D /bits/ 16 <150>; + ti,keep-vref-on; + wakeup-source; + }; +}; + +&main_uart5 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_uart5>, <&pinctrl_bt>; + uart-has-rtscts; + status =3D "okay"; + + bluetooth { + compatible =3D "nxp,88w8987-bt"; + }; +}; + +&mcasp1 { + status =3D "okay"; + #sound-dai-cells =3D <0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_mcasp1>; + op-mode =3D <0>; /* MCASP_IIS_MODE */ + tdm-slots =3D <2>; + serial-dir =3D < /* 0: INACTIVE, 1: TX, 2: RX */ + 1 0 2 0 + 0 0 0 0 + 0 0 0 0 + 0 0 0 0 + >; + tx-num-evt =3D <0>; + rx-num-evt =3D <0>; +}; + +&sdhci0 { + status =3D "okay"; + ti,driver-strength-ohm =3D <50>; + mmc-pwrseq =3D <&mmc_pwrseq>; + disable-wp; + bootph-all; +}; + +&sdhci2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_mmc2>, <&pinctrl_wifi>; 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[93.70.53.177]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-454d50df125sm60871005e9.19.2025.07.10.09.28.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Jul 2025 09:28:21 -0700 (PDT) From: Stefano Radaelli To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Stefano Radaelli , Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 3/3] arm64: dts: ti: var-som-am62p: Add support for Variscite Symphony Board Date: Thu, 10 Jul 2025 18:27:28 +0200 Message-ID: <20250710162737.49679-4-stefano.radaelli21@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250710162737.49679-1-stefano.radaelli21@gmail.com> References: <20250710162737.49679-1-stefano.radaelli21@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add device tree support for the Variscite Symphony carrier board with the VAR-SOM-AM62P system on module. The Symphony board includes - uSD Card support - USB ports and OTG - Additional Gigabit Ethernet interface - Uart interfaces - OV5640 Camera support - GPIO Expander - CAN, I2C and general purpose interfaces Link: https://www.variscite.it/product/single-board-computers/symphony-boar= d/ Signed-off-by: Stefano Radaelli --- v3: - Change compatible string to match existing mainline format - Fixed underscore typo v2: - Fixed warnings and cleanup arch/arm64/boot/dts/ti/Makefile | 1 + .../dts/ti/k3-am62p5-var-som-symphony.dts | 562 ++++++++++++++++++ 2 files changed, 563 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am62p5-var-som-symphony.dts diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makef= ile index c6171de9fe88..f8b1ed3cbdfa 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -35,6 +35,7 @@ dtb-$(CONFIG_ARCH_K3) +=3D k3-am62a7-phyboard-lyra-rdk.dtb =20 # Boards with AM62Px SoC dtb-$(CONFIG_ARCH_K3) +=3D k3-am62p5-sk.dtb +dtb-$(CONFIG_ARCH_K3) +=3D k3-am62p5-var-som-symphony.dtb dtb-$(CONFIG_ARCH_K3) +=3D k3-am62p5-verdin-nonwifi-dahlia.dtb dtb-$(CONFIG_ARCH_K3) +=3D k3-am62p5-verdin-nonwifi-dev.dtb dtb-$(CONFIG_ARCH_K3) +=3D k3-am62p5-verdin-nonwifi-ivy.dtb diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-var-som-symphony.dts b/arch/a= rm64/boot/dts/ti/k3-am62p5-var-som-symphony.dts new file mode 100644 index 000000000000..58e54968de7f --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62p5-var-som-symphony.dts @@ -0,0 +1,562 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Variscite Symphony carrier board for VAR-SOM-AM62P + * + * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti= .com/ + * Copyright (C) 2025 Variscite Ltd. - https://www.variscite.com/ + * + */ + +/dts-v1/; + +#include "k3-am62p5-var-som.dtsi" + +/ { + model =3D "Variscite VAR-SOM-AM62P on Symphony-Board"; + compatible =3D "variscite,var-som-am62p-symphony", "variscite,var-som-am6= 2p", "ti,am62p5"; + + aliases { + ethernet0 =3D &cpsw_port1; + ethernet1 =3D &cpsw_port2; + mmc0 =3D &sdhci0; + mmc1 =3D &sdhci1; + mmc2 =3D &sdhci2; + serial0 =3D &main_uart0; + serial2 =3D &main_uart2; + serial5 =3D &main_uart5; + serial6 =3D &main_uart6; + spi5 =3D &main_spi2; + usb0 =3D &usb0; + usb1 =3D &usb1; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + clk_ov5640_fixed: clock-24000000 { + #clock-cells =3D <0>; + compatible =3D "fixed-clock"; + clock-frequency =3D <24000000>; + }; + + gpio-keys { + compatible =3D "gpio-keys"; + + button-back { + label =3D "Back"; + linux,code =3D ; + gpios =3D <&pca9534 1 GPIO_ACTIVE_LOW>; + }; + + button-home { + label =3D "Home"; + linux,code =3D ; + gpios =3D <&pca9534 2 GPIO_ACTIVE_LOW>; + }; + + button-menu { + label =3D "Menu"; + linux,code =3D ; + gpios =3D <&pca9534 3 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-leds { + compatible =3D "gpio-leds"; + + led-heartbeat { + label =3D "Heartbeat"; + linux,default-trigger =3D "heartbeat"; + gpios =3D <&pca9534 0 GPIO_ACTIVE_LOW>; + }; + }; + + reg_2p8v: regulator-2p8v { + compatible =3D "regulator-fixed"; + regulator-name =3D "2P8V"; + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + vin-supply =3D <®_3v3>; + regulator-always-on; + }; + + reg_1p8v: regulator-1p8v { + compatible =3D "regulator-fixed"; + regulator-name =3D "1P8V"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + vin-supply =3D <®_3v3>; + regulator-always-on; + }; + + reg_1p5v: regulator-1p5v { + compatible =3D "regulator-fixed"; + regulator-name =3D "1P5V"; + regulator-min-microvolt =3D <1500000>; + regulator-max-microvolt =3D <1500000>; + vin-supply =3D <®_3v3>; + regulator-always-on; + }; + + reg_sdhc1_vmmc: regulator-sdhc1 { + compatible =3D "regulator-fixed"; + regulator-name =3D "+V3.3_SD"; + vin-supply =3D <®_sdhc1_vmmc_int>; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + enable-active-high; + gpio =3D <&main_gpio0 30 GPIO_ACTIVE_HIGH>; + bootph-all; + }; + + reg_sdhc1_vmmc_int: regulator-sdhc1-int { + compatible =3D "regulator-fixed"; + regulator-name =3D "+V3.3_SD_INT"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_sd1_vmmc>; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + enable-active-high; + gpio =3D <&main_gpio0 53 GPIO_ACTIVE_HIGH>; + bootph-all; + }; + + reg_sdhc1_vqmmc: regulator-sdhci1-vqmmc { + compatible =3D "regulator-gpio"; + regulator-name =3D "+V3.3_SD_VQMMC"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_sd1_vqmmc>; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + gpios =3D <&main_gpio0 56 GPIO_ACTIVE_HIGH>; + states =3D <1800000 0x0>, + <3300000 0x1>; + bootph-all; + }; + + reg_ov5640_buf_en: regulator-camera-buf-en { + compatible =3D "regulator-fixed"; + regulator-name =3D "ov5640_buf_en"; + gpios =3D <&main_gpio0 21 GPIO_ACTIVE_HIGH>; + regulator-always-on; + regulator-boot-on; + status=3D"okay"; + }; + + transceiver1: can-phy { + compatible =3D "ti,tcan1042"; + #phy-cells =3D <0>; + max-bitrate =3D <5000000>; + }; + + connector { + compatible =3D "gpio-usb-b-connector", "usb-b-connector"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_extcon>; + label =3D "USB-C"; + id-gpios =3D <&main_gpio1 12 GPIO_ACTIVE_HIGH>; + status =3D "okay"; + + port { + usb_con_hs: endpoint { + remote-endpoint =3D <&typec_hs>; + }; + }; + }; +}; + +&cdns_csi2rx0 { + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + csi0_port0: port@0 { + reg =3D <0>; + status =3D "okay"; + + csi2rx0_in_sensor: endpoint { + remote-endpoint =3D <&csi2_cam0>; + bus-type =3D <4>; /* CSI2 DPHY. */ + clock-lanes =3D <0>; + data-lanes =3D <1 2>; + }; + }; + }; +}; + +&cpsw3g { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_rgmii1>, + <&pinctrl_rgmii2>; +}; + +&cpsw3g_mdio { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_mdio1>; + + cpsw3g_phy1: ethernet-phy@5 { + reg =3D <5>; + compatible =3D "ethernet-phy-id0283.bc30"; + reset-gpios =3D <&pca9534 5 GPIO_ACTIVE_LOW>; + reset-assert-us =3D <10000>; + reset-deassert-us =3D <100000>; + }; +}; + +&cpsw_port2 { + /* + * The required RGMII TX and RX 2ns delays are implemented directly + * in hardware via passive delay elements on the Symphony PCB. + * No delay configuration is needed in software via PHY driver. + */ + phy-mode =3D "rgmii"; + phy-handle =3D <&cpsw3g_phy1>; + status =3D "okay"; +}; + +&dphy0 { + status =3D "okay"; +}; + +&mailbox0_cluster0 { + mbox_r5_0: mbox-r5-0 { + ti,mbox-rx =3D <0 0 0>; + ti,mbox-tx =3D <1 0 0>; + }; +}; + +&mailbox0_cluster1 { + mbox_mcu_r5_0: mbox-mcu-r5-0 { + ti,mbox-rx =3D <0 0 0>; + ti,mbox-tx =3D <1 0 0>; + }; +}; + +&main_i2c0{ + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_i2c0>; + clock-frequency =3D <400000>; + + ov5640: camera@3c { + compatible =3D "ovti,ov5640"; + reg =3D <0x3c>; + clocks =3D <&clk_ov5640_fixed>; + clock-names =3D "xclk"; + AVDD-supply =3D <®_2p8v>; + DOVDD-supply =3D <®_1p8v>; + DVDD-supply =3D <®_1p5v>; + powerdown-gpios =3D <&main_gpio0 10 GPIO_ACTIVE_HIGH>; + reset-gpios =3D <&main_gpio0 22 GPIO_ACTIVE_LOW>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_ov5640>; + + port { + csi2_cam0: endpoint { + remote-endpoint =3D <&csi2rx0_in_sensor>; + clock-lanes =3D <0>; + data-lanes =3D <1 2>; + }; + }; + }; + + /* GPIO expander */ + pca9534: gpio@20 { + compatible =3D "nxp,pca9534"; + reg =3D <0x20>; + gpio-controller; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_pca9534>; + interrupt-parent =3D <&main_gpio1>; + interrupts =3D <30 IRQ_TYPE_EDGE_FALLING>; + #gpio-cells =3D <2>; + status =3D "okay"; + + usb3-sel-hog { + gpio-hog; + gpios =3D <4 0>; + output-low; + line-name =3D "usb3_sel"; + }; + + eth-som-vselect-hog { + gpio-hog; + gpios =3D <6 0>; + output-low; + line-name =3D "eth-vselect"; + }; + + eth-mdio-enable-hog { + gpio-hog; + gpios =3D <7 0>; + output-high; + line-name =3D "eth-mdio-enable"; + }; + }; +}; + +&main_i2c1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_i2c1>; + clock-frequency =3D <400000>; + status =3D "okay"; + + rtc@68 { + compatible =3D "dallas,ds1337"; + reg =3D <0x68>; + status =3D "okay"; + }; +}; + +&main_mcan0 { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_mcan0>; + phys =3D <&transceiver1>; +}; + +&main_pmx0 { + pinctrl_extcon: main-extcon-pins { + pinctrl-single,pins =3D < + AM62PX_IOPAD(0x01a8, PIN_INPUT, 7) /* (F25) MCASP0_AFSX.GPIO1_12 */ + >; + }; + + pinctrl_i2c0: main-i2c0-default-pins { + pinctrl-single,pins =3D < + AM62PX_IOPAD(0x01e0, PIN_INPUT_PULLUP, 0) /* (B25) I2C0_SCL */ + AM62PX_IOPAD(0x01e4, PIN_INPUT_PULLUP, 0) /* (A24) I2C0_SDA */ + >; + }; + + pinctrl_i2c1: main-i2c1-default-pins { + pinctrl-single,pins =3D < + AM62PX_IOPAD(0x01e8, PIN_INPUT_PULLUP, 0) /* (C24) I2C1_SCL */ + AM62PX_IOPAD(0x01ec, PIN_INPUT_PULLUP, 0) /* (B24) I2C1_SDA */ + >; + bootph-all; + }; + + pinctrl_mcan0: main-mcan0-default-pins { + pinctrl-single,pins =3D < + AM62PX_IOPAD(0x01dc, PIN_INPUT, 0) /* (F20) MCAN0_RX */ + AM62PX_IOPAD(0x01d8, PIN_OUTPUT, 0) /* (B23) MCAN0_TX */ + >; + }; + + pinctrl_mmc1: main-mmc1-default-pins { + pinctrl-single,pins =3D < + AM62PX_IOPAD(0x023c, PIN_INPUT, 0) /* (H20) MMC1_CMD */ + AM62PX_IOPAD(0x0234, PIN_OUTPUT, 0) /* (J24) MMC1_CLK */ + AM62PX_IOPAD(0x0230, PIN_INPUT, 0) /* (H21) MMC1_DAT0 */ + AM62PX_IOPAD(0x022c, PIN_INPUT_PULLUP, 0) /* (H23) MMC1_DAT1 */ + AM62PX_IOPAD(0x0228, PIN_INPUT_PULLUP, 0) /* (H22) MMC1_DAT2 */ + AM62PX_IOPAD(0x0224, PIN_INPUT_PULLUP, 0) /* (H25) MMC1_DAT3 */ + AM62PX_IOPAD(0x0240, PIN_INPUT, 0) /* (D23) MMC1_SDCD */ + >; + bootph-all; + }; + + pinctrl_rgmii2: main-rgmii2-default-pins { + pinctrl-single,pins =3D < + AM62PX_IOPAD(0x0184, PIN_INPUT, 0) /* (E19) RGMII2_RD0 */ + AM62PX_IOPAD(0x0188, PIN_INPUT, 0) /* (E16) RGMII2_RD1 */ + AM62PX_IOPAD(0x018c, PIN_INPUT, 0) /* (E17) RGMII2_RD2 */ + AM62PX_IOPAD(0x0190, PIN_INPUT, 0) /* (C19) RGMII2_RD3 */ + AM62PX_IOPAD(0x0180, PIN_INPUT, 0) /* (D19) RGMII2_RXC */ + AM62PX_IOPAD(0x017c, PIN_INPUT, 0) /* (F19) RGMII2_RX_CTL */ + AM62PX_IOPAD(0x016c, PIN_INPUT, 0) /* (B19) RGMII2_TD0 */ + AM62PX_IOPAD(0x0170, PIN_INPUT, 0) /* (A21) RGMII2_TD1 */ + AM62PX_IOPAD(0x0174, PIN_INPUT, 0) /* (D17) RGMII2_TD2 */ + AM62PX_IOPAD(0x0178, PIN_INPUT, 0) /* (A19) RGMII2_TD3 */ + AM62PX_IOPAD(0x0168, PIN_INPUT_PULLDOWN, 0) /* (D16) RGMII2_TXC */ + AM62PX_IOPAD(0x0164, PIN_INPUT, 0) /* (A20) RGMII2_TX_CTL */ + >; + }; + + pinctrl_spi2: main-spi2-default-pins { + pinctrl-single,pins =3D < + AM62PX_IOPAD(0x01b0, PIN_INPUT, 1) /* (G20) MCASP0_ACLKR.SPI2_CLK */ + AM62PX_IOPAD(0x0194, PIN_OUTPUT, 1) /* (D25) MCASP0_AXR3.SPI2_D0 */ + AM62PX_IOPAD(0x0198, PIN_INPUT, 1) /* (E25) MCASP0_AXR2.SPI2_D1 */ + AM62PX_IOPAD(0x01ac, PIN_OUTPUT, 7) /* (G23) MCASP0_AFSR.GPIO1_13 */ + >; + }; + + pinctrl_uart0: main-uart0-default-pins { + pinctrl-single,pins =3D < + AM62PX_IOPAD(0x1c8, PIN_INPUT, 0) /* (A22) UART0_RXD */ + AM62PX_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (B22) UART0_TXD */ + >; + bootph-all; + }; + + pinctrl_uart2: main-uart2-default-pins { + pinctrl-single,pins =3D < + AM62PX_IOPAD(0x005c, PIN_INPUT_PULLUP, 2) /* (AC25) GPMC0_AD8.UART2_RXD= */ + AM62PX_IOPAD(0x0060, PIN_OUTPUT, 2) /* (AB25) GPMC0_AD9.UART2_TXD */ + >; + }; + + pinctrl_uart6: main-uart6-default-pins { + pinctrl-single,pins =3D < + AM62PX_IOPAD(0x009c, PIN_INPUT_PULLUP, 3) /* (AD24) GPMC0_WAIT1.UART6_R= XD */ + AM62PX_IOPAD(0x0244, PIN_OUTPUT, 1) /* (D24) MMC1_SDWP.UART6_TXD */ + >; + }; + + pinctrl_usb1: main-usb1-default-pins { + pinctrl-single,pins =3D < + AM62PX_IOPAD(0x0258, PIN_OUTPUT, 0) /* (G21) USB1_DRVVBUS */ + >; + }; + + pinctrl_ov5640: main-ov5640-pins { + pinctrl-single,pins =3D < + AM62PX_IOPAD(0x0028, PIN_OUTPUT, 7) /* (N20) OSPI0_D7.GPIO0_10 */ + AM62PX_IOPAD(0x0054, PIN_OUTPUT, 7) /* (V24) GPMC0_AD6.GPIO0_21 */ + AM62PX_IOPAD(0x0058, PIN_OUTPUT, 7) /* (W25) GPMC0_AD7.GPIO0_22 */ + >; + }; + + pinctrl_pca9534: main-pca9534-pins { + pinctrl-single,pins =3D < + AM62PX_IOPAD(0x01f0, PIN_INPUT, 7) /* (C25) EXT_REFCLK1.GPIO1_30 */ + >; + }; + + pinctrl_sd1_vmmc: main-sd1-vmmc-pins { + pinctrl-single,pins =3D < + AM62PX_IOPAD(0x0078, PIN_OUTPUT, 7) /* (AC24) GPMC0_AD15.GPIO0_30 */ + AM62PX_IOPAD(0x00d8, PIN_OUTPUT, 7) /* (AE22) VOUT0_DATA8.GPIO0_53 */ + >; + bootph-all; + }; + + pinctrl_sd1_vqmmc: main-sd1-vqmmc-pins { + pinctrl-single,pins =3D < + AM62PX_IOPAD(0x00e4, PIN_OUTPUT, 7) /* (AE21) VOUT0_DATA11.GPIO0_56 */ + >; + bootph-all; + }; +}; + +&main_spi2 { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_spi2>; + ti,pindir-d0-out-d1-in; + cs-gpios =3D <&main_gpio1 13 GPIO_ACTIVE_HIGH>; +}; + +&main_uart0 { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_uart0>; +}; + +&main_uart1 { + /* Main UART1 is used by TIFS firmware */ + status =3D "reserved"; +}; + +&main_uart2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_uart2>; + status =3D "okay"; +}; + +&main_uart6 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_uart6>; + status =3D "okay"; +}; + +&mcu_gpio0 { + status =3D "reserved"; +}; + +&mcu_gpio_intr { + status =3D "reserved"; +}; + +&mcu_r5fss0 { + status =3D "okay"; +}; + +&mcu_r5fss0_core0 { + mboxes =3D <&mailbox0_cluster1 &mbox_mcu_r5_0>; + memory-region =3D <&mcu_r5fss0_core0_dma_memory_region>, + <&mcu_r5fss0_core0_memory_region>; +}; + +&sdhci1 { + /* SD Card */ + vmmc-supply =3D <®_sdhc1_vmmc>; + vqmmc-supply =3D <®_sdhc1_vqmmc>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_mmc1>; + disable-wp; + status=3D"okay"; + bootph-all; +}; + +&ti_csi2rx0 { + status =3D "okay"; +}; + +&usb0 { + usb-role-switch; + status =3D "okay"; + + port { + typec_hs: endpoint { + remote-endpoint =3D <&usb_con_hs>; + }; + }; +}; + +&usb1 { + dr_mode =3D "host"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pinctrl_usb1>; + status =3D "okay"; +}; + +&usbss0 { + status =3D "okay"; +}; + +&usbss1 { + status =3D "okay"; +}; + +&wkup_r5fss0 { + status =3D "okay"; +}; + +&wkup_r5fss0_core0 { + mboxes =3D <&mailbox0_cluster0 &mbox_r5_0>; + memory-region =3D <&wkup_r5fss0_core0_dma_memory_region>, + <&wkup_r5fss0_core0_memory_region>; +}; + +&wkup_rtc0 { + status =3D "disabled"; +}; + +&wkup_rti0 { + /* WKUP RTI0 is used by DM firmware */ + status =3D "reserved"; +}; + +&wkup_uart0 { + /* WKUP UART0 is used by DM firmware */ + status =3D "reserved"; +}; --=20 2.43.0