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Thu, 10 Jul 2025 06:12:43 -0700 From: Akhil R To: , , , , , , , , , CC: , , , , Subject: [PATCH v6 1/3] i2c: tegra: Fix reset error handling with ACPI Date: Thu, 10 Jul 2025 18:42:04 +0530 Message-ID: <20250710131206.2316-2-akhilrajeev@nvidia.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250710131206.2316-1-akhilrajeev@nvidia.com> References: <20250710131206.2316-1-akhilrajeev@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF000015C7:EE_|SA0PR12MB4368:EE_ X-MS-Office365-Filtering-Correlation-Id: ef432b09-2874-4768-5099-08ddbfb380f8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|376014|7416014|82310400026|1800799024|7053199007|921020; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Jul 2025 13:13:03.8685 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ef432b09-2874-4768-5099-08ddbfb380f8 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF000015C7.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB4368 Content-Type: text/plain; charset="utf-8" The acpi_evaluate_object() returns an ACPI error code and not Linux one. For the some platforms the err will have positive code which may be interpreted incorrectly. Use device_reset for reset control which handles it correctly. Fixes: bd2fdedbf2ba ("i2c: tegra: Add the ACPI support") Reported-by: Andy Shevchenko Signed-off-by: Akhil R Reviewed-by: Andy Shevchenko --- drivers/i2c/busses/i2c-tegra.c | 24 +----------------------- 1 file changed, 1 insertion(+), 23 deletions(-) diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c index 049b4d154c23..687d1e608abc 100644 --- a/drivers/i2c/busses/i2c-tegra.c +++ b/drivers/i2c/busses/i2c-tegra.c @@ -607,7 +607,6 @@ static int tegra_i2c_wait_for_config_load(struct tegra_= i2c_dev *i2c_dev) static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev) { u32 val, clk_divisor, clk_multiplier, tsu_thd, tlow, thigh, non_hs_mode; - acpi_handle handle =3D ACPI_HANDLE(i2c_dev->dev); struct i2c_timings *t =3D &i2c_dev->timings; int err; =20 @@ -619,11 +618,7 @@ static int tegra_i2c_init(struct tegra_i2c_dev *i2c_de= v) * emit a noisy warning on error, which won't stay unnoticed and * won't hose machine entirely. */ - if (handle) - err =3D acpi_evaluate_object(handle, "_RST", NULL, NULL); - else - err =3D reset_control_reset(i2c_dev->rst); - + err =3D device_reset(i2c_dev->dev); WARN_ON_ONCE(err); =20 if (IS_DVC(i2c_dev)) @@ -1666,19 +1661,6 @@ static void tegra_i2c_parse_dt(struct tegra_i2c_dev = *i2c_dev) i2c_dev->is_vi =3D true; } =20 -static int tegra_i2c_init_reset(struct tegra_i2c_dev *i2c_dev) -{ - if (ACPI_HANDLE(i2c_dev->dev)) - return 0; - - i2c_dev->rst =3D devm_reset_control_get_exclusive(i2c_dev->dev, "i2c"); - if (IS_ERR(i2c_dev->rst)) - return dev_err_probe(i2c_dev->dev, PTR_ERR(i2c_dev->rst), - "failed to get reset control\n"); - - return 0; -} - static int tegra_i2c_init_clocks(struct tegra_i2c_dev *i2c_dev) { int err; @@ -1788,10 +1770,6 @@ static int tegra_i2c_probe(struct platform_device *p= dev) =20 tegra_i2c_parse_dt(i2c_dev); =20 - err =3D tegra_i2c_init_reset(i2c_dev); - if (err) - return err; - err =3D tegra_i2c_init_clocks(i2c_dev); if (err) return err; --=20 2.50.1 From nobody Tue Oct 7 09:52:24 2025 Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2058.outbound.protection.outlook.com [40.107.94.58]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DD5FC2E54DD; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Jul 2025 13:13:09.0121 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d9f67dea-4e62-4465-61c3-08ddbfb38404 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00002319.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL3PR12MB6572 Content-Type: text/plain; charset="utf-8" For controllers that has an internal software reset, make the reset property optional. This provides and option to use I2C in systems that choose to restrict reset control from Linux or not to implement the ACPI _RST method. Internal reset was not required when the reset control was mandatory. But on platforms where the resets are outside the control of Linux, this had to be implemented by just returning success from BPMP or with an empty _RST method in the ACPI table, basically ignoring the reset. While the internal reset is not identical to the hard reset of the controller, this will reset all the internal state of the controller including FIFOs. This may slightly alter the behaviour in systems which were ignoring the reset but it should not cause any functional difference since all the required I2C registers are configured after this reset, just as in boot. Considering that this sequence is hit during the boot or during the I2C recovery path from an error, the internal reset provides a better alternative than just ignoring the reset. Signed-off-by: Akhil R Reviewed-by: Andy Shevchenko --- drivers/i2c/busses/i2c-tegra.c | 35 ++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c index 687d1e608abc..e291b8586214 100644 --- a/drivers/i2c/busses/i2c-tegra.c +++ b/drivers/i2c/busses/i2c-tegra.c @@ -134,6 +134,8 @@ #define I2C_MST_FIFO_STATUS_TX GENMASK(23, 16) #define I2C_MST_FIFO_STATUS_RX GENMASK(7, 0) =20 +#define I2C_MASTER_RESET_CNTRL 0x0a8 + /* configuration load timeout in microseconds */ #define I2C_CONFIG_LOAD_TIMEOUT 1000000 =20 @@ -184,6 +186,9 @@ enum msg_end_type { * @has_mst_fifo: The I2C controller contains the new MST FIFO interface t= hat * provides additional features and allows for longer messages to * be transferred in one go. + * @has_mst_reset: The I2C controller contains MASTER_RESET_CTRL register = which + * provides an alternative to controller reset when configured as + * I2C master * @quirks: I2C adapter quirks for limiting write/read transfer size and n= ot * allowing 0 length transfers. * @supports_bus_clear: Bus Clear support to recover from bus hang during @@ -213,6 +218,7 @@ struct tegra_i2c_hw_feature { bool has_multi_master_mode; bool has_slcg_override_reg; bool has_mst_fifo; + bool has_mst_reset; const struct i2c_adapter_quirks *quirks; bool supports_bus_clear; bool has_apb_dma; @@ -603,6 +609,26 @@ static int tegra_i2c_wait_for_config_load(struct tegra= _i2c_dev *i2c_dev) =20 return 0; } + +static int tegra_i2c_master_reset(struct tegra_i2c_dev *i2c_dev) +{ + if (!i2c_dev->hw->has_mst_reset) + return -EOPNOTSUPP; + + /* + * Writing 1 to I2C_MASTER_RESET_CNTRL will reset all internal state of + * Master logic including FIFOs. Clear this bit to 0 for normal operation. + * SW needs to wait for 2us after assertion and de-assertion of this soft + * reset. + */ + i2c_writel(i2c_dev, 0x1, I2C_MASTER_RESET_CNTRL); + fsleep(2); + + i2c_writel(i2c_dev, 0x0, I2C_MASTER_RESET_CNTRL); + fsleep(2); + + return 0; +} =20 static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev) { @@ -619,6 +645,9 @@ static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev) * won't hose machine entirely. */ err =3D device_reset(i2c_dev->dev); + if (err =3D=3D -ENOENT) + err =3D tegra_i2c_master_reset(i2c_dev); + WARN_ON_ONCE(err); =20 if (IS_DVC(i2c_dev)) @@ -1467,6 +1496,7 @@ static const struct tegra_i2c_hw_feature tegra20_i2c_= hw =3D { .has_multi_master_mode =3D false, .has_slcg_override_reg =3D false, .has_mst_fifo =3D false, + .has_mst_reset =3D false, .quirks =3D &tegra_i2c_quirks, .supports_bus_clear =3D false, .has_apb_dma =3D true, @@ -1491,6 +1521,7 @@ static const struct tegra_i2c_hw_feature tegra30_i2c_= hw =3D { .has_multi_master_mode =3D false, .has_slcg_override_reg =3D false, .has_mst_fifo =3D false, + .has_mst_reset =3D false, .quirks =3D &tegra_i2c_quirks, .supports_bus_clear =3D false, .has_apb_dma =3D true, @@ -1515,6 +1546,7 @@ static const struct tegra_i2c_hw_feature tegra114_i2c= _hw =3D { .has_multi_master_mode =3D false, .has_slcg_override_reg =3D false, .has_mst_fifo =3D false, + .has_mst_reset =3D false, .quirks =3D &tegra_i2c_quirks, .supports_bus_clear =3D true, .has_apb_dma =3D true, @@ -1539,6 +1571,7 @@ static const struct tegra_i2c_hw_feature tegra124_i2c= _hw =3D { .has_multi_master_mode =3D false, .has_slcg_override_reg =3D true, .has_mst_fifo =3D false, + .has_mst_reset =3D false, .quirks =3D &tegra_i2c_quirks, .supports_bus_clear =3D true, .has_apb_dma =3D true, @@ -1563,6 +1596,7 @@ static const struct tegra_i2c_hw_feature tegra210_i2c= _hw =3D { .has_multi_master_mode =3D false, .has_slcg_override_reg =3D true, .has_mst_fifo =3D false, + .has_mst_reset =3D false, .quirks =3D &tegra_i2c_quirks, .supports_bus_clear =3D true, .has_apb_dma =3D true, @@ -1587,6 +1621,7 @@ static const struct tegra_i2c_hw_feature tegra186_i2c= _hw =3D { .has_multi_master_mode =3D false, .has_slcg_override_reg =3D true, .has_mst_fifo =3D false, + .has_mst_reset =3D false, .quirks =3D &tegra_i2c_quirks, .supports_bus_clear =3D true, .has_apb_dma =3D false, @@ -1611,6 +1646,7 @@ static const struct tegra_i2c_hw_feature tegra194_i2c= _hw =3D { .has_multi_master_mode =3D true, .has_slcg_override_reg =3D true, .has_mst_fifo =3D true, + .has_mst_reset =3D true, .quirks =3D &tegra194_i2c_quirks, .supports_bus_clear =3D true, .has_apb_dma =3D false, --=20 2.50.1 From nobody Tue Oct 7 09:52:24 2025 Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on2067.outbound.protection.outlook.com [40.107.92.67]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 230FE2E54AD; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Jul 2025 13:13:29.4016 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5aa7bf31-432e-4a70-0ed9-08ddbfb3902c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF0000231C.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB5880 Content-Type: text/plain; charset="utf-8" Calling dma_sync_*() on a buffer from dma_alloc_coherent() is pointless. The driver should not be doing its own bounce-buffering if the buffer is allocated through dma_alloc_coherent(). Suggested-by: Robin Murphy Signed-off-by: Akhil R Reviewed-by: Thierry Reding Reviewed-by: Andy Shevchenko --- drivers/i2c/busses/i2c-tegra.c | 20 +------------------- 1 file changed, 1 insertion(+), 19 deletions(-) diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c index e291b8586214..04a9610c0736 100644 --- a/drivers/i2c/busses/i2c-tegra.c +++ b/drivers/i2c/busses/i2c-tegra.c @@ -1293,17 +1293,9 @@ static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *= i2c_dev, =20 if (i2c_dev->dma_mode) { if (i2c_dev->msg_read) { - dma_sync_single_for_device(i2c_dev->dma_dev, - i2c_dev->dma_phys, - xfer_size, DMA_FROM_DEVICE); - err =3D tegra_i2c_dma_submit(i2c_dev, xfer_size); if (err) return err; - } else { - dma_sync_single_for_cpu(i2c_dev->dma_dev, - i2c_dev->dma_phys, - xfer_size, DMA_TO_DEVICE); } } =20 @@ -1313,11 +1305,6 @@ static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *= i2c_dev, if (i2c_dev->dma_mode) { memcpy(i2c_dev->dma_buf + I2C_PACKET_HEADER_SIZE, msg->buf, i2c_dev->msg_len); - - dma_sync_single_for_device(i2c_dev->dma_dev, - i2c_dev->dma_phys, - xfer_size, DMA_TO_DEVICE); - err =3D tegra_i2c_dma_submit(i2c_dev, xfer_size); if (err) return err; @@ -1358,13 +1345,8 @@ static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *= i2c_dev, return -ETIMEDOUT; } =20 - if (i2c_dev->msg_read && i2c_dev->msg_err =3D=3D I2C_ERR_NONE) { - dma_sync_single_for_cpu(i2c_dev->dma_dev, - i2c_dev->dma_phys, - xfer_size, DMA_FROM_DEVICE); - + if (i2c_dev->msg_read && i2c_dev->msg_err =3D=3D I2C_ERR_NONE) memcpy(i2c_dev->msg_buf, i2c_dev->dma_buf, i2c_dev->msg_len); - } } =20 time_left =3D tegra_i2c_wait_completion(i2c_dev, &i2c_dev->msg_complete, --=20 2.50.1