From nobody Tue Oct 7 10:37:49 2025 Received: from mail-pf1-f174.google.com (mail-pf1-f174.google.com [209.85.210.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D559725BEE1; Thu, 10 Jul 2025 12:27:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.174 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752150439; cv=none; b=gatuT3WS1w5wuzzI/NjgValtXFZDa/GQOm1B6dwK22GtrUCxM8y0s3HNF07c6jkOIp03RmH7I8iOMFkR7XIPZzlc07ehxXG5tBA3PMSqvgBgQAhmRlrBX1JzCpFSar0aUo2xfcn9eHiSR9yZMBfpajUrJ2JXZdsFHcUbGIYj2Xw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752150439; c=relaxed/simple; bh=MwYLu8Cyrq0IOP8H0Vp4M9U+gqvXRZUCsUGSh0+CU0I=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=GWgr7aGHuIV+5y5JvwFQnYfpkUh9SsP3u2qteHVTUdcI2A/19pmb3/YjRt/oHxN0mA0Ka9ajil5g6zjvDdR7bRQNkOSY+IxUNDGbZ1yWR6OBluV/SO4n8MOK22Oa6WF53Rzf/yl6wKiJUoipLb+KB46bNofSC6+FoRioFOl7OLY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=KF1LLpUF; arc=none smtp.client-ip=209.85.210.174 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="KF1LLpUF" Received: by mail-pf1-f174.google.com with SMTP id d2e1a72fcca58-748e63d4b05so585858b3a.2; Thu, 10 Jul 2025 05:27:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1752150436; x=1752755236; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Cu6L8Wens3Xd97BtOblnnT1iHNxYfpRL7TluS0Us0tU=; b=KF1LLpUFGjlmc5zABFEuLwTmz6shg7lvJqYHr+OwYTAeXeSfCdZSuDB5QzTN6KRf0Y 95+rLaFftQNUDJFYSPf8R/z1pCDGcqfj69ErOzqqpLrq8YRvSXyoOsFqqkar2Urz4yJA 8/14AMO9Le49jV1RvI5R3v0HOwk/tZEwekrqIdOKFgWmCrPvXvIoNkf8X3z57Me6FjnB +bzO9yjYkRhTMuPXdmxP9l2klHn/qdT+lHZq1CY4eL90TyxXaQXow0FMLqyAs3CLDjq8 k1OqYuDCqpiTO1ugyg9OhOD66KI0256H7+7XXPsidr08J0k3hmzGpF1Si4+f82KRvfbV d1rg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1752150436; x=1752755236; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Cu6L8Wens3Xd97BtOblnnT1iHNxYfpRL7TluS0Us0tU=; b=bAWxie+dez1F5qev9uu/asrPtXyDxLomMIY80FtP4khBYH2cvMnX1I1H3BjtY3uXYu +In9Gsud5HjT1ITR4MFyBMy5OJDUODgzHxrBAj9wBJp6ymVLKJa4/TNLanVEhSonxqSO Un/WwERFRS3uNat0XPi9c6XlR2bTA70e+baIW17rwCU1O0w4i3/gd/TGvBVD+eImR1UZ p+iHUswJKDpxNsAwrX5+oCqJgf67hEgcJiEPzWgf2gF9ar9Z2gNgRp/JcAOrzEDtW/lM 8nnPtCMxHN3ilLaRIYLEcPIMhDqC2MfwmObpW2uiBNbHbozcDv0U39DK8kXId4T43AJS s93A== X-Forwarded-Encrypted: i=1; AJvYcCVsmikNL+21Ombi+vkUpGHhfHRGReeN64EB3scO0BDsDR06gc1cMm6uIXj0UFilAB5sz5uie/5dvUUv@vger.kernel.org, AJvYcCWruZi+ae4OY+MkvoT1VgAX5vH+L9AHGZltaSRrc9NxBZeWLqEGw5IOGvnW2dk55vpH1x91a10j0yyFcJsQ@vger.kernel.org X-Gm-Message-State: AOJu0YzzMhhlke2RuqpDVyvGAroy5tWI4JNyeyq+2mBXG3K/swhoimRl xD/QLWVmMCDsw5926Gff+r+G69xxFnAx3j5NQV8tcUuivaPtLR6+Zj9b X-Gm-Gg: ASbGncsnBJnq2Qy9D8UXqn0ot2CU1jvfAu2t/mnNLhtaLKnfyl2R+8mil3YK2cK2Xpe 9WpGDbRIMTFVbrXFlUfeB7r6tDYnmy+PCn830Q0r0JhM1T6Co5XGjO1Xur/ap9/nomdwiWCGBEU n+Y/52mMpcPt+AZJT2KlMQD9hxazUj7bdkr0ElNm09O1OAmrvPXURThYwBqrB5Yx5yz7UW0n23F LUAZb6EevXBFUvyxHj6fYc8xUoMR7CxBXD0ojO8P/zPZwy/Pm54W7uT/8lZljySyxevM/CTnWUH VFdxhgJZpMSxY/EBGhIuuyqtcQJFF9xQQAOwtwhr313cl01Cxtx+e119nFnzanI= X-Google-Smtp-Source: AGHT+IGphQ/UAr06I6OM4M5FMFoBZXYClQLMTzV+u7Oxtic12d8hgoM8g0uRosGBnxW6lBqm5BcWKw== X-Received: by 2002:a05:6a00:2d06:b0:740:aa31:fe66 with SMTP id d2e1a72fcca58-74eb8e86889mr3786363b3a.4.1752150435850; Thu, 10 Jul 2025 05:27:15 -0700 (PDT) Received: from nuvole.lan ([144.202.86.13]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-74eb9f8bfe1sm2116413b3a.155.2025.07.10.05.27.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Jul 2025 05:27:15 -0700 (PDT) From: Pengyu Luo To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Pengyu Luo Subject: [PATCH RESEND v3 1/1] arm64: dts: qcom: sc8280xp: Add GPI DMA configuration Date: Thu, 10 Jul 2025 20:26:35 +0800 Message-ID: <20250710122635.231282-2-mitltlatltl@gmail.com> X-Mailer: git-send-email 2.50.0 In-Reply-To: <20250710122635.231282-1-mitltlatltl@gmail.com> References: <20250710122635.231282-1-mitltlatltl@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" SPI on SC8280XP requires DMA (GSI) mode to function properly. Without it, SPI controllers fall back to FIFO mode, which causes: [ 0.901296] geni_spi 898000.spi: error -ENODEV: Failed to get tx DMA ch [ 0.901305] geni_spi 898000.spi: FIFO mode disabled, but couldn't get DM= A, fall back to FIFO mode ... [ 45.605974] goodix-spi-hid spi0.0: SPI transfer timed out [ 45.605988] geni_spi 898000.spi: Can't set CS when prev xfer running [ 46.621555] spi_master spi0: failed to transfer one message from queue [ 46.621568] spi_master spi0: noqueue transfer failed [ 46.621577] goodix-spi-hid spi0.0: spi transfer error: -110 [ 46.621585] goodix-spi-hid spi0.0: probe with driver goodix-spi-hid fail= ed with error -110 Therefore, add GPI DMA controller nodes for qup{0,1,2}, and add DMA channels for SPI and I2C, UART is excluded for now, as it does not yet support this mode. Note that, since there is no public schematic, this configuration is derived from Windows drivers. The drivers do not expose any DMA channel mask information, so all available channels are enabled. Signed-off-by: Pengyu Luo --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 368 +++++++++++++++++++++++++ 1 file changed, 368 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/q= com/sc8280xp.dtsi index 87555a119..5b2e62356 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -912,6 +913,32 @@ gpu_speed_bin: gpu-speed-bin@18b { }; }; =20 + gpi_dma2: dma-controller@800000 { + compatible =3D "qcom,sc8280xp-gpi-dma", "qcom,sm6350-gpi-dma"; + reg =3D <0 0x00800000 0 0x60000>; + + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + ; + + dma-channels =3D <12>; + dma-channel-mask =3D <0xfff>; + #dma-cells =3D <3>; + + iommus =3D <&apps_smmu 0xb6 0x0>; + + status =3D "disabled"; + }; + qup2: geniqup@8c0000 { compatible =3D "qcom,geni-se-qup"; reg =3D <0 0x008c0000 0 0x2000>; @@ -939,6 +966,12 @@ i2c16: i2c@880000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 = 0>, <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + + dmas =3D <&gpi_dma2 0 0 QCOM_GPI_I2C>, + <&gpi_dma2 1 0 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; }; =20 @@ -955,6 +988,12 @@ spi16: spi@880000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 = 0>, <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + + dmas =3D <&gpi_dma2 0 0 QCOM_GPI_SPI>, + <&gpi_dma2 1 0 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; }; =20 @@ -971,6 +1010,12 @@ i2c17: i2c@884000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 = 0>, <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + + dmas =3D <&gpi_dma2 0 1 QCOM_GPI_I2C>, + <&gpi_dma2 1 1 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; }; =20 @@ -987,6 +1032,12 @@ spi17: spi@884000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 = 0>, <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + + dmas =3D <&gpi_dma2 0 1 QCOM_GPI_SPI>, + <&gpi_dma2 1 1 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; }; =20 @@ -1017,6 +1068,12 @@ i2c18: i2c@888000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 = 0>, <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + + dmas =3D <&gpi_dma2 0 2 QCOM_GPI_I2C>, + <&gpi_dma2 1 2 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; }; =20 @@ -1033,6 +1090,12 @@ spi18: spi@888000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 = 0>, <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + + dmas =3D <&gpi_dma2 0 2 QCOM_GPI_SPI>, + <&gpi_dma2 1 2 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; }; =20 @@ -1067,6 +1130,12 @@ i2c19: i2c@88c000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 = 0>, <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + + dmas =3D <&gpi_dma2 0 3 QCOM_GPI_I2C>, + <&gpi_dma2 1 3 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; }; =20 @@ -1083,6 +1152,12 @@ spi19: spi@88c000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 = 0>, <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + + dmas =3D <&gpi_dma2 0 3 QCOM_GPI_SPI>, + <&gpi_dma2 1 3 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; }; =20 @@ -1099,6 +1174,12 @@ i2c20: i2c@890000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 = 0>, <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + + dmas =3D <&gpi_dma2 0 4 QCOM_GPI_I2C>, + <&gpi_dma2 1 4 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; }; =20 @@ -1115,6 +1196,12 @@ spi20: spi@890000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 = 0>, <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + + dmas =3D <&gpi_dma2 0 4 QCOM_GPI_SPI>, + <&gpi_dma2 1 4 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; }; =20 @@ -1131,6 +1218,12 @@ i2c21: i2c@894000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + + dmas =3D <&gpi_dma2 0 5 QCOM_GPI_I2C>, + <&gpi_dma2 1 5 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; }; =20 @@ -1147,6 +1240,12 @@ spi21: spi@894000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 = 0>, <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + + dmas =3D <&gpi_dma2 0 5 QCOM_GPI_SPI>, + <&gpi_dma2 1 5 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; }; =20 @@ -1163,6 +1262,12 @@ i2c22: i2c@898000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + + dmas =3D <&gpi_dma2 0 6 QCOM_GPI_I2C>, + <&gpi_dma2 1 6 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; }; =20 @@ -1179,6 +1284,12 @@ spi22: spi@898000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 = 0>, <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + + dmas =3D <&gpi_dma2 0 6 QCOM_GPI_SPI>, + <&gpi_dma2 1 6 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; }; =20 @@ -1195,6 +1306,12 @@ i2c23: i2c@89c000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + + dmas =3D <&gpi_dma2 0 7 QCOM_GPI_I2C>, + <&gpi_dma2 1 7 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; }; =20 @@ -1211,10 +1328,43 @@ spi23: spi@89c000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 = 0>, <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + + dmas =3D <&gpi_dma2 0 7 QCOM_GPI_SPI>, + <&gpi_dma2 1 7 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; }; }; =20 + gpi_dma0: dma-controller@900000 { + compatible =3D "qcom,sc8280xp-gpi-dma", "qcom,sm6350-gpi-dma"; + reg =3D <0 0x00900000 0 0x60000>; + + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + ; + + dma-channels =3D <13>; + dma-channel-mask =3D <0x1fff>; + #dma-cells =3D <3>; + + iommus =3D <&apps_smmu 0x576 0x0>; + + status =3D "disabled"; + }; + qup0: geniqup@9c0000 { compatible =3D "qcom,geni-se-qup"; reg =3D <0 0x009c0000 0 0x6000>; @@ -1242,6 +1392,12 @@ i2c0: i2c@980000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + + dmas =3D <&gpi_dma0 0 0 QCOM_GPI_I2C>, + <&gpi_dma0 1 0 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; }; =20 @@ -1258,6 +1414,12 @@ spi0: spi@980000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + + dmas =3D <&gpi_dma0 0 0 QCOM_GPI_SPI>, + <&gpi_dma0 1 0 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; }; =20 @@ -1274,6 +1436,12 @@ i2c1: i2c@984000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + + dmas =3D <&gpi_dma0 0 1 QCOM_GPI_I2C>, + <&gpi_dma0 1 1 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; }; =20 @@ -1290,6 +1458,12 @@ spi1: spi@984000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + + dmas =3D <&gpi_dma0 0 1 QCOM_GPI_SPI>, + <&gpi_dma0 1 1 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; }; =20 @@ -1306,6 +1480,12 @@ i2c2: i2c@988000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + + dmas =3D <&gpi_dma0 0 2 QCOM_GPI_I2C>, + <&gpi_dma0 1 2 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; }; =20 @@ -1322,6 +1502,12 @@ spi2: spi@988000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + + dmas =3D <&gpi_dma0 0 2 QCOM_GPI_SPI>, + <&gpi_dma0 1 2 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; }; =20 @@ -1352,6 +1538,12 @@ i2c3: i2c@98c000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + + dmas =3D <&gpi_dma0 0 3 QCOM_GPI_I2C>, + <&gpi_dma0 1 3 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; }; =20 @@ -1368,6 +1560,12 @@ spi3: spi@98c000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + + dmas =3D <&gpi_dma0 0 3 QCOM_GPI_SPI>, + <&gpi_dma0 1 3 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; }; =20 @@ -1384,6 +1582,12 @@ i2c4: i2c@990000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + + dmas =3D <&gpi_dma0 0 4 QCOM_GPI_I2C>, + <&gpi_dma0 1 4 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; }; =20 @@ -1400,6 +1604,12 @@ spi4: spi@990000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + + dmas =3D <&gpi_dma0 0 4 QCOM_GPI_SPI>, + <&gpi_dma0 1 4 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; }; =20 @@ -1416,6 +1626,12 @@ i2c5: i2c@994000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + + dmas =3D <&gpi_dma0 0 5 QCOM_GPI_I2C>, + <&gpi_dma0 1 5 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; }; =20 @@ -1432,6 +1648,12 @@ spi5: spi@994000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + + dmas =3D <&gpi_dma0 0 5 QCOM_GPI_SPI>, + <&gpi_dma0 1 5 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; }; =20 @@ -1448,6 +1670,12 @@ i2c6: i2c@998000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + + dmas =3D <&gpi_dma0 0 6 QCOM_GPI_I2C>, + <&gpi_dma0 1 6 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; }; =20 @@ -1464,6 +1692,12 @@ spi6: spi@998000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + + dmas =3D <&gpi_dma0 0 6 QCOM_GPI_SPI>, + <&gpi_dma0 1 6 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; }; =20 @@ -1480,6 +1714,12 @@ i2c7: i2c@99c000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + + dmas =3D <&gpi_dma0 0 7 QCOM_GPI_I2C>, + <&gpi_dma0 1 7 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; }; =20 @@ -1496,10 +1736,42 @@ spi7: spi@99c000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + + dmas =3D <&gpi_dma0 0 7 QCOM_GPI_SPI>, + <&gpi_dma0 1 7 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; }; }; =20 + gpi_dma1: dma-controller@a00000 { + compatible =3D "qcom,sc8280xp-gpi-dma", "qcom,sm6350-gpi-dma"; + reg =3D <0 0x00a00000 0 0x60000>; + + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + ; + + dma-channels =3D <12>; + dma-channel-mask =3D <0xfff>; + #dma-cells =3D <3>; + + iommus =3D <&apps_smmu 0x96 0x0>; + + status =3D "disabled"; + }; + qup1: geniqup@ac0000 { compatible =3D "qcom,geni-se-qup"; reg =3D <0 0x00ac0000 0 0x6000>; @@ -1527,6 +1799,12 @@ i2c8: i2c@a80000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 = 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + + dmas =3D <&gpi_dma1 0 0 QCOM_GPI_I2C>, + <&gpi_dma1 1 0 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; }; =20 @@ -1543,6 +1821,12 @@ spi8: spi@a80000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 = 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + + dmas =3D <&gpi_dma1 0 0 QCOM_GPI_SPI>, + <&gpi_dma1 1 0 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; }; =20 @@ -1559,6 +1843,12 @@ i2c9: i2c@a84000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 = 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + + dmas =3D <&gpi_dma1 0 1 QCOM_GPI_I2C>, + <&gpi_dma1 1 1 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; }; =20 @@ -1575,6 +1865,12 @@ spi9: spi@a84000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 = 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + + dmas =3D <&gpi_dma1 0 1 QCOM_GPI_SPI>, + <&gpi_dma1 1 1 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; }; =20 @@ -1591,6 +1887,12 @@ i2c10: i2c@a88000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 = 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + + dmas =3D <&gpi_dma1 0 2 QCOM_GPI_I2C>, + <&gpi_dma1 1 2 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; }; =20 @@ -1607,6 +1909,12 @@ spi10: spi@a88000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 = 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + + dmas =3D <&gpi_dma1 0 2 QCOM_GPI_SPI>, + <&gpi_dma1 1 2 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; }; =20 @@ -1623,6 +1931,12 @@ i2c11: i2c@a8c000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 = 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + + dmas =3D <&gpi_dma1 0 3 QCOM_GPI_I2C>, + <&gpi_dma1 1 3 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; }; =20 @@ -1639,6 +1953,12 @@ spi11: spi@a8c000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 = 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + + dmas =3D <&gpi_dma1 0 3 QCOM_GPI_SPI>, + <&gpi_dma1 1 3 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; }; =20 @@ -1655,6 +1975,12 @@ i2c12: i2c@a90000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 = 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + + dmas =3D <&gpi_dma1 0 4 QCOM_GPI_I2C>, + <&gpi_dma1 1 4 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; }; =20 @@ -1671,6 +1997,12 @@ spi12: spi@a90000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 = 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + + dmas =3D <&gpi_dma1 0 4 QCOM_GPI_SPI>, + <&gpi_dma1 1 4 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; }; =20 @@ -1687,6 +2019,12 @@ i2c13: i2c@a94000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 = 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + + dmas =3D <&gpi_dma1 0 5 QCOM_GPI_I2C>, + <&gpi_dma1 1 5 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; }; =20 @@ -1703,6 +2041,12 @@ spi13: spi@a94000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 = 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + + dmas =3D <&gpi_dma1 0 5 QCOM_GPI_SPI>, + <&gpi_dma1 1 5 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; }; =20 @@ -1719,6 +2063,12 @@ i2c14: i2c@a98000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 = 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + + dmas =3D <&gpi_dma1 0 6 QCOM_GPI_I2C>, + <&gpi_dma1 1 6 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; }; =20 @@ -1735,6 +2085,12 @@ spi14: spi@a98000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 = 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + + dmas =3D <&gpi_dma1 0 6 QCOM_GPI_SPI>, + <&gpi_dma1 1 6 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; }; =20 @@ -1751,6 +2107,12 @@ i2c15: i2c@a9c000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 = 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + + dmas =3D <&gpi_dma1 0 7 QCOM_GPI_I2C>, + <&gpi_dma1 1 7 QCOM_GPI_I2C>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; }; =20 @@ -1767,6 +2129,12 @@ spi15: spi@a9c000 { <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 = 0>, <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names =3D "qup-core", "qup-config", "qup-memory"; + + dmas =3D <&gpi_dma1 0 7 QCOM_GPI_SPI>, + <&gpi_dma1 1 7 QCOM_GPI_SPI>; + dma-names =3D "tx", + "rx"; + status =3D "disabled"; }; }; --=20 2.50.0