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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Jul 2025 10:12:40.6765 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8bef3777-1c70-46af-810e-08ddbf9a4dca X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099D5.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6587 Content-Type: text/plain; charset="utf-8" AXI DMA driver incorrectly assumes complete transfer completion upon IRQ reception, particularly problematic when IRQ coalescing is active. Updating the tail pointer dynamically fixes it. Remove existing idle state validation in the beginning of xilinx_dma_start_transfer() as it blocks valid transfer initiation on busy channels with queued descriptors. Additionally, refactor xilinx_dma_start_transfer() to consolidate coalesce and delay configurations while conditionally starting channels only when idle. Signed-off-by: Suraj Gupta Fixes: Fixes: c0bba3a99f07 ("dmaengine: vdma: Add Support for Xilinx AXI Di= rect Memory Access Engine") Tested-by: Folker Schwesinger --- drivers/dma/xilinx/xilinx_dma.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dm= a.c index a34d8f0ceed8..187749b7b8a6 100644 --- a/drivers/dma/xilinx/xilinx_dma.c +++ b/drivers/dma/xilinx/xilinx_dma.c @@ -1548,9 +1548,6 @@ static void xilinx_dma_start_transfer(struct xilinx_d= ma_chan *chan) if (list_empty(&chan->pending_list)) return; =20 - if (!chan->idle) - return; - head_desc =3D list_first_entry(&chan->pending_list, struct xilinx_dma_tx_descriptor, node); tail_desc =3D list_last_entry(&chan->pending_list, @@ -1558,23 +1555,24 @@ static void xilinx_dma_start_transfer(struct xilinx= _dma_chan *chan) tail_segment =3D list_last_entry(&tail_desc->segments, struct xilinx_axidma_tx_segment, node); =20 + if (chan->has_sg && list_empty(&chan->active_list)) + xilinx_write(chan, XILINX_DMA_REG_CURDESC, + head_desc->async_tx.phys); + reg =3D dma_ctrl_read(chan, XILINX_DMA_REG_DMACR); =20 if (chan->desc_pendingcount <=3D XILINX_DMA_COALESCE_MAX) { reg &=3D ~XILINX_DMA_CR_COALESCE_MAX; reg |=3D chan->desc_pendingcount << XILINX_DMA_CR_COALESCE_SHIFT; - dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg); } =20 - if (chan->has_sg) - xilinx_write(chan, XILINX_DMA_REG_CURDESC, - head_desc->async_tx.phys); reg &=3D ~XILINX_DMA_CR_DELAY_MAX; reg |=3D chan->irq_delay << XILINX_DMA_CR_DELAY_SHIFT; dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg); =20 - xilinx_dma_start(chan); + if (chan->idle) + xilinx_dma_start(chan); =20 if (chan->err) return; @@ -1914,8 +1912,10 @@ static irqreturn_t xilinx_dma_irq_handler(int irq, v= oid *data) XILINX_DMA_DMASR_DLY_CNT_IRQ)) { spin_lock(&chan->lock); xilinx_dma_complete_descriptor(chan); - chan->idle =3D true; - chan->start_transfer(chan); + if (list_empty(&chan->active_list)) { + chan->idle =3D true; + chan->start_transfer(chan); + } spin_unlock(&chan->lock); } =20 --=20 2.25.1