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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Jul 2025 10:12:37.1940 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 73e6dac1-eaa9-4b6b-c0c0-08ddbf9a4bb7 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099D8.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB6925 Content-Type: text/plain; charset="utf-8" Interrupt coalescing is a mechanism to reduce the number of hardware interrupts triggered ether until a certain amount of work is pending, or a timeout timer triggers. Tuning the interrupt coalesce settings involves adjusting the amount of work and timeout delay. Many DMA controllers support to configure coalesce count and delay. Add support to configure them via dma_slave_config and read using dma_slave_caps. Signed-off-by: Suraj Gupta --- include/linux/dmaengine.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h index bb146c5ac3e4..c7c1adb8e571 100644 --- a/include/linux/dmaengine.h +++ b/include/linux/dmaengine.h @@ -431,6 +431,9 @@ enum dma_slave_buswidth { * @peripheral_config: peripheral configuration for programming peripheral * for dmaengine transfer * @peripheral_size: peripheral configuration buffer size + * @coalesce_cnt: Maximum number of transfers before receiving an interrup= t. + * @coalesce_usecs: How many usecs to delay an interrupt after a transfer + * is completed. * * This struct is passed in as configuration data to a DMA engine * in order to set up a certain channel for DMA transport at runtime. @@ -457,6 +460,8 @@ struct dma_slave_config { bool device_fc; void *peripheral_config; size_t peripheral_size; + u32 coalesce_cnt; + u32 coalesce_usecs; }; =20 /** @@ -507,6 +512,9 @@ enum dma_residue_granularity { * @residue_granularity: granularity of the reported transfer residue * @descriptor_reuse: if a descriptor can be reused by client and * resubmitted multiple times + * @coalesce_cnt: Maximum number of transfers before receiving an interrup= t. + * @coalesce_usecs: How many usecs to delay an interrupt after a transfer + * is completed. */ struct dma_slave_caps { u32 src_addr_widths; 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Thu, 10 Jul 2025 05:12:37 -0500 From: Suraj Gupta To: , , , , , , CC: , , , , Subject: [PATCH V2 2/4] dmaengine: xilinx_dma: Fix irq handler and start transfer path for AXI DMA Date: Thu, 10 Jul 2025 15:42:27 +0530 Message-ID: <20250710101229.804183-3-suraj.gupta2@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250710101229.804183-1-suraj.gupta2@amd.com> References: <20250710101229.804183-1-suraj.gupta2@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: None (SATLEXMB04.amd.com: suraj.gupta2@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF000099D5:EE_|PH7PR12MB6587:EE_ X-MS-Office365-Filtering-Correlation-Id: 8bef3777-1c70-46af-810e-08ddbf9a4dca X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|376014|82310400026; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Jul 2025 10:12:40.6765 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8bef3777-1c70-46af-810e-08ddbf9a4dca X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099D5.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6587 Content-Type: text/plain; charset="utf-8" AXI DMA driver incorrectly assumes complete transfer completion upon IRQ reception, particularly problematic when IRQ coalescing is active. Updating the tail pointer dynamically fixes it. Remove existing idle state validation in the beginning of xilinx_dma_start_transfer() as it blocks valid transfer initiation on busy channels with queued descriptors. Additionally, refactor xilinx_dma_start_transfer() to consolidate coalesce and delay configurations while conditionally starting channels only when idle. Signed-off-by: Suraj Gupta Fixes: Fixes: c0bba3a99f07 ("dmaengine: vdma: Add Support for Xilinx AXI Di= rect Memory Access Engine") Tested-by: Folker Schwesinger --- drivers/dma/xilinx/xilinx_dma.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dm= a.c index a34d8f0ceed8..187749b7b8a6 100644 --- a/drivers/dma/xilinx/xilinx_dma.c +++ b/drivers/dma/xilinx/xilinx_dma.c @@ -1548,9 +1548,6 @@ static void xilinx_dma_start_transfer(struct xilinx_d= ma_chan *chan) if (list_empty(&chan->pending_list)) return; =20 - if (!chan->idle) - return; - head_desc =3D list_first_entry(&chan->pending_list, struct xilinx_dma_tx_descriptor, node); tail_desc =3D list_last_entry(&chan->pending_list, @@ -1558,23 +1555,24 @@ static void xilinx_dma_start_transfer(struct xilinx= _dma_chan *chan) tail_segment =3D list_last_entry(&tail_desc->segments, struct xilinx_axidma_tx_segment, node); =20 + if (chan->has_sg && list_empty(&chan->active_list)) + xilinx_write(chan, XILINX_DMA_REG_CURDESC, + head_desc->async_tx.phys); + reg =3D dma_ctrl_read(chan, XILINX_DMA_REG_DMACR); =20 if (chan->desc_pendingcount <=3D XILINX_DMA_COALESCE_MAX) { reg &=3D ~XILINX_DMA_CR_COALESCE_MAX; reg |=3D chan->desc_pendingcount << XILINX_DMA_CR_COALESCE_SHIFT; - dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg); } =20 - if (chan->has_sg) - xilinx_write(chan, XILINX_DMA_REG_CURDESC, - head_desc->async_tx.phys); reg &=3D ~XILINX_DMA_CR_DELAY_MAX; reg |=3D chan->irq_delay << XILINX_DMA_CR_DELAY_SHIFT; dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg); =20 - xilinx_dma_start(chan); + if (chan->idle) + xilinx_dma_start(chan); =20 if (chan->err) return; @@ -1914,8 +1912,10 @@ static irqreturn_t xilinx_dma_irq_handler(int irq, v= oid *data) XILINX_DMA_DMASR_DLY_CNT_IRQ)) { spin_lock(&chan->lock); xilinx_dma_complete_descriptor(chan); - chan->idle =3D true; - chan->start_transfer(chan); + if (list_empty(&chan->active_list)) { + chan->idle =3D true; + chan->start_transfer(chan); + } spin_unlock(&chan->lock); } =20 --=20 2.25.1 From nobody Tue Oct 7 10:30:53 2025 Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2072.outbound.protection.outlook.com [40.107.94.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5F3752D979A; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Jul 2025 10:12:45.0173 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 34c3cc99-70dc-49be-d27c-08ddbf9a5069 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001EF.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4341 Content-Type: text/plain; charset="utf-8" AXI DMA supports interrupt coalescing. Client can fine-tune coalesce parameters based on transaction load. Add support to configure/ report coalesce parameters. Change delay setting to scale with SG clock rate rather than being a fixed number of clock cycles (Referred from AXI ethernet driver). Increase Buffer Descriptors ring size from 512 to 1024 to allow sufficient space in BD ring during max coalesce count of 255. Signed-off-by: Suraj Gupta --- drivers/dma/xilinx/xilinx_dma.c | 73 +++++++++++++++++++++++++++++---- 1 file changed, 66 insertions(+), 7 deletions(-) diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dm= a.c index 187749b7b8a6..26f328cd3e10 100644 --- a/drivers/dma/xilinx/xilinx_dma.c +++ b/drivers/dma/xilinx/xilinx_dma.c @@ -33,6 +33,7 @@ * */ =20 +#include #include #include #include @@ -159,6 +160,9 @@ XILINX_DMA_DMASR_SOF_EARLY_ERR | \ XILINX_DMA_DMASR_DMA_INT_ERR) =20 +/* Constant to convert delay counts to microseconds */ +#define XILINX_DMA_DELAY_SCALE (125ULL * USEC_PER_SEC) + /* Axi VDMA Flush on Fsync bits */ #define XILINX_DMA_FLUSH_S2MM 3 #define XILINX_DMA_FLUSH_MM2S 2 @@ -184,7 +188,7 @@ #define XILINX_DMA_BD_EOP BIT(26) #define XILINX_DMA_BD_COMP_MASK BIT(31) #define XILINX_DMA_COALESCE_MAX 255 -#define XILINX_DMA_NUM_DESCS 512 +#define XILINX_DMA_NUM_DESCS 1024 #define XILINX_DMA_NUM_APP_WORDS 5 =20 /* AXI CDMA Specific Registers/Offsets */ @@ -403,6 +407,7 @@ struct xilinx_dma_tx_descriptor { * @terminating: Check for channel being synchronized by user * @tasklet: Cleanup work after irq * @config: Device configuration info + * @slave_cfg: Device configuration info from Dmaengine * @flush_on_fsync: Flush on Frame sync * @desc_pendingcount: Descriptor pending count * @ext_addr: Indicates 64 bit addressing is supported by dma channel @@ -442,6 +447,7 @@ struct xilinx_dma_chan { bool terminating; struct tasklet_struct tasklet; struct xilinx_vdma_config config; + struct dma_slave_config slave_cfg; bool flush_on_fsync; u32 desc_pendingcount; bool ext_addr; @@ -1540,7 +1546,9 @@ static void xilinx_dma_start_transfer(struct xilinx_d= ma_chan *chan) { struct xilinx_dma_tx_descriptor *head_desc, *tail_desc; struct xilinx_axidma_tx_segment *tail_segment; - u32 reg; + struct dma_slave_config *slave_cfg =3D &chan->slave_cfg; + u64 clk_rate; + u32 reg, usec, timer; =20 if (chan->err) return; @@ -1561,14 +1569,32 @@ static void xilinx_dma_start_transfer(struct xilinx= _dma_chan *chan) =20 reg =3D dma_ctrl_read(chan, XILINX_DMA_REG_DMACR); =20 - if (chan->desc_pendingcount <=3D XILINX_DMA_COALESCE_MAX) { - reg &=3D ~XILINX_DMA_CR_COALESCE_MAX; + reg &=3D ~XILINX_DMA_CR_COALESCE_MAX; + reg &=3D ~XILINX_DMA_CR_DELAY_MAX; + + /* Use dma_slave_config if it has valid values */ + if (slave_cfg->coalesce_cnt && + slave_cfg->coalesce_cnt <=3D XILINX_DMA_COALESCE_MAX) + reg |=3D slave_cfg->coalesce_cnt << + XILINX_DMA_CR_COALESCE_SHIFT; + else if (chan->desc_pendingcount <=3D XILINX_DMA_COALESCE_MAX) reg |=3D chan->desc_pendingcount << XILINX_DMA_CR_COALESCE_SHIFT; - } =20 - reg &=3D ~XILINX_DMA_CR_DELAY_MAX; - reg |=3D chan->irq_delay << XILINX_DMA_CR_DELAY_SHIFT; + if (slave_cfg->coalesce_usecs <=3D XILINX_DMA_DMACR_DELAY_MAX) + usec =3D slave_cfg->coalesce_usecs; + else + usec =3D chan->irq_delay; + + /* Scale with SG clock rate rather than being a fixed number of + * clock cycles. + * 1 Timeout Interval =3D 125 * (clock period of SG clock) + */ + clk_rate =3D clk_get_rate(chan->xdev->rx_clk); + timer =3D DIV64_U64_ROUND_CLOSEST((u64)usec * clk_rate, + XILINX_DMA_DELAY_SCALE); + timer =3D min(timer, FIELD_MAX(XILINX_DMA_DMACR_DELAY_MASK)); + reg |=3D timer << XILINX_DMA_CR_DELAY_SHIFT; dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg); =20 if (chan->idle) @@ -1701,9 +1727,41 @@ static void xilinx_dma_issue_pending(struct dma_chan= *dchan) static int xilinx_dma_device_config(struct dma_chan *dchan, struct dma_slave_config *config) { + struct xilinx_dma_chan *chan =3D to_xilinx_chan(dchan); + + if (chan->xdev->dma_config->dmatype !=3D XDMA_TYPE_AXIDMA) + return 0; + + if (!config->coalesce_cnt || + config->coalesce_cnt > XILINX_DMA_DMACR_FRAME_COUNT_MAX || + config->coalesce_usecs > XILINX_DMA_DMACR_DELAY_MAX) + return -EINVAL; + + chan->slave_cfg.coalesce_cnt =3D config->coalesce_cnt; + chan->slave_cfg.coalesce_usecs =3D config->coalesce_usecs; + return 0; } =20 +static void xilinx_dma_device_caps(struct dma_chan *dchan, + struct dma_slave_caps *caps) +{ + struct xilinx_dma_chan *chan =3D to_xilinx_chan(dchan); + u64 clk_rate, timer; + u32 reg; + + if (chan->xdev->dma_config->dmatype !=3D XDMA_TYPE_AXIDMA) + return; + + reg =3D dma_ctrl_read(chan, XILINX_DMA_REG_DMACR); + caps->coalesce_cnt =3D FIELD_GET(XILINX_DMA_CR_COALESCE_MAX, reg); + + clk_rate =3D clk_get_rate(chan->xdev->rx_clk); + timer =3D FIELD_GET(XILINX_DMA_CR_DELAY_MAX, reg); + caps->coalesce_usecs =3D DIV64_U64_ROUND_CLOSEST(timer * XILINX_DMA_DELAY= _SCALE, + clk_rate); +} + /** * xilinx_dma_complete_descriptor - Mark the active descriptor as complete * @chan : xilinx DMA channel @@ -3178,6 +3236,7 @@ static int xilinx_dma_probe(struct platform_device *p= dev) xdev->common.device_tx_status =3D xilinx_dma_tx_status; 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Thu, 10 Jul 2025 05:12:46 -0500 Received: from xhdsuragupt40.xilinx.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server id 15.1.2507.39 via Frontend Transport; Thu, 10 Jul 2025 05:12:43 -0500 From: Suraj Gupta To: , , , , , , CC: , , , , Subject: [PATCH V2 4/4] net: xilinx: axienet: Add ethtool support to configure/report irq coalescing parameters in DMAengine flow Date: Thu, 10 Jul 2025 15:42:29 +0530 Message-ID: <20250710101229.804183-5-suraj.gupta2@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250710101229.804183-1-suraj.gupta2@amd.com> References: <20250710101229.804183-1-suraj.gupta2@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF000099D6:EE_|MW3PR12MB4394:EE_ X-MS-Office365-Filtering-Correlation-Id: 71f2f611-7859-4141-1cad-08ddbf9a5205 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|36860700013|376014; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Jul 2025 10:12:47.7714 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 71f2f611-7859-4141-1cad-08ddbf9a5205 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099D6.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW3PR12MB4394 Content-Type: text/plain; charset="utf-8" Add support to configure and report interrupt coalesce count and delay via ethtool in DMAEngine flow. Enable Tx and Rx adaptive irq coalescing with DIM to allow runtime configuration of coalesce count based on load. CQE profiles same as legacy (non-dmaengine) flow are used. Increase Rx skb ring size from 128 as maximum coalesce packets are 255. Netperf numbers and CPU usage after DIM: TCP Tx: 885 Mb/s, 27.02% TCP Rx: 640 Mb/s, 27.73% UDP Tx: 857 Mb/s, 25.00% UDP Rx: 730 Mb/s, 23.94% Above numbers are observed with 4x Cortex-a53. Signed-off-by: Suraj Gupta --- drivers/net/ethernet/xilinx/xilinx_axienet.h | 13 +- .../net/ethernet/xilinx/xilinx_axienet_main.c | 190 +++++++++++++++++- 2 files changed, 190 insertions(+), 13 deletions(-) diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet.h b/drivers/net/eth= ernet/xilinx/xilinx_axienet.h index 5ff742103beb..747efde9a05f 100644 --- a/drivers/net/ethernet/xilinx/xilinx_axienet.h +++ b/drivers/net/ethernet/xilinx/xilinx_axienet.h @@ -126,6 +126,9 @@ #define XAXIDMA_DFT_TX_USEC 50 #define XAXIDMA_DFT_RX_USEC 16 =20 +/* Default TX delay timer value for SGDMA mode with DMAEngine */ +#define XAXIDMAENGINE_DFT_TX_USEC 16 + #define XAXIDMA_BD_CTRL_TXSOF_MASK 0x08000000 /* First tx packet */ #define XAXIDMA_BD_CTRL_TXEOF_MASK 0x04000000 /* Last tx packet */ #define XAXIDMA_BD_CTRL_ALL_MASK 0x0C000000 /* All control bits */ @@ -485,8 +488,11 @@ struct skbuf_dma_descriptor { * @dma_regs: Base address for the axidma device address space * @napi_rx: NAPI RX control structure * @rx_dim: DIM state for the receive queue - * @rx_dim_enabled: Whether DIM is enabled or not - * @rx_irqs: Number of interrupts + * @tx_dim: DIM state for the transmit queue + * @rx_dim_enabled: Whether Rx DIM is enabled or not + * @tx_dim_enabled: Whether Tx DIM is enabled or not + * @rx_irqs: Number of Rx interrupts + * @tx_irqs: Number of Tx interrupts * @rx_cr_lock: Lock protecting @rx_dma_cr, its register, and @rx_dma_star= ted * @rx_dma_cr: Nominal content of RX DMA control register * @rx_dma_started: Set when RX DMA is started @@ -570,8 +576,11 @@ struct axienet_local { =20 struct napi_struct napi_rx; struct dim rx_dim; + struct dim tx_dim; bool rx_dim_enabled; + bool tx_dim_enabled; u16 rx_irqs; + u16 tx_irqs; spinlock_t rx_cr_lock; u32 rx_dma_cr; bool rx_dma_started; diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c b/drivers/ne= t/ethernet/xilinx/xilinx_axienet_main.c index 6011d7eae0c7..2c7cc092fbe8 100644 --- a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c +++ b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c @@ -54,7 +54,7 @@ #define RX_BD_NUM_MAX 4096 #define DMA_NUM_APP_WORDS 5 #define LEN_APP 4 -#define RX_BUF_NUM_DEFAULT 128 +#define RX_BUF_NUM_DEFAULT 512 =20 /* Must be shorter than length of ethtool_drvinfo.driver field to fit */ #define DRIVER_NAME "xaxienet" @@ -869,6 +869,7 @@ static void axienet_dma_tx_cb(void *data, const struct = dmaengine_result *result) struct netdev_queue *txq; int len; =20 + WRITE_ONCE(lp->tx_irqs, READ_ONCE(lp->tx_irqs) + 1); skbuf_dma =3D axienet_get_tx_desc(lp, lp->tx_ring_tail++); len =3D skbuf_dma->skb->len; txq =3D skb_get_tx_queue(lp->ndev, skbuf_dma->skb); @@ -881,6 +882,17 @@ static void axienet_dma_tx_cb(void *data, const struct= dmaengine_result *result) netif_txq_completed_wake(txq, 1, len, CIRC_SPACE(lp->tx_ring_head, lp->tx_ring_tail, TX_BD_NUM_MAX), 2); + + if (READ_ONCE(lp->tx_dim_enabled)) { + struct dim_sample sample =3D { + .time =3D ktime_get(), + .pkt_ctr =3D u64_stats_read(&lp->tx_packets), + .byte_ctr =3D u64_stats_read(&lp->tx_bytes), + .event_ctr =3D READ_ONCE(lp->tx_irqs), + }; + + net_dim(&lp->tx_dim, &sample); + } } =20 /** @@ -1161,6 +1173,7 @@ static void axienet_dma_rx_cb(void *data, const struc= t dmaengine_result *result) struct sk_buff *skb; u32 *app_metadata; =20 + WRITE_ONCE(lp->rx_irqs, READ_ONCE(lp->rx_irqs) + 1); skbuf_dma =3D axienet_get_rx_desc(lp, lp->rx_ring_tail++); skb =3D skbuf_dma->skb; app_metadata =3D dmaengine_desc_get_metadata_ptr(skbuf_dma->desc, &meta_l= en, @@ -1179,7 +1192,18 @@ static void axienet_dma_rx_cb(void *data, const stru= ct dmaengine_result *result) u64_stats_add(&lp->rx_bytes, rx_len); u64_stats_update_end(&lp->rx_stat_sync); axienet_rx_submit_desc(lp->ndev); + dma_async_issue_pending(lp->rx_chan); + if (READ_ONCE(lp->rx_dim_enabled)) { + struct dim_sample sample =3D { + .time =3D ktime_get(), + .pkt_ctr =3D u64_stats_read(&lp->rx_packets), + .byte_ctr =3D u64_stats_read(&lp->rx_bytes), + .event_ctr =3D READ_ONCE(lp->rx_irqs), + }; + + net_dim(&lp->rx_dim, &sample); + } } =20 /** @@ -1492,6 +1516,9 @@ static void axienet_rx_submit_desc(struct net_device = *ndev) dev_kfree_skb(skb); } =20 +static u32 axienet_dim_coalesce_count_rx(struct axienet_local *lp); +static u32 axienet_dim_coalesce_count_tx(struct axienet_local *lp); + /** * axienet_init_dmaengine - init the dmaengine code. * @ndev: Pointer to net_device structure @@ -1505,6 +1532,7 @@ static int axienet_init_dmaengine(struct net_device *= ndev) { struct axienet_local *lp =3D netdev_priv(ndev); struct skbuf_dma_descriptor *skbuf_dma; + struct dma_slave_config tx_config, rx_config; int i, ret; =20 lp->tx_chan =3D dma_request_chan(lp->dev, "tx_chan0"); @@ -1520,6 +1548,22 @@ static int axienet_init_dmaengine(struct net_device = *ndev) goto err_dma_release_tx; } =20 + tx_config.coalesce_cnt =3D axienet_dim_coalesce_count_tx(lp); + tx_config.coalesce_usecs =3D XAXIDMAENGINE_DFT_TX_USEC; + rx_config.coalesce_cnt =3D axienet_dim_coalesce_count_rx(lp); + rx_config.coalesce_usecs =3D XAXIDMA_DFT_RX_USEC; + + ret =3D dmaengine_slave_config(lp->tx_chan, &tx_config); + if (ret) { + dev_err(lp->dev, "Failed to configure Tx coalesce parameters\n"); + goto err_dma_release_tx; + } + ret =3D dmaengine_slave_config(lp->rx_chan, &rx_config); + if (ret) { + dev_err(lp->dev, "Failed to configure Rx coalesce parameters\n"); + goto err_dma_release_tx; + } + lp->tx_ring_tail =3D 0; lp->tx_ring_head =3D 0; lp->rx_ring_tail =3D 0; @@ -1692,6 +1736,7 @@ static int axienet_open(struct net_device *ndev) free_irq(lp->eth_irq, ndev); err_phy: cancel_work_sync(&lp->rx_dim.work); + cancel_work_sync(&lp->tx_dim.work); cancel_delayed_work_sync(&lp->stats_work); phylink_stop(lp->phylink); phylink_disconnect_phy(lp->phylink); @@ -1722,6 +1767,7 @@ static int axienet_stop(struct net_device *ndev) } =20 cancel_work_sync(&lp->rx_dim.work); + cancel_work_sync(&lp->tx_dim.work); cancel_delayed_work_sync(&lp->stats_work); =20 phylink_stop(lp->phylink); @@ -2104,6 +2150,15 @@ static u32 axienet_dim_coalesce_count_rx(struct axie= net_local *lp) return min(1 << (lp->rx_dim.profile_ix << 1), 255); } =20 +/** + * axienet_dim_coalesce_count_tx() - TX coalesce count for DIM + * @lp: Device private data + */ +static u32 axienet_dim_coalesce_count_tx(struct axienet_local *lp) +{ + return min(1 << (lp->tx_dim.profile_ix << 1), 255); +} + /** * axienet_rx_dim_work() - Adjust RX DIM settings * @work: The work struct @@ -2120,6 +2175,40 @@ static void axienet_rx_dim_work(struct work_struct *= work) lp->rx_dim.state =3D DIM_START_MEASURE; } =20 +/** + * axienet_rx_dim_work_dmaengine() - Adjust RX DIM settings in dmaengine + * @work: The work struct + */ +static void axienet_rx_dim_work_dmaengine(struct work_struct *work) +{ + struct axienet_local *lp =3D + container_of(work, struct axienet_local, rx_dim.work); + struct dma_slave_config cfg =3D { + .coalesce_cnt =3D axienet_dim_coalesce_count_rx(lp), + .coalesce_usecs =3D 16, + }; + + dmaengine_slave_config(lp->rx_chan, &cfg); + lp->rx_dim.state =3D DIM_START_MEASURE; +} + +/** + * axienet_tx_dim_work_dmaengine() - Adjust RX DIM settings in dmaengine + * @work: The work struct + */ +static void axienet_tx_dim_work_dmaengine(struct work_struct *work) +{ + struct axienet_local *lp =3D + container_of(work, struct axienet_local, tx_dim.work); + struct dma_slave_config cfg =3D { + .coalesce_cnt =3D axienet_dim_coalesce_count_tx(lp), + .coalesce_usecs =3D 16, + }; + + dmaengine_slave_config(lp->tx_chan, &cfg); + lp->tx_dim.state =3D DIM_START_MEASURE; +} + /** * axienet_update_coalesce_tx() - Set TX CR * @lp: Device private data @@ -2171,6 +2260,20 @@ axienet_ethtools_get_coalesce(struct net_device *nde= v, u32 cr; =20 ecoalesce->use_adaptive_rx_coalesce =3D lp->rx_dim_enabled; + ecoalesce->use_adaptive_tx_coalesce =3D lp->tx_dim_enabled; + + if (lp->use_dmaengine) { + struct dma_slave_caps tx_caps, rx_caps; + + dma_get_slave_caps(lp->tx_chan, &tx_caps); + dma_get_slave_caps(lp->rx_chan, &rx_caps); + + ecoalesce->tx_max_coalesced_frames =3D tx_caps.coalesce_cnt; + ecoalesce->tx_coalesce_usecs =3D tx_caps.coalesce_usecs; + ecoalesce->rx_max_coalesced_frames =3D rx_caps.coalesce_cnt; + ecoalesce->rx_coalesce_usecs =3D rx_caps.coalesce_usecs; + return 0; + } =20 spin_lock_irq(&lp->rx_cr_lock); cr =3D lp->rx_dma_cr; @@ -2208,8 +2311,10 @@ axienet_ethtools_set_coalesce(struct net_device *nde= v, struct netlink_ext_ack *extack) { struct axienet_local *lp =3D netdev_priv(ndev); - bool new_dim =3D ecoalesce->use_adaptive_rx_coalesce; - bool old_dim =3D lp->rx_dim_enabled; + bool new_rxdim =3D ecoalesce->use_adaptive_rx_coalesce; + bool new_txdim =3D ecoalesce->use_adaptive_tx_coalesce; + bool old_rxdim =3D lp->rx_dim_enabled; + bool old_txdim =3D lp->tx_dim_enabled; u32 cr, mask =3D ~XAXIDMA_CR_RUNSTOP_MASK; =20 if (ecoalesce->rx_max_coalesced_frames > 255 || @@ -2224,20 +2329,76 @@ axienet_ethtools_set_coalesce(struct net_device *nd= ev, return -EINVAL; } =20 - if (((ecoalesce->rx_max_coalesced_frames > 1 || new_dim) && + if (((ecoalesce->rx_max_coalesced_frames > 1 || new_rxdim) && !ecoalesce->rx_coalesce_usecs) || - (ecoalesce->tx_max_coalesced_frames > 1 && + ((ecoalesce->tx_max_coalesced_frames > 1 || new_txdim) && !ecoalesce->tx_coalesce_usecs)) { NL_SET_ERR_MSG(extack, "usecs must be non-zero when frames is greater than one"); return -EINVAL; } =20 - if (new_dim && !old_dim) { + if (lp->use_dmaengine) { + struct dma_slave_config tx_cfg, rx_cfg; + int ret; + + if (new_rxdim && !old_rxdim) { + rx_cfg.coalesce_cnt =3D axienet_dim_coalesce_count_rx(lp); + rx_cfg.coalesce_usecs =3D ecoalesce->rx_coalesce_usecs; + } else if (!new_rxdim) { + if (old_rxdim) { + WRITE_ONCE(lp->rx_dim_enabled, false); + flush_work(&lp->rx_dim.work); + } + + rx_cfg.coalesce_cnt =3D ecoalesce->rx_max_coalesced_frames; + rx_cfg.coalesce_usecs =3D ecoalesce->rx_coalesce_usecs; + } else { + rx_cfg.coalesce_cnt =3D ecoalesce->rx_max_coalesced_frames; + rx_cfg.coalesce_usecs =3D ecoalesce->rx_coalesce_usecs; + } + + if (new_txdim && !old_txdim) { + tx_cfg.coalesce_cnt =3D axienet_dim_coalesce_count_tx(lp); + tx_cfg.coalesce_usecs =3D ecoalesce->tx_coalesce_usecs; + } else if (!new_txdim) { + if (old_txdim) { + WRITE_ONCE(lp->tx_dim_enabled, false); + flush_work(&lp->tx_dim.work); + } + + tx_cfg.coalesce_cnt =3D ecoalesce->tx_max_coalesced_frames; + tx_cfg.coalesce_usecs =3D ecoalesce->tx_coalesce_usecs; + } else { + tx_cfg.coalesce_cnt =3D ecoalesce->tx_max_coalesced_frames; + tx_cfg.coalesce_usecs =3D ecoalesce->tx_coalesce_usecs; + } + + ret =3D dmaengine_slave_config(lp->rx_chan, &rx_cfg); + if (ret) { + NL_SET_ERR_MSG(extack, "failed to set rx coalesce parameters"); + return ret; + } + + if (new_rxdim && !old_rxdim) + WRITE_ONCE(lp->rx_dim_enabled, true); + + ret =3D dmaengine_slave_config(lp->tx_chan, &tx_cfg); + if (ret) { + NL_SET_ERR_MSG(extack, "failed to set tx coalesce parameters"); + return ret; + } + if (new_txdim && !old_txdim) + WRITE_ONCE(lp->tx_dim_enabled, true); + + return 0; + } + + if (new_rxdim && !old_rxdim) { cr =3D axienet_calc_cr(lp, axienet_dim_coalesce_count_rx(lp), ecoalesce->rx_coalesce_usecs); - } else if (!new_dim) { - if (old_dim) { + } else if (!new_rxdim) { + if (old_rxdim) { WRITE_ONCE(lp->rx_dim_enabled, false); napi_synchronize(&lp->napi_rx); flush_work(&lp->rx_dim.work); @@ -2252,7 +2413,7 @@ axienet_ethtools_set_coalesce(struct net_device *ndev, } =20 axienet_update_coalesce_rx(lp, cr, mask); - if (new_dim && !old_dim) + if (new_rxdim && !old_rxdim) WRITE_ONCE(lp->rx_dim_enabled, true); =20 cr =3D axienet_calc_cr(lp, ecoalesce->tx_max_coalesced_frames, @@ -2496,7 +2657,7 @@ axienet_ethtool_get_rmon_stats(struct net_device *dev, static const struct ethtool_ops axienet_ethtool_ops =3D { .supported_coalesce_params =3D ETHTOOL_COALESCE_MAX_FRAMES | ETHTOOL_COALESCE_USECS | - ETHTOOL_COALESCE_USE_ADAPTIVE_RX, + ETHTOOL_COALESCE_USE_ADAPTIVE, .get_drvinfo =3D axienet_ethtools_get_drvinfo, .get_regs_len =3D axienet_ethtools_get_regs_len, .get_regs =3D axienet_ethtools_get_regs, @@ -3041,7 +3202,14 @@ static int axienet_probe(struct platform_device *pde= v) =20 spin_lock_init(&lp->rx_cr_lock); spin_lock_init(&lp->tx_cr_lock); - INIT_WORK(&lp->rx_dim.work, axienet_rx_dim_work); + if (lp->use_dmaengine) { + INIT_WORK(&lp->rx_dim.work, axienet_rx_dim_work_dmaengine); + INIT_WORK(&lp->tx_dim.work, axienet_tx_dim_work_dmaengine); + lp->tx_dim_enabled =3D true; + lp->tx_dim.profile_ix =3D 1; + } else { + INIT_WORK(&lp->rx_dim.work, axienet_rx_dim_work); + } lp->rx_dim_enabled =3D true; lp->rx_dim.profile_ix =3D 1; lp->rx_dma_cr =3D axienet_calc_cr(lp, axienet_dim_coalesce_count_rx(lp), --=20 2.25.1