From nobody Tue Oct 7 11:57:54 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 33F4E288C0A; Thu, 10 Jul 2025 07:19:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.19 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752131986; cv=none; b=M34qn8shR7ElZJdH3kvdEFJ224ROAKT0g6l6hzXot04rTJybxv0cVKNFGrLxeFtb93M4W4eoV6gCMORPAKDJqG1gBZ8VYhPXWwUqhJOhJl2zNzBGRr3Zhy4hqXrymRurqxpnOgM9J580cDRzO3pAK2cmncn6oZB1oPCf+7NDS0Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752131986; c=relaxed/simple; bh=eO42llR5MAMKPH3xJzmuqVCVmJD4rwgy+TanImTIm3c=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=W6d8hjVzacOGiM4keUPoPjIK+LzqdQJ+a2m3eEmnNWz+v4WC+v+eP/zaARO6AG9G44E2B8ImSAZu+NkaFit0auA32judkq1V6XBb1qazpfQ3/cGqQiA4S2ZrNyeynOkc14rKfxYRIvSTs2mbBVmI/T7ROfQTQygCZImZFozEHJQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=U6kOCnN8; arc=none smtp.client-ip=198.175.65.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="U6kOCnN8" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1752131985; x=1783667985; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=eO42llR5MAMKPH3xJzmuqVCVmJD4rwgy+TanImTIm3c=; b=U6kOCnN8467d3U8PW9tQIlL/OPE4YcujW7XEcvjlKs3lpnmhMPSok2+T erRJ/P48UuqmG0xiVS/cRHPLO8byZHs1D1ZC1/0gU9NT35Qy+gSh02X7C 3zrf0dCkBcxq6tB1fRYaomTIXfInmTwNtnk20/exahs9XR9imteaLtoip fI/M4i7lQBm0rrlVT8eMY/7naOkmDnLxl5YgYuHxjlaOAKySm5T2z2GVl cLPvHhrDy2Qi3VL9mkuDEDBOZMhpi9asT8y/kuEhP1Yt0knfPFjTOvIsc KdjfqBrJlA8NaPorwNTNKYbfzOJq+0a2oWnWXBhI9zrkrMBA1NdY1gbE3 A==; X-CSE-ConnectionGUID: Kn7Xp2rlSs2W77LP725+ew== X-CSE-MsgGUID: dPvx8nl2SNy9A7FqwlXCVA== X-IronPort-AV: E=McAfee;i="6800,10657,11489"; a="54256685" X-IronPort-AV: E=Sophos;i="6.16,300,1744095600"; d="scan'208";a="54256685" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Jul 2025 00:19:45 -0700 X-CSE-ConnectionGUID: B/sOHe+/RBeT1WWsvnPKfw== X-CSE-MsgGUID: nGiYzyD4RNKbKq2QGJutCA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,300,1744095600"; d="scan'208";a="160323933" Received: from jraag-z790m-itx-wifi.iind.intel.com ([10.190.239.23]) by orviesa003.jf.intel.com with ESMTP; 10 Jul 2025 00:19:40 -0700 From: Raag Jadav To: lucas.demarchi@intel.com, thomas.hellstrom@linux.intel.com, rodrigo.vivi@intel.com Cc: jarkko.nikula@linux.intel.com, airlied@gmail.com, simona@ffwll.ch, andriy.shevchenko@linux.intel.com, mika.westerberg@linux.intel.com, jsd@semihalf.com, andi.shyti@kernel.org, raag.jadav@intel.com, riana.tauro@intel.com, srinivasa.adatrao@intel.com, michael.j.ruhl@intel.com, intel-xe@lists.freedesktop.org, linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org, Heikki Krogerus , Andi Shyti Subject: [PATCH v7 1/5] i2c: designware: Use polling by default when there is no irq resource Date: Thu, 10 Jul 2025 12:46:08 +0530 Message-Id: <20250710071612.2714990-2-raag.jadav@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250710071612.2714990-1-raag.jadav@intel.com> References: <20250710071612.2714990-1-raag.jadav@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Heikki Krogerus The irq resource itself can be used as a generic way to determine when polling is needed. This not only removes the need for special additional device properties that would soon be needed when the platform may or may not have the irq, but it also removes the need to check the platform in the first place in order to determine is polling needed or not. Signed-off-by: Heikki Krogerus Reviewed-by: Andi Shyti Acked-by: Jarkko Nikula --- drivers/i2c/busses/i2c-designware-platdrv.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/i2c/busses/i2c-designware-platdrv.c b/drivers/i2c/buss= es/i2c-designware-platdrv.c index 879719e91df2..3104f52e32be 100644 --- a/drivers/i2c/busses/i2c-designware-platdrv.c +++ b/drivers/i2c/busses/i2c-designware-platdrv.c @@ -205,25 +205,28 @@ static void i2c_dw_remove_lock_support(struct dw_i2c_= dev *dev) =20 static int dw_i2c_plat_probe(struct platform_device *pdev) { + u32 flags =3D (uintptr_t)device_get_match_data(&pdev->dev); struct device *device =3D &pdev->dev; struct i2c_adapter *adap; struct dw_i2c_dev *dev; int irq, ret; =20 - irq =3D platform_get_irq(pdev, 0); - if (irq < 0) + irq =3D platform_get_irq_optional(pdev, 0); + if (irq =3D=3D -ENXIO) + flags |=3D ACCESS_POLLING; + else if (irq < 0) return irq; =20 dev =3D devm_kzalloc(device, sizeof(*dev), GFP_KERNEL); if (!dev) return -ENOMEM; =20 - dev->flags =3D (uintptr_t)device_get_match_data(device); if (device_property_present(device, "wx,i2c-snps-model")) - dev->flags =3D MODEL_WANGXUN_SP | ACCESS_POLLING; + flags =3D MODEL_WANGXUN_SP | ACCESS_POLLING; =20 dev->dev =3D device; dev->irq =3D irq; + dev->flags =3D flags; platform_set_drvdata(pdev, dev); =20 ret =3D dw_i2c_plat_request_regs(dev); --=20 2.34.1 From nobody Tue Oct 7 11:57:54 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C88E6289340; Thu, 10 Jul 2025 07:19:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.19 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752131992; cv=none; b=ANR30/QYrpf08iCa8Sr/kvvKMVeDYkFXpWAGtqcUwvHCN7NoaPd+jd1EGAD6IYjOEsZ+lg9xwNxZY/4PMzKjtOJISQzYPW2aOaSmZZJDWRLdk0b4qSoZNUogU5i9N1ssjQLahGR0UM1cu8uwKSH4I+KGU28UeC33/M3HxQAD0AQ= ARC-Message-Signature: i=1; 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d="scan'208";a="160323941" Received: from jraag-z790m-itx-wifi.iind.intel.com ([10.190.239.23]) by orviesa003.jf.intel.com with ESMTP; 10 Jul 2025 00:19:45 -0700 From: Raag Jadav To: lucas.demarchi@intel.com, thomas.hellstrom@linux.intel.com, rodrigo.vivi@intel.com Cc: jarkko.nikula@linux.intel.com, airlied@gmail.com, simona@ffwll.ch, andriy.shevchenko@linux.intel.com, mika.westerberg@linux.intel.com, jsd@semihalf.com, andi.shyti@kernel.org, raag.jadav@intel.com, riana.tauro@intel.com, srinivasa.adatrao@intel.com, michael.j.ruhl@intel.com, intel-xe@lists.freedesktop.org, linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org, Heikki Krogerus , Andi Shyti Subject: [PATCH v7 2/5] i2c: designware: Add quirk for Intel Xe Date: Thu, 10 Jul 2025 12:46:09 +0530 Message-Id: <20250710071612.2714990-3-raag.jadav@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250710071612.2714990-1-raag.jadav@intel.com> References: <20250710071612.2714990-1-raag.jadav@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Heikki Krogerus The regmap is coming from the parent also in case of Xe GPUs. Reusing the Wangxun quirk for that. Originally-by: Michael J. Ruhl Signed-off-by: Heikki Krogerus Reviewed-by: Andi Shyti Acked-by: Jarkko Nikula --- drivers/i2c/busses/i2c-designware-platdrv.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/i2c/busses/i2c-designware-platdrv.c b/drivers/i2c/buss= es/i2c-designware-platdrv.c index 3104f52e32be..a35e4c64a1d4 100644 --- a/drivers/i2c/busses/i2c-designware-platdrv.c +++ b/drivers/i2c/busses/i2c-designware-platdrv.c @@ -101,7 +101,7 @@ static int bt1_i2c_request_regs(struct dw_i2c_dev *dev) } #endif =20 -static int txgbe_i2c_request_regs(struct dw_i2c_dev *dev) +static int dw_i2c_get_parent_regmap(struct dw_i2c_dev *dev) { dev->map =3D dev_get_regmap(dev->dev->parent, NULL); if (!dev->map) @@ -123,12 +123,15 @@ static int dw_i2c_plat_request_regs(struct dw_i2c_dev= *dev) struct platform_device *pdev =3D to_platform_device(dev->dev); int ret; =20 + if (device_is_compatible(dev->dev, "intel,xe-i2c")) + return dw_i2c_get_parent_regmap(dev); + switch (dev->flags & MODEL_MASK) { case MODEL_BAIKAL_BT1: ret =3D bt1_i2c_request_regs(dev); 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10 Jul 2025 00:19:51 -0700 From: Raag Jadav To: lucas.demarchi@intel.com, thomas.hellstrom@linux.intel.com, rodrigo.vivi@intel.com Cc: jarkko.nikula@linux.intel.com, airlied@gmail.com, simona@ffwll.ch, andriy.shevchenko@linux.intel.com, mika.westerberg@linux.intel.com, jsd@semihalf.com, andi.shyti@kernel.org, raag.jadav@intel.com, riana.tauro@intel.com, srinivasa.adatrao@intel.com, michael.j.ruhl@intel.com, intel-xe@lists.freedesktop.org, linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org, Heikki Krogerus , Andi Shyti Subject: [PATCH v7 3/5] drm/xe: Support for I2C attached MCUs Date: Thu, 10 Jul 2025 12:46:10 +0530 Message-Id: <20250710071612.2714990-4-raag.jadav@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250710071612.2714990-1-raag.jadav@intel.com> References: <20250710071612.2714990-1-raag.jadav@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Heikki Krogerus Adding adaption/glue layer where the I2C host adapter (Synopsys DesignWare I2C adapter) and the I2C clients (the microcontroller units) are enumerated. The microcontroller units (MCU) that are attached to the GPU depend on the OEM. The initially supported MCU will be the Add-In Management Controller (AMC). Originally-by: Michael J. Ruhl Signed-off-by: Heikki Krogerus Reviewed-by: Rodrigo Vivi Reviewed-by: Andi Shyti Signed-off-by: Raag Jadav --- drivers/gpu/drm/xe/Kconfig | 1 + drivers/gpu/drm/xe/Makefile | 1 + drivers/gpu/drm/xe/regs/xe_i2c_regs.h | 15 ++ drivers/gpu/drm/xe/regs/xe_irq_regs.h | 1 + drivers/gpu/drm/xe/regs/xe_pmt.h | 2 +- drivers/gpu/drm/xe/regs/xe_regs.h | 2 + drivers/gpu/drm/xe/xe_device.c | 5 + drivers/gpu/drm/xe/xe_device_types.h | 4 + drivers/gpu/drm/xe/xe_i2c.c | 300 ++++++++++++++++++++++++++ drivers/gpu/drm/xe/xe_i2c.h | 58 +++++ drivers/gpu/drm/xe/xe_irq.c | 2 + 11 files changed, 390 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/xe/regs/xe_i2c_regs.h create mode 100644 drivers/gpu/drm/xe/xe_i2c.c create mode 100644 drivers/gpu/drm/xe/xe_i2c.h diff --git a/drivers/gpu/drm/xe/Kconfig b/drivers/gpu/drm/xe/Kconfig index f66e6d39e319..2bb2bc052120 100644 --- a/drivers/gpu/drm/xe/Kconfig +++ b/drivers/gpu/drm/xe/Kconfig @@ -45,6 +45,7 @@ config DRM_XE select WANT_DEV_COREDUMP select AUXILIARY_BUS select HMM_MIRROR + select REGMAP if I2C help Driver for Intel Xe2 series GPUs and later. Experimental support for Xe series is also available. diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile index 7c039caefd00..d52cf5808d6f 100644 --- a/drivers/gpu/drm/xe/Makefile +++ b/drivers/gpu/drm/xe/Makefile @@ -125,6 +125,7 @@ xe-y +=3D xe_bb.o \ xe_wait_user_fence.o \ xe_wopcm.o =20 +xe-$(CONFIG_I2C) +=3D xe_i2c.o xe-$(CONFIG_HMM_MIRROR) +=3D xe_hmm.o xe-$(CONFIG_DRM_XE_GPUSVM) +=3D xe_svm.o =20 diff --git a/drivers/gpu/drm/xe/regs/xe_i2c_regs.h b/drivers/gpu/drm/xe/reg= s/xe_i2c_regs.h new file mode 100644 index 000000000000..92dae4487614 --- /dev/null +++ b/drivers/gpu/drm/xe/regs/xe_i2c_regs.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _XE_I2C_REGS_H_ +#define _XE_I2C_REGS_H_ + +#include "xe_reg_defs.h" +#include "xe_regs.h" + +#define I2C_BRIDGE_OFFSET (SOC_BASE + 0xd9000) +#define I2C_CONFIG_SPACE_OFFSET (SOC_BASE + 0xf6000) +#define I2C_MEM_SPACE_OFFSET (SOC_BASE + 0xf7400) + +#define REG_SG_REMAP_ADDR_PREFIX XE_REG(SOC_BASE + 0x0164) +#define REG_SG_REMAP_ADDR_POSTFIX XE_REG(SOC_BASE + 0x0168) + +#endif /* _XE_I2C_REGS_H_ */ diff --git a/drivers/gpu/drm/xe/regs/xe_irq_regs.h b/drivers/gpu/drm/xe/reg= s/xe_irq_regs.h index f0ecfcac4003..13635e4331d4 100644 --- a/drivers/gpu/drm/xe/regs/xe_irq_regs.h +++ b/drivers/gpu/drm/xe/regs/xe_irq_regs.h @@ -19,6 +19,7 @@ #define MASTER_IRQ REG_BIT(31) #define GU_MISC_IRQ REG_BIT(29) #define DISPLAY_IRQ REG_BIT(16) +#define I2C_IRQ REG_BIT(12) #define GT_DW_IRQ(x) REG_BIT(x) =20 /* diff --git a/drivers/gpu/drm/xe/regs/xe_pmt.h b/drivers/gpu/drm/xe/regs/xe_= pmt.h index b0efd9b48d1e..2995d72c3f78 100644 --- a/drivers/gpu/drm/xe/regs/xe_pmt.h +++ b/drivers/gpu/drm/xe/regs/xe_pmt.h @@ -5,7 +5,7 @@ #ifndef _XE_PMT_H_ #define _XE_PMT_H_ =20 -#define SOC_BASE 0x280000 +#include "xe_regs.h" =20 #define BMG_PMT_BASE_OFFSET 0xDB000 #define BMG_DISCOVERY_OFFSET (SOC_BASE + BMG_PMT_BASE_OFFSET) diff --git a/drivers/gpu/drm/xe/regs/xe_regs.h b/drivers/gpu/drm/xe/regs/xe= _regs.h index 3abb17d2ca33..1926b4044314 100644 --- a/drivers/gpu/drm/xe/regs/xe_regs.h +++ b/drivers/gpu/drm/xe/regs/xe_regs.h @@ -7,6 +7,8 @@ =20 #include "regs/xe_reg_defs.h" =20 +#define SOC_BASE 0x280000 + #define GU_CNTL_PROTECTED XE_REG(0x10100C) #define DRIVERINT_FLR_DIS REG_BIT(31) =20 diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c index 0b73cb72bad1..6db09cfc8eb8 100644 --- a/drivers/gpu/drm/xe/xe_device.c +++ b/drivers/gpu/drm/xe/xe_device.c @@ -43,6 +43,7 @@ #include "xe_guc_pc.h" #include "xe_hw_engine_group.h" #include "xe_hwmon.h" +#include "xe_i2c.h" #include "xe_irq.h" #include "xe_mmio.h" #include "xe_module.h" @@ -902,6 +903,10 @@ int xe_device_probe(struct xe_device *xe) if (err) goto err_unregister_display; =20 + err =3D xe_i2c_probe(xe); + if (err) + goto err_unregister_display; + for_each_gt(gt, xe, id) xe_gt_sanitize_freq(gt); =20 diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_d= evice_types.h index 78c4acafd268..decc749fbf70 100644 --- a/drivers/gpu/drm/xe/xe_device_types.h +++ b/drivers/gpu/drm/xe/xe_device_types.h @@ -34,6 +34,7 @@ struct dram_info; struct intel_display; struct intel_dg_nvm_dev; struct xe_ggtt; +struct xe_i2c; struct xe_pat_ops; struct xe_pxp; =20 @@ -585,6 +586,9 @@ struct xe_device { /** @pmu: performance monitoring unit */ struct xe_pmu pmu; =20 + /** @i2c: I2C host controller */ + struct xe_i2c *i2c; + /** @atomic_svm_timeslice_ms: Atomic SVM fault timeslice MS */ u32 atomic_svm_timeslice_ms; =20 diff --git a/drivers/gpu/drm/xe/xe_i2c.c b/drivers/gpu/drm/xe/xe_i2c.c new file mode 100644 index 000000000000..6f05142a8abf --- /dev/null +++ b/drivers/gpu/drm/xe/xe_i2c.c @@ -0,0 +1,300 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Intel Xe I2C attached Microcontroller Units (MCU) + * + * Copyright (C) 2025 Intel Corporation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "regs/xe_i2c_regs.h" +#include "regs/xe_irq_regs.h" + +#include "xe_device.h" +#include "xe_device_types.h" +#include "xe_i2c.h" +#include "xe_mmio.h" +#include "xe_platform_types.h" + +/** + * DOC: Xe I2C devices + * + * Register a platform device for the I2C host controller (Synpsys DesignW= are + * I2C) if the registers of that controller are mapped to the MMIO, and al= so the + * I2C client device for the Add-In Management Controller (the MCU) attach= ed to + * the host controller. + * + * See drivers/i2c/busses/i2c-designware-* for more information on the I2C= host + * controller. + */ + +static const char adapter_name[] =3D "i2c_designware"; + +static const struct property_entry xe_i2c_adapter_properties[] =3D { + PROPERTY_ENTRY_STRING("compatible", "intel,xe-i2c"), + PROPERTY_ENTRY_U32("clock-frequency", I2C_MAX_FAST_MODE_PLUS_FREQ), + { } +}; + +static inline void xe_i2c_read_endpoint(struct xe_mmio *mmio, void *ep) +{ + u32 *val =3D ep; + + val[0] =3D xe_mmio_read32(mmio, REG_SG_REMAP_ADDR_PREFIX); + val[1] =3D xe_mmio_read32(mmio, REG_SG_REMAP_ADDR_POSTFIX); +} + +static void xe_i2c_client_work(struct work_struct *work) +{ + struct xe_i2c *i2c =3D container_of(work, struct xe_i2c, work); + struct i2c_board_info info =3D { + .type =3D "amc", + .flags =3D I2C_CLIENT_HOST_NOTIFY, + .addr =3D i2c->ep.addr[1], + }; + + i2c->client[0] =3D i2c_new_client_device(i2c->adapter, &info); +} + +static int xe_i2c_notifier(struct notifier_block *nb, unsigned long action= , void *data) +{ + struct xe_i2c *i2c =3D container_of(nb, struct xe_i2c, bus_notifier); + struct i2c_adapter *adapter =3D i2c_verify_adapter(data); + struct device *dev =3D data; + + if (action =3D=3D BUS_NOTIFY_ADD_DEVICE && + adapter && dev->parent =3D=3D &i2c->pdev->dev) { + i2c->adapter =3D adapter; + schedule_work(&i2c->work); + return NOTIFY_OK; + } + + return NOTIFY_DONE; +} + +static int xe_i2c_register_adapter(struct xe_i2c *i2c) +{ + struct pci_dev *pci =3D to_pci_dev(i2c->drm_dev); + struct platform_device *pdev; + struct fwnode_handle *fwnode; + int ret; + + fwnode =3D fwnode_create_software_node(xe_i2c_adapter_properties, NULL); + if (!fwnode) + return -ENOMEM; + + /* + * Not using platform_device_register_full() here because we don't have + * a handle to the platform_device before it returns. xe_i2c_notifier() + * uses that handle, but it may be called before + * platform_device_register_full() is done. + */ + pdev =3D platform_device_alloc(adapter_name, pci_dev_id(pci)); + if (!pdev) { + ret =3D -ENOMEM; + goto err_fwnode_remove; + } + + if (i2c->adapter_irq) { + struct resource res; + + res =3D DEFINE_RES_IRQ_NAMED(i2c->adapter_irq, "xe_i2c"); + + ret =3D platform_device_add_resources(pdev, &res, 1); + if (ret) + goto err_pdev_put; + } + + pdev->dev.parent =3D i2c->drm_dev; + pdev->dev.fwnode =3D fwnode; + i2c->adapter_node =3D fwnode; + i2c->pdev =3D pdev; + + ret =3D platform_device_add(pdev); + if (ret) + goto err_pdev_put; + + return 0; + +err_pdev_put: + platform_device_put(pdev); +err_fwnode_remove: + fwnode_remove_software_node(fwnode); + + return ret; +} + +static void xe_i2c_unregister_adapter(struct xe_i2c *i2c) +{ + platform_device_unregister(i2c->pdev); + fwnode_remove_software_node(i2c->adapter_node); +} + +/** + * xe_i2c_irq_handler: Handler for I2C interrupts + * @xe: xe device instance + * @master_ctl: interrupt register + * + * Forward interrupts generated by the I2C host adapter to the I2C host ad= apter + * driver. + */ +void xe_i2c_irq_handler(struct xe_device *xe, u32 master_ctl) +{ + if (!xe->i2c || !xe->i2c->adapter_irq) + return; + + if (master_ctl & I2C_IRQ) + generic_handle_irq_safe(xe->i2c->adapter_irq); +} + +static int xe_i2c_irq_map(struct irq_domain *h, unsigned int virq, + irq_hw_number_t hw_irq_num) +{ + irq_set_chip_and_handler(virq, &dummy_irq_chip, handle_simple_irq); + return 0; +} + +static const struct irq_domain_ops xe_i2c_irq_ops =3D { + .map =3D xe_i2c_irq_map, +}; + +static int xe_i2c_create_irq(struct xe_i2c *i2c) +{ + struct irq_domain *domain; + + if (!(i2c->ep.capabilities & XE_I2C_EP_CAP_IRQ)) + return 0; + + domain =3D irq_domain_create_linear(dev_fwnode(i2c->drm_dev), 1, &xe_i2c_= irq_ops, NULL); + if (!domain) + return -ENOMEM; + + i2c->adapter_irq =3D irq_create_mapping(domain, 0); + i2c->irqdomain =3D domain; + + return 0; +} + +static void xe_i2c_remove_irq(struct xe_i2c *i2c) +{ + if (!i2c->irqdomain) + return; + + irq_dispose_mapping(i2c->adapter_irq); + irq_domain_remove(i2c->irqdomain); +} + +static int xe_i2c_read(void *context, unsigned int reg, unsigned int *val) +{ + struct xe_i2c *i2c =3D context; + + *val =3D xe_mmio_read32(i2c->mmio, XE_REG(reg + I2C_MEM_SPACE_OFFSET)); + + return 0; +} + +static int xe_i2c_write(void *context, unsigned int reg, unsigned int val) +{ + struct xe_i2c *i2c =3D context; + + xe_mmio_write32(i2c->mmio, XE_REG(reg + I2C_MEM_SPACE_OFFSET), val); + + return 0; +} + +static const struct regmap_config i2c_regmap_config =3D { + .reg_bits =3D 32, + .val_bits =3D 32, + .reg_read =3D xe_i2c_read, + .reg_write =3D xe_i2c_write, + .fast_io =3D true, +}; + +static void xe_i2c_remove(void *data) +{ + struct xe_i2c *i2c =3D data; + unsigned int i; + + for (i =3D 0; i < XE_I2C_MAX_CLIENTS; i++) + i2c_unregister_device(i2c->client[i]); + + bus_unregister_notifier(&i2c_bus_type, &i2c->bus_notifier); + xe_i2c_unregister_adapter(i2c); + xe_i2c_remove_irq(i2c); +} + +/** + * xe_i2c_probe: Probe the I2C host adapter and the I2C clients attached t= o it + * @xe: xe device instance + * + * Register all the I2C devices described in the I2C Endpoint data structu= re. + * + * Return: 0 on success, error code on failure + */ +int xe_i2c_probe(struct xe_device *xe) +{ + struct device *drm_dev =3D xe->drm.dev; + struct xe_i2c_endpoint ep; + struct regmap *regmap; + struct xe_i2c *i2c; + int ret; + + if (xe->info.platform !=3D XE_BATTLEMAGE) + return 0; + + xe_i2c_read_endpoint(xe_root_tile_mmio(xe), &ep); + if (ep.cookie !=3D XE_I2C_EP_COOKIE_DEVICE) + return 0; + + i2c =3D devm_kzalloc(drm_dev, sizeof(*i2c), GFP_KERNEL); + if (!i2c) + return -ENOMEM; + + INIT_WORK(&i2c->work, xe_i2c_client_work); + i2c->mmio =3D xe_root_tile_mmio(xe); + i2c->drm_dev =3D drm_dev; + i2c->ep =3D ep; + + regmap =3D devm_regmap_init(drm_dev, NULL, i2c, &i2c_regmap_config); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + i2c->bus_notifier.notifier_call =3D xe_i2c_notifier; + ret =3D bus_register_notifier(&i2c_bus_type, &i2c->bus_notifier); + if (ret) + return ret; + + ret =3D xe_i2c_create_irq(i2c); + if (ret) + goto err_unregister_notifier; + + ret =3D xe_i2c_register_adapter(i2c); + if (ret) + goto err_remove_irq; + + return devm_add_action_or_reset(drm_dev, xe_i2c_remove, i2c); + +err_remove_irq: + xe_i2c_remove_irq(i2c); + +err_unregister_notifier: + bus_unregister_notifier(&i2c_bus_type, &i2c->bus_notifier); + + return ret; +} diff --git a/drivers/gpu/drm/xe/xe_i2c.h b/drivers/gpu/drm/xe/xe_i2c.h new file mode 100644 index 000000000000..7ea40f4e4aa4 --- /dev/null +++ b/drivers/gpu/drm/xe/xe_i2c.h @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _XE_I2C_H_ +#define _XE_I2C_H_ + +#include +#include +#include +#include + +struct device; +struct fwnode_handle; +struct i2c_adapter; +struct i2c_client; +struct irq_domain; +struct platform_device; +struct xe_device; +struct xe_mmio; + +#define XE_I2C_MAX_CLIENTS 3 + +#define XE_I2C_EP_COOKIE_DEVICE 0xde + +/* Endpoint Capabilities */ +#define XE_I2C_EP_CAP_IRQ BIT(0) + +struct xe_i2c_endpoint { + u8 cookie; + u8 capabilities; + u16 addr[XE_I2C_MAX_CLIENTS]; +}; + +struct xe_i2c { + struct fwnode_handle *adapter_node; + struct platform_device *pdev; + struct i2c_adapter *adapter; + struct i2c_client *client[XE_I2C_MAX_CLIENTS]; + + struct notifier_block bus_notifier; + struct work_struct work; + + struct irq_domain *irqdomain; + int adapter_irq; + + struct xe_i2c_endpoint ep; + struct device *drm_dev; + + struct xe_mmio *mmio; +}; + +#if IS_ENABLED(CONFIG_I2C) +int xe_i2c_probe(struct xe_device *xe); +void xe_i2c_irq_handler(struct xe_device *xe, u32 master_ctl); +#else +static inline int xe_i2c_probe(struct xe_device *xe) { return 0; } +static inline void xe_i2c_irq_handler(struct xe_device *xe, u32 master_ctl= ) { } +#endif + +#endif diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c index 5362d3174b06..c43e62dc692e 100644 --- a/drivers/gpu/drm/xe/xe_irq.c +++ b/drivers/gpu/drm/xe/xe_irq.c @@ -18,6 +18,7 @@ #include "xe_gt.h" #include "xe_guc.h" #include "xe_hw_engine.h" +#include "xe_i2c.h" #include "xe_memirq.h" #include "xe_mmio.h" #include "xe_pxp.h" @@ -476,6 +477,7 @@ static irqreturn_t dg1_irq_handler(int irq, void *arg) if (xe->info.has_heci_cscfi) xe_heci_csc_irq_handler(xe, master_ctl); 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10 Jul 2025 00:19:57 -0700 From: Raag Jadav To: lucas.demarchi@intel.com, thomas.hellstrom@linux.intel.com, rodrigo.vivi@intel.com Cc: jarkko.nikula@linux.intel.com, airlied@gmail.com, simona@ffwll.ch, andriy.shevchenko@linux.intel.com, mika.westerberg@linux.intel.com, jsd@semihalf.com, andi.shyti@kernel.org, raag.jadav@intel.com, riana.tauro@intel.com, srinivasa.adatrao@intel.com, michael.j.ruhl@intel.com, intel-xe@lists.freedesktop.org, linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org, Heikki Krogerus , Karthik Poosa , Andi Shyti Subject: [PATCH v7 4/5] drm/xe/pm: Wire up suspend/resume for I2C controller Date: Thu, 10 Jul 2025 12:46:11 +0530 Message-Id: <20250710071612.2714990-5-raag.jadav@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250710071612.2714990-1-raag.jadav@intel.com> References: <20250710071612.2714990-1-raag.jadav@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Wire up suspend/resume handles for I2C controller to match its power state with SGUnit. Signed-off-by: Raag Jadav Signed-off-by: Heikki Krogerus Reviewed-by: Karthik Poosa Reviewed-by: Andi Shyti --- drivers/gpu/drm/xe/regs/xe_i2c_regs.h | 5 +++++ drivers/gpu/drm/xe/xe_i2c.c | 29 +++++++++++++++++++++++++++ drivers/gpu/drm/xe/xe_i2c.h | 4 ++++ drivers/gpu/drm/xe/xe_pm.c | 9 +++++++++ 4 files changed, 47 insertions(+) diff --git a/drivers/gpu/drm/xe/regs/xe_i2c_regs.h b/drivers/gpu/drm/xe/reg= s/xe_i2c_regs.h index 92dae4487614..af781c8e4a80 100644 --- a/drivers/gpu/drm/xe/regs/xe_i2c_regs.h +++ b/drivers/gpu/drm/xe/regs/xe_i2c_regs.h @@ -2,6 +2,8 @@ #ifndef _XE_I2C_REGS_H_ #define _XE_I2C_REGS_H_ =20 +#include + #include "xe_reg_defs.h" #include "xe_regs.h" =20 @@ -12,4 +14,7 @@ #define REG_SG_REMAP_ADDR_PREFIX XE_REG(SOC_BASE + 0x0164) #define REG_SG_REMAP_ADDR_POSTFIX XE_REG(SOC_BASE + 0x0168) =20 +#define I2C_CONFIG_CMD XE_REG(I2C_CONFIG_SPACE_OFFSET + PCI_COMMAND) +#define I2C_CONFIG_PMCSR XE_REG(I2C_CONFIG_SPACE_OFFSET + 0x84) + #endif /* _XE_I2C_REGS_H_ */ diff --git a/drivers/gpu/drm/xe/xe_i2c.c b/drivers/gpu/drm/xe/xe_i2c.c index 6f05142a8abf..db9c0340be5c 100644 --- a/drivers/gpu/drm/xe/xe_i2c.c +++ b/drivers/gpu/drm/xe/xe_i2c.c @@ -226,6 +226,31 @@ static const struct regmap_config i2c_regmap_config = =3D { .fast_io =3D true, }; =20 +void xe_i2c_pm_suspend(struct xe_device *xe) +{ + struct xe_mmio *mmio =3D xe_root_tile_mmio(xe); + + if (!xe->i2c || xe->i2c->ep.cookie !=3D XE_I2C_EP_COOKIE_DEVICE) + return; + + xe_mmio_rmw32(mmio, I2C_CONFIG_PMCSR, PCI_PM_CTRL_STATE_MASK, (__force u3= 2)PCI_D3hot); + drm_dbg(&xe->drm, "pmcsr: 0x%08x\n", xe_mmio_read32(mmio, I2C_CONFIG_PMCS= R)); +} + +void xe_i2c_pm_resume(struct xe_device *xe, bool d3cold) +{ + struct xe_mmio *mmio =3D xe_root_tile_mmio(xe); + + if (!xe->i2c || xe->i2c->ep.cookie !=3D XE_I2C_EP_COOKIE_DEVICE) + return; + + if (d3cold) + xe_mmio_rmw32(mmio, I2C_CONFIG_CMD, 0, PCI_COMMAND_MEMORY); + + xe_mmio_rmw32(mmio, I2C_CONFIG_PMCSR, PCI_PM_CTRL_STATE_MASK, (__force u3= 2)PCI_D0); + drm_dbg(&xe->drm, "pmcsr: 0x%08x\n", xe_mmio_read32(mmio, I2C_CONFIG_PMCS= R)); +} + static void xe_i2c_remove(void *data) { struct xe_i2c *i2c =3D data; @@ -270,6 +295,10 @@ int xe_i2c_probe(struct xe_device *xe) i2c->mmio =3D xe_root_tile_mmio(xe); i2c->drm_dev =3D drm_dev; i2c->ep =3D ep; + xe->i2c =3D i2c; + + /* PCI PM isn't aware of this device, bring it up and match it with SGUni= t state. */ + xe_i2c_pm_resume(xe, true); =20 regmap =3D devm_regmap_init(drm_dev, NULL, i2c, &i2c_regmap_config); if (IS_ERR(regmap)) diff --git a/drivers/gpu/drm/xe/xe_i2c.h b/drivers/gpu/drm/xe/xe_i2c.h index 7ea40f4e4aa4..b767ed8ce52b 100644 --- a/drivers/gpu/drm/xe/xe_i2c.h +++ b/drivers/gpu/drm/xe/xe_i2c.h @@ -50,9 +50,13 @@ struct xe_i2c { #if IS_ENABLED(CONFIG_I2C) int xe_i2c_probe(struct xe_device *xe); void xe_i2c_irq_handler(struct xe_device *xe, u32 master_ctl); +void xe_i2c_pm_suspend(struct xe_device *xe); +void xe_i2c_pm_resume(struct xe_device *xe, bool d3cold); #else static inline int xe_i2c_probe(struct xe_device *xe) { return 0; } static inline void xe_i2c_irq_handler(struct xe_device *xe, u32 master_ctl= ) { } +static inline void xe_i2c_pm_suspend(struct xe_device *xe) { } +static inline void xe_i2c_pm_resume(struct xe_device *xe, bool d3cold) { } #endif =20 #endif diff --git a/drivers/gpu/drm/xe/xe_pm.c b/drivers/gpu/drm/xe/xe_pm.c index bcfda545e74f..f171a91b849c 100644 --- a/drivers/gpu/drm/xe/xe_pm.c +++ b/drivers/gpu/drm/xe/xe_pm.c @@ -19,6 +19,7 @@ #include "xe_ggtt.h" #include "xe_gt.h" #include "xe_guc.h" +#include "xe_i2c.h" #include "xe_irq.h" #include "xe_pcode.h" #include "xe_pxp.h" @@ -146,6 +147,8 @@ int xe_pm_suspend(struct xe_device *xe) =20 xe_display_pm_suspend_late(xe); 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a="54256746" X-IronPort-AV: E=Sophos;i="6.16,300,1744095600"; d="scan'208";a="54256746" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Jul 2025 00:20:08 -0700 X-CSE-ConnectionGUID: wxyUNwkBSaqM6p7EKD6arQ== X-CSE-MsgGUID: c534Jed4S+e0kQ6Jkn6abQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,300,1744095600"; d="scan'208";a="160324007" Received: from jraag-z790m-itx-wifi.iind.intel.com ([10.190.239.23]) by orviesa003.jf.intel.com with ESMTP; 10 Jul 2025 00:20:03 -0700 From: Raag Jadav To: lucas.demarchi@intel.com, thomas.hellstrom@linux.intel.com, rodrigo.vivi@intel.com Cc: jarkko.nikula@linux.intel.com, airlied@gmail.com, simona@ffwll.ch, andriy.shevchenko@linux.intel.com, mika.westerberg@linux.intel.com, jsd@semihalf.com, andi.shyti@kernel.org, raag.jadav@intel.com, riana.tauro@intel.com, srinivasa.adatrao@intel.com, michael.j.ruhl@intel.com, intel-xe@lists.freedesktop.org, linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org, Heikki Krogerus , Andi Shyti Subject: [PATCH v7 5/5] drm/xe/xe_i2c: Add support for i2c in survivability mode Date: Thu, 10 Jul 2025 12:46:12 +0530 Message-Id: <20250710071612.2714990-6-raag.jadav@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250710071612.2714990-1-raag.jadav@intel.com> References: <20250710071612.2714990-1-raag.jadav@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Riana Tauro Initialize i2c in survivability mode to allow firmware update of Add-In Management Controller (AMC) in survivability mode. Signed-off-by: Riana Tauro Signed-off-by: Heikki Krogerus Reviewed-by: Raag Jadav Reviewed-by: Andi Shyti --- drivers/gpu/drm/xe/xe_survivability_mode.c | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/xe/xe_survivability_mode.c b/drivers/gpu/drm/x= e/xe_survivability_mode.c index 1f710b3fc599..41705f5d52e3 100644 --- a/drivers/gpu/drm/xe/xe_survivability_mode.c +++ b/drivers/gpu/drm/xe/xe_survivability_mode.c @@ -14,6 +14,7 @@ #include "xe_device.h" #include "xe_gt.h" #include "xe_heci_gsc.h" +#include "xe_i2c.h" #include "xe_mmio.h" #include "xe_pcode_api.h" #include "xe_vsec.h" @@ -173,20 +174,22 @@ static int enable_survivability_mode(struct pci_dev *= pdev) survivability->mode =3D true; =20 ret =3D xe_heci_gsc_init(xe); - if (ret) { - /* - * But if it fails, device can't enter survivability - * so move it back for correct error handling - */ - survivability->mode =3D false; - return ret; - } + if (ret) + goto err; =20 xe_vsec_init(xe); =20 + ret =3D xe_i2c_probe(xe); + if (ret) + goto err; + dev_err(dev, "In Survivability Mode\n"); =20 return 0; + +err: + survivability->mode =3D false; + return ret; } =20 /** --=20 2.34.1