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(ksk4725@coasia.com@115.23.218.194) by 192.168.10.159 with ESMTP; 10 Jul 2025 09:21:05 +0900 X-Original-SENDERIP: 115.23.218.194 X-Original-SENDERCOUNTRY: KR, South Korea X-Original-MAILFROM: ksk4725@coasia.com X-Original-RCPTTO: jesper.nilsson@axis.com, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, krzk@kernel.org, s.nawrocki@samsung.com, cw00.choi@samsung.com, alim.akhtar@samsung.com, linus.walleij@linaro.org, tomasz.figa@gmail.com, catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de, ravi.patel@samsung.com, ksk4725@coasia.com, smn1196@coasia.com, kenkim@coasia.com, pjsin865@coasia.com, gwk1013@coasia.com, hgkim05@coasia.com, mingyoungbo@coasia.com, pankaj.dubey@samsung.com, shradha.t@samsung.com, inbaraj.e@samsung.com, swathi.ks@samsung.com, hrishikesh.d@samsung.com, dj76.yang@samsung.com, hypmean.kim@samsung.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@axis.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, soc@lists.linux.dev From: ksk4725@coasia.com To: Jesper Nilsson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krzysztof Kozlowski , Sylwester Nawrocki , Chanwoo Choi , Alim Akhtar , Linus Walleij , Tomasz Figa , Catalin Marinas , Will Deacon , Arnd Bergmann , Ravi Patel , SeonGu Kang , SungMin Park Cc: kenkim , Jongshin Park , GunWoo Kim , HaGyeong Kim , GyoungBo Min , Pankaj Dubey , Shradha Todi , Inbaraj E , Swathi K S , Hrishikesh , Dongjin Yang , Sang Min Kim , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@axis.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, soc@lists.linux.dev Subject: [PATCH 14/16] arm64: dts: axis: Add initial device tree support Date: Thu, 10 Jul 2025 09:20:44 +0900 Message-Id: <20250710002047.1573841-15-ksk4725@coasia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250710002047.1573841-1-ksk4725@coasia.com> References: <20250710002047.1573841-1-ksk4725@coasia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: sungminpark Add initial device tree support for Axis ARTPEC-8 SoC and Grizzly board. This SoC contains four cores of cortex-a53 CPUs and other various peripheral IPs. Signed-off-by: Ravi Patel Signed-off-by: sungminpark --- MAINTAINERS | 14 ++ arch/arm64/Kconfig.platforms | 13 + arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/axis/Makefile | 4 + arch/arm64/boot/dts/axis/artpec8-grizzly.dts | 67 +++++ arch/arm64/boot/dts/axis/artpec8.dtsi | 252 +++++++++++++++++++ 6 files changed, 351 insertions(+) create mode 100644 arch/arm64/boot/dts/axis/Makefile create mode 100644 arch/arm64/boot/dts/axis/artpec8-grizzly.dts create mode 100644 arch/arm64/boot/dts/axis/artpec8.dtsi diff --git a/MAINTAINERS b/MAINTAINERS index fa1e04e87d1d..371005f3f41a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2320,6 +2320,20 @@ F: drivers/crypto/axis F: drivers/mmc/host/usdhi6rol0.c F: drivers/pinctrl/pinctrl-artpec* =20 +ARM/ARTPEC ARM64 MACHINE SUPPORT +M: Jesper Nilsson +M: Ravi Patel +M: SeonGu Kang +M: SungMin Park +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) +L: linux-samsung-soc@vger.kernel.org +L: linux-arm-kernel@axis.com +S: Maintained +F: Documentation/devicetree/bindings/clock/axis,artpec*-clock.yaml +F: arch/arm64/boot/dts/axis/ +F: drivers/clk/samsung/clk-artpec*.c +F: include/dt-bindings/clock/axis,artpec*-clk.h + ARM/ASPEED I2C DRIVER M: Ryan Chen R: Benjamin Herrenschmidt diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 8b76821f190f..418ee47227c1 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -40,6 +40,19 @@ config ARCH_APPLE This enables support for Apple's in-house ARM SoC family, such as the Apple M1. =20 +config ARCH_ARTPEC + bool "Axis Communications ARTPEC SoC Family" + help + This enables support for the ARMv8 based ARTPEC SoC Family. + +config ARCH_ARTPEC8 + bool "Axis ARTPEC-8 SoC Platform" + depends on ARCH_ARTPEC + depends on ARCH_EXYNOS + select ARM_GIC + help + This enables support for the Axis ARTPEC-8 SoC. + menuconfig ARCH_BCM bool "Broadcom SoC Support" =20 diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile index 79b73a21ddc2..6b6a3aedc2ed 100644 --- a/arch/arm64/boot/dts/Makefile +++ b/arch/arm64/boot/dts/Makefile @@ -9,6 +9,7 @@ subdir-y +=3D amlogic subdir-y +=3D apm subdir-y +=3D apple subdir-y +=3D arm +subdir-y +=3D axis subdir-y +=3D bitmain subdir-y +=3D blaize subdir-y +=3D broadcom diff --git a/arch/arm64/boot/dts/axis/Makefile b/arch/arm64/boot/dts/axis/M= akefile new file mode 100644 index 000000000000..ccf00de64016 --- /dev/null +++ b/arch/arm64/boot/dts/axis/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 + +dtb-$(CONFIG_ARCH_ARTPEC) +=3D \ + artpec8-grizzly.dtb diff --git a/arch/arm64/boot/dts/axis/artpec8-grizzly.dts b/arch/arm64/boot= /dts/axis/artpec8-grizzly.dts new file mode 100644 index 000000000000..7671130a0333 --- /dev/null +++ b/arch/arm64/boot/dts/axis/artpec8-grizzly.dts @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Axis ARTPEC-8 Grizzly board device tree source + * + * Copyright (c) 2022-2025 Samsung Electronics Co., Ltd. + * https://www.samsung.com + * Copyright (c) 2022-2025 Axis Communications AB. + * https://www.axis.com + */ + +/dts-v1/; +#include "artpec8.dtsi" +#include +/ { + model =3D "ARTPEC-8 grizzly board"; + compatible =3D "axis,artpec8-grizzly", "axis,artpec8"; + + aliases { + serial0 =3D &serial_0; + }; + + chosen { + stdout-path =3D &serial_0; + }; + + memory@80000000 { + device_type =3D "memory"; + reg =3D <0x0 0x80000000 0x0 0x80000000>; + }; +}; + +&osc_clk { + clock-frequency =3D <50000000>; + status =3D "okay"; +}; + +&serial_0 { + status =3D "okay"; +}; + +&cmu_cmu { + status =3D "okay"; +}; + +&cmu_bus { + status =3D "okay"; +}; + +&cmu_core { + status =3D "okay"; +}; + +&cmu_cpucl { + status =3D "okay"; +}; + +&cmu_fsys { + status =3D "okay"; +}; + +&cmu_imem { + status =3D "okay"; +}; + +&cmu_peri { + status =3D "okay"; +}; diff --git a/arch/arm64/boot/dts/axis/artpec8.dtsi b/arch/arm64/boot/dts/ax= is/artpec8.dtsi new file mode 100644 index 000000000000..296192560adf --- /dev/null +++ b/arch/arm64/boot/dts/axis/artpec8.dtsi @@ -0,0 +1,252 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Axis ARTPEC-8 SoC device tree source + * + * Copyright (c) 2022-2025 Samsung Electronics Co., Ltd. + * https://www.samsung.com + * Copyright (c) 2022-2025 Axis Communications AB. + * https://www.axis.com + */ + +#include +#include + +/ { + compatible =3D "axis,artpec8"; + interrupt-parent =3D <&gic>; + #address-cells =3D <2>; + #size-cells =3D <2>; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu0: cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x0>; + cpu-idle-states =3D <&cpu_sleep>; + enable-method =3D "psci"; + clocks =3D <&cmu_cpucl DOUT_CLK_CPUCL_CPU>; + clock-names =3D "dout_clk_cpucl_cpu"; + clock-frequency =3D <1200000000>; + }; + + cpu1: cpu@1 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x1>; + cpu-idle-states =3D <&cpu_sleep>; + enable-method =3D "psci"; + clock-frequency =3D <1200000000>; + }; + + cpu2: cpu@2 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x2>; + cpu-idle-states =3D <&cpu_sleep>; + enable-method =3D "psci"; + clock-frequency =3D <1200000000>; + }; + + cpu3: cpu@3 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x3>; + cpu-idle-states =3D <&cpu_sleep>; + enable-method =3D "psci"; + clock-frequency =3D <1200000000>; + }; + + idle-states { + entry-method =3D "psci"; + + cpu_sleep: cpu-sleep { + compatible =3D "arm,idle-state"; + arm,psci-suspend-param =3D <0x0010000>; + local-timer-stop; + entry-latency-us =3D <300>; + exit-latency-us =3D <1200>; + min-residency-us =3D <2000>; + }; + }; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupts =3D , + , + , + ; + }; + + pmu { + compatible =3D "arm,cortex-a53-pmu"; + interrupts =3D , + , + , + ; + interrupt-affinity =3D <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + + psci { + compatible =3D "arm,psci-0.2"; + method =3D "smc"; + }; + + osc_clk: xxti { + compatible =3D "fixed-clock"; + clock-output-names =3D "xxti"; + #clock-cells =3D <0>; + }; + + fin_pll: fin_pll { + compatible =3D "fixed-factor-clock"; + clocks =3D <&osc_clk>; + #clock-cells =3D <0>; + clock-div =3D <2>; + clock-mult =3D <1>; + clock-output-names =3D "fin_pll"; + }; + + soc: soc@0 { + compatible =3D "simple-bus"; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x0 0x0 0x0 0x17000000>; + + mct@10040000 { + compatible =3D "samsung,exynos4210-mct"; + reg =3D <0x10040000 0x1000>; + clocks =3D <&fin_pll>, <&cmu_imem MOUT_IMEM_ACLK_USER>; + clock-names =3D "fin_pll", "mct"; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + ; + }; + + gic: interrupt-controller@10201000 { + compatible =3D "arm,gic-400"; + #interrupt-cells =3D <3>; + #address-cells =3D <0>; + interrupt-controller; + reg =3D <0x10201000 0x00001000>, + <0x10202000 0x00002000>, + <0x10204000 0x00002000>, + <0x10206000 0x00002000>; + }; + + cmu_cmu: clock-controller@12400000 { + compatible =3D "axis,artpec8-cmu-cmu"; + reg =3D <0x12400000 0x4000>; + #clock-cells =3D <1>; + clocks =3D <&fin_pll>; + clock-names =3D "fin_pll"; + status =3D "disabled"; + }; + + cmu_bus: clock-controller@12c10000 { + compatible =3D "axis,artpec8-cmu-bus"; + reg =3D <0x12c10000 0x4000>; + #clock-cells =3D <1>; + clocks =3D <&fin_pll>, + <&cmu_cmu DOUT_CLKCMU_BUS_BUS>, + <&cmu_cmu DOUT_CLKCMU_BUS_DLP>; + clock-names =3D "fin_pll", + "dout_clkcmu_bus_bus", + "dout_clkcmu_bus_dlp"; + status =3D "disabled"; + }; + + cmu_core: clock-controller@12410000 { + compatible =3D "axis,artpec8-cmu-core"; + reg =3D <0x12410000 0x4000>; + #clock-cells =3D <1>; + clocks =3D <&fin_pll>, + <&cmu_cmu DOUT_CLKCMU_CORE_MAIN>, + <&cmu_cmu DOUT_CLKCMU_CORE_DLP>; + clock-names =3D "fin_pll", + "dout_clkcmu_core_main", + "dout_clkcmu_core_dlp"; + status =3D "disabled"; + }; + + cmu_cpucl: clock-controller@11410000 { + compatible =3D "axis,artpec8-cmu-cpucl"; + reg =3D <0x11410000 0x4000>; + #clock-cells =3D <1>; + clocks =3D <&fin_pll>, + <&cmu_cmu DOUT_CLKCMU_CPUCL_SWITCH>; + clock-names =3D "fin_pll", + "dout_clkcmu_cpucl_switch"; + status =3D "disabled"; + }; + + cmu_fsys: clock-controller@16c10000 { + compatible =3D "axis,artpec8-cmu-fsys"; + reg =3D <0x16c10000 0x4000>; + #clock-cells =3D <1>; + clocks =3D <&fin_pll>, + <&cmu_cmu DOUT_CLKCMU_FSYS_SCAN0>, + <&cmu_cmu DOUT_CLKCMU_FSYS_SCAN1>, + <&cmu_cmu DOUT_CLKCMU_FSYS_BUS>, + <&cmu_cmu DOUT_CLKCMU_FSYS_IP>; + clock-names =3D "fin_pll", + "dout_clkcmu_fsys_scan0", + "dout_clkcmu_fsys_scan1", + "dout_clkcmu_fsys_bus", + "dout_clkcmu_fsys_ip"; + status =3D "disabled"; + }; + + cmu_imem: clock-controller@10010000 { + compatible =3D "axis,artpec8-cmu-imem"; + reg =3D <0x10010000 0x4000>; + #clock-cells =3D <1>; + clocks =3D <&fin_pll>, + <&cmu_cmu DOUT_CLKCMU_IMEM_ACLK>, + <&cmu_cmu DOUT_CLKCMU_IMEM_JPEG>; + clock-names =3D "fin_pll", + "dout_clkcmu_imem_aclk", + "dout_clkcmu_imem_jpeg"; + status =3D "disabled"; + }; + + cmu_peri: clock-controller@16410000 { + compatible =3D "axis,artpec8-cmu-peri"; + reg =3D <0x16410000 0x4000>; + #clock-cells =3D <1>; + clocks =3D <&fin_pll>, + <&cmu_cmu DOUT_CLKCMU_PERI_IP>, + <&cmu_cmu DOUT_CLKCMU_PERI_AUDIO>, + <&cmu_cmu DOUT_CLKCMU_PERI_DISP>; + clock-names =3D "fin_pll", + "dout_clkcmu_peri_ip", + "dout_clkcmu_peri_audio", + "dout_clkcmu_peri_disp"; + status =3D "disabled"; + }; + + serial_0: serial@16cc0000 { + compatible =3D "axis,artpec8-uart"; + reg =3D <0x16cc0000 0x100>; + clocks =3D <&cmu_fsys DOUT_FSYS_BUS300>, + <&cmu_fsys DOUT_FSYS_SCLK_UART>; + clock-names =3D "uart", "clk_uart_baud0"; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&serial0_bus>; + status =3D "disabled"; + }; + }; +}; --=20 2.34.1