From nobody Tue Dec 23 12:18:25 2025 Received: from spam.coasia.com (mail2.coasia.com [112.168.119.159]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5EAD0125B2 for ; Thu, 10 Jul 2025 00:20:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=112.168.119.159 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752106863; cv=none; b=THy2GdTPtlQeS1xT1ua8/HXykobCshrM3kXHwR+BxNmZI3rpAgWz1lWKAeWPznm1udzv+JFCMGLT3QvTVEst2EF5IygtVq4C2Qb9WM+l4EuA7uqQA7mJH4DTxR1QXuQDg18lFitrV8yZBP9gkx4OkFlCbRbdk7iV4iCunyWjvIg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752106863; c=relaxed/simple; bh=DyFX5NVU0qfu6w33KZd1xOrQORMsGM0vYCT7ZpTXwlo=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=NGH+v0m9bFxKwLpzt2G256+A/xpQ/GOdoJUCJ3tBIZs+5yR1NWxnUxW7Dpflt3cZthPiMlo5i9coo3N02Rq6H3c1mhY/fC27JyAsobxPHh0AJLMwe8GFW86sBWVC2FyEDpuaVwIvFBEIlACnba8c33wUEICiiA5fpOuePClw0OY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=coasia.com; spf=pass smtp.mailfrom=coasia.com; dkim=pass (1024-bit key) header.d=coasia.com header.i=@coasia.com header.b=vh5S674m; arc=none smtp.client-ip=112.168.119.159 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=coasia.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=coasia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=coasia.com header.i=@coasia.com header.b="vh5S674m" DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=coasia.com; s=coasia; t=1752106850; bh=DyFX5NVU0qfu6w33KZd1xOrQORMsGM0vYCT7ZpTXwlo=; l=4651; h=From:To:Subject:Date:Message-Id:MIME-Version; b=vh5S674mIvXVosNkJsEGHaPWeduY8Ag4VBabLfEEwvW3o5DycqS4EdFl8pQYA/FPo ygmb4clDvQFkVscMIC02TQcJn/HJiKKQCyy4jXhqcHeH9YbWo/LW1rX04NGzloTJmU eFESaz1fIyCReTrtdaGPR5JMXBiyvKUZWYnQB83Q= Received: from unknown (HELO kangseongu..) (ksk4725@coasia.com@115.23.218.194) by 192.168.10.159 with ESMTP; 10 Jul 2025 09:20:50 +0900 X-Original-SENDERIP: 115.23.218.194 X-Original-SENDERCOUNTRY: KR, South Korea X-Original-MAILFROM: ksk4725@coasia.com X-Original-RCPTTO: jesper.nilsson@axis.com, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, krzk@kernel.org, s.nawrocki@samsung.com, cw00.choi@samsung.com, alim.akhtar@samsung.com, linus.walleij@linaro.org, tomasz.figa@gmail.com, catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de, ravi.patel@samsung.com, ksk4725@coasia.com, smn1196@coasia.com, kenkim@coasia.com, pjsin865@coasia.com, gwk1013@coasia.com, hgkim05@coasia.com, mingyoungbo@coasia.com, pankaj.dubey@samsung.com, shradha.t@samsung.com, inbaraj.e@samsung.com, swathi.ks@samsung.com, hrishikesh.d@samsung.com, dj76.yang@samsung.com, hypmean.kim@samsung.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@axis.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, soc@lists.linux.dev From: ksk4725@coasia.com To: Jesper Nilsson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krzysztof Kozlowski , Sylwester Nawrocki , Chanwoo Choi , Alim Akhtar , Linus Walleij , Tomasz Figa , Catalin Marinas , Will Deacon , Arnd Bergmann , Ravi Patel , SeonGu Kang , SungMin Park Cc: kenkim , Jongshin Park , GunWoo Kim , HaGyeong Kim , GyoungBo Min , Pankaj Dubey , Shradha Todi , Inbaraj E , Swathi K S , Hrishikesh , Dongjin Yang , Sang Min Kim , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@axis.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, soc@lists.linux.dev Subject: [PATCH 01/16] dt-bindings: clock: Add CMU bindings definitions for ARTPEC-8 platform Date: Thu, 10 Jul 2025 09:20:31 +0900 Message-Id: <20250710002047.1573841-2-ksk4725@coasia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250710002047.1573841-1-ksk4725@coasia.com> References: <20250710002047.1573841-1-ksk4725@coasia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Ravi Patel Add device tree clock definitions constants for ARTPEC-8 platform. ARTPEC-8 platform has separate instances for each particular CMU. So clock IDs in this bindings header also start from 1 for each CMU block. Signed-off-by: Hakyeong Kim Signed-off-by: Ravi Patel --- include/dt-bindings/clock/axis,artpec8-clk.h | 122 +++++++++++++++++++ 1 file changed, 122 insertions(+) create mode 100644 include/dt-bindings/clock/axis,artpec8-clk.h diff --git a/include/dt-bindings/clock/axis,artpec8-clk.h b/include/dt-bind= ings/clock/axis,artpec8-clk.h new file mode 100644 index 000000000000..69adfa999e34 --- /dev/null +++ b/include/dt-bindings/clock/axis,artpec8-clk.h @@ -0,0 +1,122 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2022-2025 Samsung Electronics Co., Ltd. + * https://www.samsung.com + * Copyright (c) 2022-2025 Axis Communications AB. + * https://www.axis.com + * + * Device Tree binding constants for ARTPEC-8 clock controller. + */ + +#ifndef _DT_BINDINGS_CLOCK_ARTPEC8_H +#define _DT_BINDINGS_CLOCK_ARTPEC8_H + +/* CMU_CMU */ +#define PLL_SHARED0 1 +#define DOUT_PLL_SHARED0_DIV2 2 +#define DOUT_PLL_SHARED0_DIV3 3 +#define DOUT_PLL_SHARED0_DIV4 4 +#define PLL_SHARED1 5 +#define DOUT_PLL_SHARED1_DIV2 6 +#define DOUT_PLL_SHARED1_DIV3 7 +#define DOUT_PLL_SHARED1_DIV4 8 +#define PLL_AUDIO 9 +#define DOUT_CLKCMU_BUS_BUS 10 +#define DOUT_CLKCMU_BUS_DLP 11 +#define DOUT_CLKCMU_CDC_CORE 12 +#define DOUT_CLKCMU_OTP 13 +#define DOUT_CLKCMU_CORE_MAIN 14 +#define DOUT_CLKCMU_CORE_DLP 15 +#define DOUT_CLKCMU_CPUCL_SWITCH 16 +#define DOUT_CLKCMU_DLP_CORE 17 +#define DOUT_CLKCMU_FSYS_BUS 18 +#define DOUT_CLKCMU_FSYS_IP 19 +#define DOUT_CLKCMU_FSYS_SCAN0 20 +#define DOUT_CLKCMU_FSYS_SCAN1 21 +#define DOUT_CLKCMU_GPU_3D 22 +#define DOUT_CLKCMU_GPU_2D 23 +#define DOUT_CLKCMU_IMEM_ACLK 24 +#define DOUT_CLKCMU_IMEM_JPEG 25 +#define DOUT_CLKCMU_MIF_SWITCH 26 +#define DOUT_CLKCMU_MIF_BUSP 27 +#define DOUT_CLKCMU_PERI_DISP 28 +#define DOUT_CLKCMU_PERI_IP 29 +#define DOUT_CLKCMU_PERI_AUDIO 30 +#define DOUT_CLKCMU_RSP_CORE 31 +#define DOUT_CLKCMU_TRFM_CORE 32 +#define DOUT_CLKCMU_VCA_ACE 33 +#define DOUT_CLKCMU_VCA_OD 34 +#define DOUT_CLKCMU_VIO_CORE 35 +#define DOUT_CLKCMU_VIO_AUDIO 36 +#define DOUT_CLKCMU_VIP0_CORE 37 +#define DOUT_CLKCMU_VIP1_CORE 38 +#define DOUT_CLKCMU_VPP_CORE 39 + +/* CMU_BUS */ +#define MOUT_CLK_BUS_ACLK_USER 1 +#define MOUT_CLK_BUS_DLP_USER 2 +#define DOUT_CLK_BUS_PCLK 3 + +/* CMU_CORE */ +#define MOUT_CLK_CORE_ACLK_USER 1 +#define MOUT_CLK_CORE_DLP_USER 2 +#define DOUT_CLK_CORE_PCLK 3 + +/* CMU_CPUCL */ +#define PLL_CPUCL 1 +#define MOUT_CLK_CPUCL_PLL 2 +#define MOUT_CLKCMU_CPUCL_SWITCH_USER 3 +#define DOUT_CLK_CPUCL_CPU 4 +#define DOUT_CLK_CLUSTER_ACLK 5 +#define DOUT_CLK_CLUSTER_PCLKDBG 6 +#define DOUT_CLK_CLUSTER_CNTCLK 7 +#define DOUT_CLK_CLUSTER_ATCLK 8 +#define DOUT_CLK_CPUCL_PCLK 9 +#define DOUT_CLK_CPUCL_CMUREF 10 +#define DOUT_CLK_CPUCL_DBG 11 +#define DOUT_CLK_CPUCL_PCLKDBG 12 + +/* CMU_FSYS */ +#define PLL_FSYS 1 +#define MOUT_FSYS_SCAN0_USER 2 +#define MOUT_FSYS_SCAN1_USER 3 +#define MOUT_FSYS_BUS_USER 4 +#define MOUT_FSYS_MMC_USER 5 +#define DOUT_FSYS_PCIE_PIPE 6 +#define DOUT_FSYS_ADC 7 +#define DOUT_FSYS_PCIE_PHY_REFCLK_SYSPLL 8 +#define DOUT_FSYS_EQOS_INT125 9 +#define DOUT_FSYS_OTP_MEM 10 +#define DOUT_FSYS_SCLK_UART 11 +#define DOUT_FSYS_EQOS_25 12 +#define DOUT_FSYS_EQOS_2p5 13 +#define DOUT_FSYS_BUS300 14 +#define DOUT_FSYS_BUS_QSPI 15 +#define DOUT_FSYS_MMC_CARD0 16 +#define DOUT_FSYS_MMC_CARD1 17 +#define DOUT_SCAN_CLK_FSYS_125 18 +#define DOUT_FSYS_QSPI 19 +#define DOUT_FSYS_SFMC_NAND 20 +#define DOUT_SCAN_CLK_FSYS_MMC 21 + +/* CMU_IMEM */ +#define MOUT_IMEM_ACLK_USER 1 +#define MOUT_IMEM_GIC_CA53 2 +#define MOUT_IMEM_GIC_CA5 3 +#define MOUT_IMEM_JPEG_USER 4 + +/* CMU_PERI */ +#define MOUT_PERI_IP_USER 1 +#define MOUT_PERI_AUDIO_USER 2 +#define MOUT_PERI_I2S0 3 +#define MOUT_PERI_I2S1 4 +#define MOUT_PERI_DISP_USER 5 +#define DOUT_PERI_SPI 6 +#define DOUT_PERI_UART1 7 +#define DOUT_PERI_UART2 8 +#define DOUT_PERI_PCLK 9 +#define DOUT_PERI_I2S0 10 +#define DOUT_PERI_I2S1 11 +#define DOUT_PERI_DSIM 12 + +#endif /* _DT_BINDINGS_CLOCK_ARTPEC8_H */ --=20 2.34.1 From nobody Tue Dec 23 12:18:25 2025 Received: from spam.coasia.com (mail2.coasia.com [112.168.119.159]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5ECC718C12 for ; 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(ksk4725@coasia.com@115.23.218.194) by 192.168.10.159 with ESMTP; 10 Jul 2025 09:20:51 +0900 X-Original-SENDERIP: 115.23.218.194 X-Original-SENDERCOUNTRY: KR, South Korea X-Original-MAILFROM: ksk4725@coasia.com X-Original-RCPTTO: jesper.nilsson@axis.com, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, krzk@kernel.org, s.nawrocki@samsung.com, cw00.choi@samsung.com, alim.akhtar@samsung.com, linus.walleij@linaro.org, tomasz.figa@gmail.com, catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de, ravi.patel@samsung.com, ksk4725@coasia.com, smn1196@coasia.com, kenkim@coasia.com, pjsin865@coasia.com, gwk1013@coasia.com, hgkim05@coasia.com, mingyoungbo@coasia.com, pankaj.dubey@samsung.com, shradha.t@samsung.com, inbaraj.e@samsung.com, swathi.ks@samsung.com, hrishikesh.d@samsung.com, dj76.yang@samsung.com, hypmean.kim@samsung.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@axis.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, soc@lists.linux.dev From: ksk4725@coasia.com To: Jesper Nilsson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krzysztof Kozlowski , Sylwester Nawrocki , Chanwoo Choi , Alim Akhtar , Linus Walleij , Tomasz Figa , Catalin Marinas , Will Deacon , Arnd Bergmann , Ravi Patel , SeonGu Kang , SungMin Park Cc: kenkim , Jongshin Park , GunWoo Kim , HaGyeong Kim , GyoungBo Min , Pankaj Dubey , Shradha Todi , Inbaraj E , Swathi K S , Hrishikesh , Dongjin Yang , Sang Min Kim , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@axis.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, soc@lists.linux.dev Subject: [PATCH 02/16] dt-bindings: clock: Add ARTPEC-8 CMU bindings Date: Thu, 10 Jul 2025 09:20:32 +0900 Message-Id: <20250710002047.1573841-3-ksk4725@coasia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250710002047.1573841-1-ksk4725@coasia.com> References: <20250710002047.1573841-1-ksk4725@coasia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Hakyeong Kim Add dt-schema for ARTPEC-8 SoC clock controller. Add device-tree binding definitions for following CMU blocks: - CMU_CMU - CMU_BUS - CMU_CORE - CMU_CPUCL - CMU_FSYS - CMU_IMEM - CMU_PERI Signed-off-by: Ravi Patel Signed-off-by: Hakyeong Kim --- .../bindings/clock/axis,artpec8-clock.yaml | 224 ++++++++++++++++++ 1 file changed, 224 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/axis,artpec8-cl= ock.yaml diff --git a/Documentation/devicetree/bindings/clock/axis,artpec8-clock.yam= l b/Documentation/devicetree/bindings/clock/axis,artpec8-clock.yaml new file mode 100644 index 000000000000..baacea10599b --- /dev/null +++ b/Documentation/devicetree/bindings/clock/axis,artpec8-clock.yaml @@ -0,0 +1,224 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/axis,artpec8-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Axis ARTPEC-8 SoC clock controller + +maintainers: + - Jesper Nilsson + +description: | + ARTPEC-8 clock controller is comprised of several CMU units, generating + clocks for different domains. Those CMU units are modeled as separate de= vice + tree nodes, and might depend on each other. The root clock in that root = tree + is an external clock: OSCCLK (25 MHz). This external clock must be defin= ed + as a fixed-rate clock in dts. + + CMU_CMU is a top-level CMU, where all base clocks are prepared using PLL= s and + dividers; all other clocks of function blocks (other CMUs) are usually + derived from CMU_CMU. + + Each clock is assigned an identifier and client nodes can use this ident= ifier + to specify the clock which they consume. All clocks available for usage + in clock consumer nodes are defined as preprocessor macros in + 'include/dt-bindings/clock/axis,artpec8-clk.h' header. + +properties: + compatible: + enum: + - axis,artpec8-cmu-cmu + - axis,artpec8-cmu-bus + - axis,artpec8-cmu-core + - axis,artpec8-cmu-cpucl + - axis,artpec8-cmu-fsys + - axis,artpec8-cmu-imem + - axis,artpec8-cmu-peri + + clocks: + minItems: 1 + maxItems: 5 + + clock-names: + minItems: 1 + maxItems: 5 + + "#clock-cells": + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - "#clock-cells" + - clocks + - clock-names + +allOf: + - if: + properties: + compatible: + contains: + const: axis,artpec8-cmu-cmu + + then: + properties: + clocks: + items: + - description: External reference clock (25 MHz) + + clock-names: + items: + - const: fin_pll + + - if: + properties: + compatible: + contains: + const: axis,artpec8-cmu-bus + + then: + properties: + clocks: + items: + - description: External reference clock (25 MHz) + - description: CMU_BUS BUS clock (from CMU_CMU) + - description: CMU_BUS DLP clock (from CMU_CMU) + + clock-names: + items: + - const: fin_pll + - const: dout_clkcmu_bus_bus + - const: dout_clkcmu_bus_dlp + + - if: + properties: + compatible: + contains: + const: axis,artpec8-cmu-core + + then: + properties: + clocks: + items: + - description: External reference clock (25 MHz) + - description: CMU_CORE main clock (from CMU_CMU) + - description: CMU_CORE DLP clock (from CMU_CMU) + + clock-names: + items: + - const: fin_pll + - const: dout_clkcmu_core_main + - const: dout_clkcmu_core_dlp + + - if: + properties: + compatible: + contains: + const: axis,artpec8-cmu-cpucl + + then: + properties: + clocks: + items: + - description: External reference clock (25 MHz) + - description: CMU_CPUCL switch clock (from CMU_CMU) + + clock-names: + items: + - const: fin_pll + - const: dout_clkcmu_cpucl_switch + + - if: + properties: + compatible: + contains: + const: axis,artpec8-cmu-fsys + + then: + properties: + clocks: + items: + - description: External reference clock (25 MHz) + - description: CMU_FSYS SCAN0 clock (from CMU_CMU) + - description: CMU_FSYS SCAN1 clock (from CMU_CMU) + - description: CMU_FSYS BUS clock (from CMU_CMU) + - description: CMU_FSYS IP clock (from CMU_CMU) + + clock-names: + items: + - const: fin_pll + - const: dout_clkcmu_fsys_scan0 + - const: dout_clkcmu_fsys_scan1 + - const: dout_clkcmu_fsys_bus + - const: dout_clkcmu_fsys_ip + + - if: + properties: + compatible: + contains: + const: axis,artpec8-cmu-imem + + then: + properties: + clocks: + items: + - description: External reference clock (25 MHz) + - description: CMU_IMEM ACLK clock (from CMU_CMU) + - description: CMU_IMEM JPEG clock (from CMU_CMU) + + clock-names: + items: + - const: fin_pll + - const: dout_clkcmu_imem_aclk + - const: dout_clkcmu_imem_jpeg + + - if: + properties: + compatible: + contains: + const: axis,artpec8-cmu-peri + + then: + properties: + clocks: + items: + - description: External reference clock (25 MHz) + - description: CMU_PERI IP clock (from CMU_CMU) + - description: CMU_PERI AUDIO clock (from CMU_CMU) + - description: CMU_PERI DISP clock (from CMU_CMU) + + clock-names: + items: + - const: fin_pll + - const: dout_clkcmu_peri_ip + - const: dout_clkcmu_peri_audio + - const: dout_clkcmu_peri_disp + +additionalProperties: false + +examples: + # Clock controller node for CMU_FSYS + - | + #include + + cmu_fsys: clock-controller@16c10000 { + compatible =3D "axis,artpec8-cmu-fsys"; + reg =3D <0x16c10000 0x4000>; + #clock-cells =3D <1>; + clocks =3D <&fin_pll>, + <&cmu_cmu DOUT_CLKCMU_FSYS_SCAN0>, + <&cmu_cmu DOUT_CLKCMU_FSYS_SCAN1>, + <&cmu_cmu DOUT_CLKCMU_FSYS_BUS>, + <&cmu_cmu DOUT_CLKCMU_FSYS_IP>; + clock-names =3D "fin_pll", + "dout_clkcmu_fsys_scan0", + "dout_clkcmu_fsys_scan1", + "dout_clkcmu_fsys_bus", + "dout_clkcmu_fsys_ip"; + }; + +... --=20 2.34.1 From nobody Tue Dec 23 12:18:25 2025 Received: from spam.coasia.com (mail2.coasia.com [112.168.119.159]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C9CD243146 for ; Thu, 10 Jul 2025 00:21:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=112.168.119.159 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752106866; cv=none; b=D4gfZ2Bzb/yAXJespSJEYBAtmLe9qOzMVg111Jve1ICdxaeCRSz5z2OsMDwjlEaOg5X5dxfOCUJ/Nwj2RMZ/DgiyXs9ndDkptJkrOtKwgcE3NA6z7MXrj8Q7af1Jb75JN/t1m6GLgrebmpi2We+GSBO5bJlK5wTeTb4+Skt/mCA= ARC-Message-Signature: i=1; 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(ksk4725@coasia.com@115.23.218.194) by 192.168.10.159 with ESMTP; 10 Jul 2025 09:20:52 +0900 X-Original-SENDERIP: 115.23.218.194 X-Original-SENDERCOUNTRY: KR, South Korea X-Original-MAILFROM: ksk4725@coasia.com X-Original-RCPTTO: jesper.nilsson@axis.com, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, krzk@kernel.org, s.nawrocki@samsung.com, cw00.choi@samsung.com, alim.akhtar@samsung.com, linus.walleij@linaro.org, tomasz.figa@gmail.com, catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de, kenkim@coasia.com, pjsin865@coasia.com, gwk1013@coasia.com, ksk4725@coasia.com, hgkim05@coasia.com, mingyoungbo@coasia.com, smn1196@coasia.com, pankaj.dubey@samsung.com, shradha.t@samsung.com, ravi.patel@samsung.com, inbaraj.e@samsung.com, swathi.ks@samsung.com, hrishikesh.d@samsung.com, dj76.yang@samsung.com, hypmean.kim@samsung.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@axis.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, soc@lists.linux.dev From: ksk4725@coasia.com To: Jesper Nilsson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krzysztof Kozlowski , Sylwester Nawrocki , Chanwoo Choi , Alim Akhtar , Linus Walleij , Tomasz Figa , Catalin Marinas , Will Deacon , Arnd Bergmann Cc: kenkim , Jongshin Park , GunWoo Kim , SeonGu Kang , HaGyeong Kim , GyoungBo Min , SungMin Park , Pankaj Dubey , Shradha Todi , Ravi Patel , Inbaraj E , Swathi K S , Hrishikesh , Dongjin Yang , Sang Min Kim , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@axis.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, soc@lists.linux.dev Subject: [PATCH 03/16] clk: samsung: Add clock PLL support for ARTPEC-8 SoC Date: Thu, 10 Jul 2025 09:20:33 +0900 Message-Id: <20250710002047.1573841-4-ksk4725@coasia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250710002047.1573841-1-ksk4725@coasia.com> References: <20250710002047.1573841-1-ksk4725@coasia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Hakyeong Kim Add below clock PLL support for ARTPEC-8 SoC platform: - pll_1017x - pll_1031x Signed-off-by: Ravi Patel Signed-off-by: Hakyeong Kim --- drivers/clk/samsung/clk-pll.c | 129 +++++++++++++++++++++++++++++++++- drivers/clk/samsung/clk-pll.h | 2 + 2 files changed, 130 insertions(+), 1 deletion(-) diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c index fe8abe442c51..3337483ff8b8 100644 --- a/drivers/clk/samsung/clk-pll.c +++ b/drivers/clk/samsung/clk-pll.c @@ -17,6 +17,7 @@ #include "clk.h" #include "clk-pll.h" =20 +#define PLL_TIMEOUT_MS 10U #define PLL_TIMEOUT_US 20000U #define PLL_TIMEOUT_LOOPS 1000000U =20 @@ -273,7 +274,7 @@ static int samsung_pll35xx_set_rate(struct clk_hw *hw, = unsigned long drate, } =20 /* Set PLL lock time. */ - if (pll->type =3D=3D pll_142xx) + if (pll->type =3D=3D pll_142xx || pll->type =3D=3D pll_1017x) writel_relaxed(rate->pdiv * PLL142XX_LOCK_FACTOR, pll->lock_reg); else @@ -1325,6 +1326,125 @@ static const struct clk_ops samsung_pll531x_clk_ops= =3D { .recalc_rate =3D samsung_pll531x_recalc_rate, }; =20 +/* + * PLL1031X Clock Type + */ +#define PLL1031X_LOCK_FACTOR (500) + +#define PLL1031X_MDIV_MASK (0x3ff) +#define PLL1031X_PDIV_MASK (0x3f) +#define PLL1031X_SDIV_MASK (0x7) +#define PLL1031X_MDIV_SHIFT (16) +#define PLL1031X_PDIV_SHIFT (8) +#define PLL1031X_SDIV_SHIFT (0) + +#define PLL1031X_KDIV_MASK (0xffff) +#define PLL1031X_KDIV_SHIFT (0) +#define PLL1031X_MFR_MASK (0x3f) +#define PLL1031X_MRR_MASK (0x1f) +#define PLL1031X_MFR_SHIFT (16) +#define PLL1031X_MRR_SHIFT (24) + +static unsigned long samsung_pll1031x_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct samsung_clk_pll *pll =3D to_clk_pll(hw); + u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con3; + u64 fvco =3D parent_rate; + + pll_con0 =3D readl_relaxed(pll->con_reg); + pll_con3 =3D readl_relaxed(pll->con_reg + 0xc); + mdiv =3D (pll_con0 >> PLL1031X_MDIV_SHIFT) & PLL1031X_MDIV_MASK; + pdiv =3D (pll_con0 >> PLL1031X_PDIV_SHIFT) & PLL1031X_PDIV_MASK; + sdiv =3D (pll_con0 >> PLL1031X_SDIV_SHIFT) & PLL1031X_SDIV_MASK; + kdiv =3D (pll_con3 & PLL1031X_KDIV_MASK); + + fvco *=3D (mdiv << PLL1031X_MDIV_SHIFT) + kdiv; + do_div(fvco, (pdiv << sdiv)); + fvco >>=3D PLL1031X_MDIV_SHIFT; + + return (unsigned long)fvco; +} + +static bool samsung_pll1031x_mpk_change(u32 pll_con0, u32 pll_con3, + const struct samsung_pll_rate_table *rate) +{ + u32 old_mdiv, old_pdiv, old_kdiv; + + old_mdiv =3D (pll_con0 >> PLL1031X_MDIV_SHIFT) & PLL1031X_MDIV_MASK; + old_pdiv =3D (pll_con0 >> PLL1031X_PDIV_SHIFT) & PLL1031X_PDIV_MASK; + old_kdiv =3D (pll_con3 >> PLL1031X_KDIV_SHIFT) & PLL1031X_KDIV_MASK; + + return (old_mdiv !=3D rate->mdiv || old_pdiv !=3D rate->pdiv || + old_kdiv !=3D rate->kdiv); +} + +static int samsung_pll1031x_set_rate(struct clk_hw *hw, unsigned long drat= e, + unsigned long prate) +{ + struct samsung_clk_pll *pll =3D to_clk_pll(hw); + const struct samsung_pll_rate_table *rate; + u32 con0, con3; + + /* Get required rate settings from table */ + rate =3D samsung_get_pll_settings(pll, drate); + if (!rate) { + pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, + drate, clk_hw_get_name(hw)); + return -EINVAL; + } + + con0 =3D readl_relaxed(pll->con_reg); + con3 =3D readl_relaxed(pll->con_reg + 0xc); + + if (!(samsung_pll1031x_mpk_change(con0, con3, rate))) { + /* If only s change, change just s value only */ + con0 &=3D ~(PLL1031X_SDIV_MASK << PLL1031X_SDIV_SHIFT); + con0 |=3D rate->sdiv << PLL1031X_SDIV_SHIFT; + writel_relaxed(con0, pll->con_reg); + + return 0; + } + + /* Set PLL lock time. */ + writel_relaxed(rate->pdiv * PLL1031X_LOCK_FACTOR, pll->lock_reg); + + /* Set PLL M, P, and S values. */ + con0 &=3D ~((PLL1031X_MDIV_MASK << PLL1031X_MDIV_SHIFT) | + (PLL1031X_PDIV_MASK << PLL1031X_PDIV_SHIFT) | + (PLL1031X_SDIV_MASK << PLL1031X_SDIV_SHIFT)); + + con0 |=3D (rate->mdiv << PLL1031X_MDIV_SHIFT) | + (rate->pdiv << PLL1031X_PDIV_SHIFT) | + (rate->sdiv << PLL1031X_SDIV_SHIFT); + + /* Set PLL K, MFR and MRR values. */ + con3 =3D readl_relaxed(pll->con_reg + 0xc); + con3 &=3D ~((PLL1031X_KDIV_MASK << PLL1031X_KDIV_SHIFT) | + (PLL1031X_MFR_MASK << PLL1031X_MFR_SHIFT) | + (PLL1031X_MRR_MASK << PLL1031X_MRR_SHIFT)); + con3 |=3D (rate->kdiv << PLL1031X_KDIV_SHIFT) | + (rate->mfr << PLL1031X_MFR_SHIFT) | + (rate->mrr << PLL1031X_MRR_SHIFT); + + /* Write configuration to PLL */ + writel_relaxed(con0, pll->con_reg); + writel_relaxed(con3, pll->con_reg + 0xc); + + /* Wait for PLL lock if the PLL is enabled */ + return samsung_pll_lock_wait(pll, BIT(pll->lock_offs)); +} + +static const struct clk_ops samsung_pll1031x_clk_ops =3D { + .recalc_rate =3D samsung_pll1031x_recalc_rate, + .round_rate =3D samsung_pll_round_rate, + .set_rate =3D samsung_pll1031x_set_rate, +}; + +static const struct clk_ops samsung_pll1031x_clk_min_ops =3D { + .recalc_rate =3D samsung_pll1031x_recalc_rate, +}; + static void __init _samsung_clk_register_pll(struct samsung_clk_provider *= ctx, const struct samsung_pll_clock *pll_clk) { @@ -1373,6 +1493,7 @@ static void __init _samsung_clk_register_pll(struct s= amsung_clk_provider *ctx, case pll_1451x: case pll_1452x: case pll_142xx: + case pll_1017x: pll->enable_offs =3D PLL35XX_ENABLE_SHIFT; pll->lock_offs =3D PLL35XX_LOCK_STAT_SHIFT; if (!pll->rate_table) @@ -1468,6 +1589,12 @@ static void __init _samsung_clk_register_pll(struct = samsung_clk_provider *ctx, case pll_4311: init.ops =3D &samsung_pll531x_clk_ops; break; + case pll_1031x: + if (!pll->rate_table) + init.ops =3D &samsung_pll1031x_clk_min_ops; + else + init.ops =3D &samsung_pll1031x_clk_ops; + break; default: pr_warn("%s: Unknown pll type for pll clk %s\n", __func__, pll_clk->name); diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h index e9a5f8e0e0a3..6c8bb7f26da5 100644 --- a/drivers/clk/samsung/clk-pll.h +++ b/drivers/clk/samsung/clk-pll.h @@ -49,6 +49,8 @@ enum samsung_pll_type { pll_0718x, pll_0732x, pll_4311, + pll_1017x, + pll_1031x, }; =20 #define PLL_RATE(_fin, _m, _p, _s, _k, _ks) \ --=20 2.34.1 From nobody Tue Dec 23 12:18:25 2025 Received: from spam.coasia.com (mail2.coasia.com [112.168.119.159]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 84DDD469D for ; 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(ksk4725@coasia.com@115.23.218.194) by 192.168.10.159 with ESMTP; 10 Jul 2025 09:20:53 +0900 X-Original-SENDERIP: 115.23.218.194 X-Original-SENDERCOUNTRY: KR, South Korea X-Original-MAILFROM: ksk4725@coasia.com X-Original-RCPTTO: jesper.nilsson@axis.com, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, krzk@kernel.org, s.nawrocki@samsung.com, cw00.choi@samsung.com, alim.akhtar@samsung.com, linus.walleij@linaro.org, tomasz.figa@gmail.com, catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de, ravi.patel@samsung.com, ksk4725@coasia.com, smn1196@coasia.com, kenkim@coasia.com, pjsin865@coasia.com, gwk1013@coasia.com, hgkim05@coasia.com, mingyoungbo@coasia.com, pankaj.dubey@samsung.com, shradha.t@samsung.com, inbaraj.e@samsung.com, swathi.ks@samsung.com, hrishikesh.d@samsung.com, dj76.yang@samsung.com, hypmean.kim@samsung.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@axis.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, soc@lists.linux.dev From: ksk4725@coasia.com To: Jesper Nilsson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krzysztof Kozlowski , Sylwester Nawrocki , Chanwoo Choi , Alim Akhtar , Linus Walleij , Tomasz Figa , Catalin Marinas , Will Deacon , Arnd Bergmann , Ravi Patel , SeonGu Kang , SungMin Park Cc: kenkim , Jongshin Park , GunWoo Kim , HaGyeong Kim , GyoungBo Min , Pankaj Dubey , Shradha Todi , Inbaraj E , Swathi K S , Hrishikesh , Dongjin Yang , Sang Min Kim , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@axis.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, soc@lists.linux.dev Subject: [PATCH 04/16] clk: samsung: artpec-8: Add initial clock support Date: Thu, 10 Jul 2025 09:20:34 +0900 Message-Id: <20250710002047.1573841-5-ksk4725@coasia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250710002047.1573841-1-ksk4725@coasia.com> References: <20250710002047.1573841-1-ksk4725@coasia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Hakyeong Kim Add initial clock support for ARTPEC-8 SoC which is required for enabling basic clock management. Add clock support for below CMU block in ARTPEC-8 SoC: - CMU_IMEM Signed-off-by: Ravi Patel Signed-off-by: Hakyeong Kim --- drivers/clk/samsung/Kconfig | 8 ++++ drivers/clk/samsung/Makefile | 1 + drivers/clk/samsung/clk-artpec8.c | 62 +++++++++++++++++++++++++++++++ 3 files changed, 71 insertions(+) create mode 100644 drivers/clk/samsung/clk-artpec8.c diff --git a/drivers/clk/samsung/Kconfig b/drivers/clk/samsung/Kconfig index 76a494e95027..289591b403ad 100644 --- a/drivers/clk/samsung/Kconfig +++ b/drivers/clk/samsung/Kconfig @@ -13,6 +13,7 @@ config COMMON_CLK_SAMSUNG select EXYNOS_5420_COMMON_CLK if ARM && SOC_EXYNOS5420 select EXYNOS_ARM64_COMMON_CLK if ARM64 && ARCH_EXYNOS select TESLA_FSD_COMMON_CLK if ARM64 && ARCH_TESLA_FSD + select ARTPEC8_COMMON_CLK if ARM64 && ARCH_ARTPEC8 =20 config S3C64XX_COMMON_CLK bool "Samsung S3C64xx clock controller support" if COMPILE_TEST @@ -102,3 +103,10 @@ config TESLA_FSD_COMMON_CLK help Support for the clock controller present on the Tesla FSD SoC. Choose Y here only if you build for this SoC. + +config ARTPEC8_COMMON_CLK + bool "Axis ARTPEC-8 clock controller support" if COMPILE_TEST + depends on COMMON_CLK_SAMSUNG + help + Support for the clock controller present on the Axis ARTPEC-8 SoC. + Choose Y here only if you are building for the Axis ARTPEC-8 SoC. diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile index b77fe288e4bb..473eb08fc8fc 100644 --- a/drivers/clk/samsung/Makefile +++ b/drivers/clk/samsung/Makefile @@ -3,6 +3,7 @@ # Samsung Clock specific Makefile # =20 +obj-$(CONFIG_ARTPEC8_COMMON_CLK) +=3D clk-artpec8.o obj-$(CONFIG_COMMON_CLK) +=3D clk.o clk-pll.o clk-cpu.o obj-$(CONFIG_EXYNOS_3250_COMMON_CLK) +=3D clk-exynos3250.o obj-$(CONFIG_EXYNOS_4_COMMON_CLK) +=3D clk-exynos4.o diff --git a/drivers/clk/samsung/clk-artpec8.c b/drivers/clk/samsung/clk-ar= tpec8.c new file mode 100644 index 000000000000..11a48b2fcc09 --- /dev/null +++ b/drivers/clk/samsung/clk-artpec8.c @@ -0,0 +1,62 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022-2025 Samsung Electronics Co., Ltd. + * https://www.samsung.com + * Copyright (c) 2022-2025 Axis Communications AB. + * https://www.axis.com + * + * Common Clock Framework support for ARTPEC-8 SoC. + */ + +#include +#include + +#include "clk.h" + +/* NOTE: Must be equal to the last clock ID increased by one */ +#define CMU_IMEM_NR_CLK (MOUT_IMEM_JPEG_USER + 1) + +/* Register Offset definitions for CMU_IMEM (0x10010000) */ +#define PLL_CON0_MUX_CLK_IMEM_ACLK_USER 0x0100 +#define PLL_CON0_MUX_CLK_IMEM_JPEG_USER 0x0120 +#define MUX_CLK_IMEM_GIC_CA53 0x1000 +#define MUX_CLK_IMEM_GIC_CA5 0x1008 + +static const unsigned long cmu_imem_clk_regs[] __initconst =3D { + PLL_CON0_MUX_CLK_IMEM_ACLK_USER, + PLL_CON0_MUX_CLK_IMEM_JPEG_USER, + MUX_CLK_IMEM_GIC_CA53, + MUX_CLK_IMEM_GIC_CA5, +}; + +PNAME(mout_imem_aclk_user_p) =3D { "fin_pll", "dout_clkcmu_imem_aclk" }; +PNAME(mout_imem_gic_ca53_p) =3D { "mout_imem_aclk_user", "fin_pll" }; +PNAME(mout_imem_gic_ca5_p) =3D { "mout_imem_aclk_user", "fin_pll" }; +PNAME(mout_imem_jpeg_user_p) =3D { "fin_pll", "dout_clkcmu_imem_jpeg" }; + +static const struct samsung_mux_clock cmu_imem_mux_clks[] __initconst =3D { + MUX(MOUT_IMEM_ACLK_USER, "mout_imem_aclk_user", + mout_imem_aclk_user_p, PLL_CON0_MUX_CLK_IMEM_ACLK_USER, 4, 1), + MUX(MOUT_IMEM_GIC_CA53, "mout_imem_gic_ca53", + mout_imem_gic_ca53_p, MUX_CLK_IMEM_GIC_CA53, 0, 1), + MUX(MOUT_IMEM_GIC_CA5, "mout_imem_gic_ca5", + mout_imem_gic_ca5_p, MUX_CLK_IMEM_GIC_CA5, 0, 1), + MUX(MOUT_IMEM_JPEG_USER, "mout_imem_jpeg_user", + mout_imem_jpeg_user_p, PLL_CON0_MUX_CLK_IMEM_JPEG_USER, 4, 1), +}; + +static const struct samsung_cmu_info cmu_imem_info __initconst =3D { + .mux_clks =3D cmu_imem_mux_clks, + .nr_mux_clks =3D ARRAY_SIZE(cmu_imem_mux_clks), + .nr_clk_ids =3D CMU_IMEM_NR_CLK, + .clk_regs =3D cmu_imem_clk_regs, + .nr_clk_regs =3D ARRAY_SIZE(cmu_imem_clk_regs), +}; + +static void __init artpec8_clk_cmu_imem_init(struct device_node *np) +{ + samsung_cmu_register_one(np, &cmu_imem_info); +} + +CLK_OF_DECLARE(artpec8_clk_cmu_imem, "axis,artpec8-cmu-imem", + artpec8_clk_cmu_imem_init); --=20 2.34.1 From nobody Tue Dec 23 12:18:25 2025 Received: from spam.coasia.com (mail2.coasia.com [112.168.119.159]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C1B8AAD5E for ; Thu, 10 Jul 2025 00:20:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=112.168.119.159 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752106862; cv=none; b=KlKh3LvSL7gkAD+cYsEOUVexHerUtpnT2JG7ArkypYn7fUnaHnkB5CwAEE3VY4A9wo28yClDjotAMMEcX+DkwgjJQzTC4I3Ajrl7BfIU1/DYd3KzXuMTPgFFOPoZsMqeHe3LFdctnGtnppurIWo0Qaf+MLNYro44cRkyWPE0vBs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752106862; c=relaxed/simple; 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(ksk4725@coasia.com@115.23.218.194) by 192.168.10.159 with ESMTP; 10 Jul 2025 09:20:54 +0900 X-Original-SENDERIP: 115.23.218.194 X-Original-SENDERCOUNTRY: KR, South Korea X-Original-MAILFROM: ksk4725@coasia.com X-Original-RCPTTO: jesper.nilsson@axis.com, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, krzk@kernel.org, s.nawrocki@samsung.com, cw00.choi@samsung.com, alim.akhtar@samsung.com, linus.walleij@linaro.org, tomasz.figa@gmail.com, catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de, ravi.patel@samsung.com, ksk4725@coasia.com, smn1196@coasia.com, kenkim@coasia.com, pjsin865@coasia.com, gwk1013@coasia.com, hgkim05@coasia.com, mingyoungbo@coasia.com, pankaj.dubey@samsung.com, shradha.t@samsung.com, inbaraj.e@samsung.com, swathi.ks@samsung.com, hrishikesh.d@samsung.com, dj76.yang@samsung.com, hypmean.kim@samsung.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@axis.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, soc@lists.linux.dev From: ksk4725@coasia.com To: Jesper Nilsson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krzysztof Kozlowski , Sylwester Nawrocki , Chanwoo Choi , Alim Akhtar , Linus Walleij , Tomasz Figa , Catalin Marinas , Will Deacon , Arnd Bergmann , Ravi Patel , SeonGu Kang , SungMin Park Cc: kenkim , Jongshin Park , GunWoo Kim , HaGyeong Kim , GyoungBo Min , Pankaj Dubey , Shradha Todi , Inbaraj E , Swathi K S , Hrishikesh , Dongjin Yang , Sang Min Kim , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@axis.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, soc@lists.linux.dev Subject: [PATCH 05/16] clk: samsung: artpec-8: Add clock support for CMU_CMU block Date: Thu, 10 Jul 2025 09:20:35 +0900 Message-Id: <20250710002047.1573841-6-ksk4725@coasia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250710002047.1573841-1-ksk4725@coasia.com> References: <20250710002047.1573841-1-ksk4725@coasia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Hakyeong Kim Add clock support for below CMU block in ARTPEC-8 SoC. - CMU_CMU Signed-off-by: Ravi Patel Signed-off-by: Hakyeong Kim --- drivers/clk/samsung/clk-artpec8.c | 415 ++++++++++++++++++++++++++++++ 1 file changed, 415 insertions(+) diff --git a/drivers/clk/samsung/clk-artpec8.c b/drivers/clk/samsung/clk-ar= tpec8.c index 11a48b2fcc09..1ef9e52ad24b 100644 --- a/drivers/clk/samsung/clk-artpec8.c +++ b/drivers/clk/samsung/clk-artpec8.c @@ -14,8 +14,423 @@ #include "clk.h" =20 /* NOTE: Must be equal to the last clock ID increased by one */ +#define CMU_CMU_NR_CLK (DOUT_CLKCMU_VPP_CORE + 1) #define CMU_IMEM_NR_CLK (MOUT_IMEM_JPEG_USER + 1) =20 +/* register offset definitions for cmu_cmu (0x12400000) */ +#define PLL_LOCKTIME_PLL_AUDIO 0x0000 +#define PLL_LOCKTIME_PLL_SHARED0 0x0004 +#define PLL_LOCKTIME_PLL_SHARED1 0x0008 +#define PLL_CON0_PLL_AUDIO 0x0100 +#define PLL_CON0_PLL_SHARED0 0x0120 +#define PLL_CON0_PLL_SHARED1 0x0140 +#define MUX_CLKCMU_2D 0x1000 +#define MUX_CLKCMU_3D 0x1004 +#define MUX_CLKCMU_BUS_BUS 0x1008 +#define MUX_CLKCMU_BUS_DLP 0x100c +#define MUX_CLKCMU_CDC_CORE 0x1010 +#define MUX_CLKCMU_FSYS_SCAN0 0x1014 +#define MUX_CLKCMU_FSYS_SCAN1 0x1018 +#define MUX_CLKCMU_IMEM_JPEG 0x101c +#define MUX_CLKCMU_PERI_DISP 0x1020 +#define MUX_CLKCMU_CORE_BUS 0x1024 +#define MUX_CLKCMU_CORE_DLP 0x1028 +#define MUX_CLKCMU_CPUCL_SWITCH 0x1030 +#define MUX_CLKCMU_DLP_CORE 0x1034 +#define MUX_CLKCMU_FSYS_BUS 0x1038 +#define MUX_CLKCMU_FSYS_IP 0x103c +#define MUX_CLKCMU_IMEM_ACLK 0x1054 +#define MUX_CLKCMU_MIF_BUSP 0x1080 +#define MUX_CLKCMU_MIF_SWITCH 0x1084 +#define MUX_CLKCMU_PERI_IP 0x1088 +#define MUX_CLKCMU_RSP_CORE 0x108c +#define MUX_CLKCMU_TRFM_CORE 0x1090 +#define MUX_CLKCMU_VCA_ACE 0x1094 +#define MUX_CLKCMU_VCA_OD 0x1098 +#define MUX_CLKCMU_VIO_CORE 0x109c +#define MUX_CLKCMU_VIP0_CORE 0x10a0 +#define MUX_CLKCMU_VIP1_CORE 0x10a4 +#define MUX_CLKCMU_VPP_CORE 0x10a8 + +#define DIV_CLKCMU_BUS_BUS 0x1800 +#define DIV_CLKCMU_BUS_DLP 0x1804 +#define DIV_CLKCMU_CDC_CORE 0x1808 +#define DIV_CLKCMU_FSYS_SCAN0 0x180c +#define DIV_CLKCMU_FSYS_SCAN1 0x1810 +#define DIV_CLKCMU_IMEM_JPEG 0x1814 +#define DIV_CLKCMU_MIF_SWITCH 0x1818 +#define DIV_CLKCMU_CORE_DLP 0x181c +#define DIV_CLKCMU_CORE_MAIN 0x1820 +#define DIV_CLKCMU_PERI_DISP 0x1824 +#define DIV_CLKCMU_CPUCL_SWITCH 0x1828 +#define DIV_CLKCMU_DLP_CORE 0x182c +#define DIV_CLKCMU_FSYS_BUS 0x1830 +#define DIV_CLKCMU_FSYS_IP 0x1834 +#define DIV_CLKCMU_VIO_AUDIO 0x1838 +#define DIV_CLKCMU_GPU_2D 0x1848 +#define DIV_CLKCMU_GPU_3D 0x184c +#define DIV_CLKCMU_IMEM_ACLK 0x1854 +#define DIV_CLKCMU_MIF_BUSP 0x1884 +#define DIV_CLKCMU_PERI_AUDIO 0x1890 +#define DIV_CLKCMU_PERI_IP 0x1894 +#define DIV_CLKCMU_RSP_CORE 0x1898 +#define DIV_CLKCMU_TRFM_CORE 0x189c +#define DIV_CLKCMU_VCA_ACE 0x18a0 +#define DIV_CLKCMU_VCA_OD 0x18a4 +#define DIV_CLKCMU_VIO_CORE 0x18ac +#define DIV_CLKCMU_VIP0_CORE 0x18b0 +#define DIV_CLKCMU_VIP1_CORE 0x18b4 +#define DIV_CLKCMU_VPP_CORE 0x18b8 +#define DIV_PLL_SHARED0_DIV2 0x18bc +#define DIV_PLL_SHARED0_DIV3 0x18c0 +#define DIV_PLL_SHARED0_DIV4 0x18c4 +#define DIV_PLL_SHARED1_DIV2 0x18c8 +#define DIV_PLL_SHARED1_DIV3 0x18cc +#define DIV_PLL_SHARED1_DIV4 0x18d0 + +static const unsigned long cmu_cmu_clk_regs[] __initconst =3D { + PLL_LOCKTIME_PLL_AUDIO, + PLL_LOCKTIME_PLL_SHARED0, + PLL_LOCKTIME_PLL_SHARED1, + PLL_CON0_PLL_AUDIO, + PLL_CON0_PLL_SHARED0, + PLL_CON0_PLL_SHARED1, + MUX_CLKCMU_2D, + MUX_CLKCMU_3D, + MUX_CLKCMU_BUS_BUS, + MUX_CLKCMU_BUS_DLP, + MUX_CLKCMU_CDC_CORE, + MUX_CLKCMU_FSYS_SCAN0, + MUX_CLKCMU_FSYS_SCAN1, + MUX_CLKCMU_IMEM_JPEG, + MUX_CLKCMU_PERI_DISP, + MUX_CLKCMU_CORE_BUS, + MUX_CLKCMU_CORE_DLP, + MUX_CLKCMU_CPUCL_SWITCH, + MUX_CLKCMU_DLP_CORE, + MUX_CLKCMU_FSYS_BUS, + MUX_CLKCMU_FSYS_IP, + MUX_CLKCMU_IMEM_ACLK, + MUX_CLKCMU_MIF_BUSP, + MUX_CLKCMU_MIF_SWITCH, + MUX_CLKCMU_PERI_IP, + MUX_CLKCMU_RSP_CORE, + MUX_CLKCMU_TRFM_CORE, + MUX_CLKCMU_VCA_ACE, + MUX_CLKCMU_VCA_OD, + MUX_CLKCMU_VIO_CORE, + MUX_CLKCMU_VIP0_CORE, + MUX_CLKCMU_VIP1_CORE, + MUX_CLKCMU_VPP_CORE, + DIV_CLKCMU_BUS_BUS, + DIV_CLKCMU_BUS_DLP, + DIV_CLKCMU_CDC_CORE, + DIV_CLKCMU_FSYS_SCAN0, + DIV_CLKCMU_FSYS_SCAN1, + DIV_CLKCMU_IMEM_JPEG, + DIV_CLKCMU_MIF_SWITCH, + DIV_CLKCMU_CORE_DLP, + DIV_CLKCMU_CORE_MAIN, + DIV_CLKCMU_PERI_DISP, + DIV_CLKCMU_CPUCL_SWITCH, + DIV_CLKCMU_DLP_CORE, + DIV_CLKCMU_FSYS_BUS, + DIV_CLKCMU_FSYS_IP, + DIV_CLKCMU_VIO_AUDIO, + DIV_CLKCMU_GPU_2D, + DIV_CLKCMU_GPU_3D, + DIV_CLKCMU_IMEM_ACLK, + DIV_CLKCMU_MIF_BUSP, + DIV_CLKCMU_PERI_AUDIO, + DIV_CLKCMU_PERI_IP, + DIV_CLKCMU_RSP_CORE, + DIV_CLKCMU_TRFM_CORE, + DIV_CLKCMU_VCA_ACE, + DIV_CLKCMU_VCA_OD, + DIV_CLKCMU_VIO_CORE, + DIV_CLKCMU_VIP0_CORE, + DIV_CLKCMU_VIP1_CORE, + DIV_CLKCMU_VPP_CORE, + DIV_PLL_SHARED0_DIV2, + DIV_PLL_SHARED0_DIV3, + DIV_PLL_SHARED0_DIV4, + DIV_PLL_SHARED1_DIV2, + DIV_PLL_SHARED1_DIV3, + DIV_PLL_SHARED1_DIV4, +}; + +static const struct samsung_pll_rate_table artpec8_pll_audio_rates[] =3D { + PLL_36XX_RATE(25 * MHZ, 589823913U, 47, 1, 1, 12184), + PLL_36XX_RATE(25 * MHZ, 393215942U, 47, 3, 0, 12184), + PLL_36XX_RATE(25 * MHZ, 294911956U, 47, 1, 2, 12184), + PLL_36XX_RATE(25 * MHZ, 100000000U, 32, 2, 2, 0), + PLL_36XX_RATE(25 * MHZ, 98303985U, 47, 3, 2, 12184), + PLL_36XX_RATE(25 * MHZ, 49151992U, 47, 3, 3, 12184), +}; + +static const struct samsung_pll_clock cmu_cmu_pll_clks[] __initconst =3D { + PLL(pll_1017x, PLL_SHARED0, "fout_pll_shared0", "fin_pll", + PLL_LOCKTIME_PLL_SHARED0, PLL_CON0_PLL_SHARED0, NULL), + PLL(pll_1017x, PLL_SHARED1, "fout_pll_shared1", "fin_pll", + PLL_LOCKTIME_PLL_SHARED1, PLL_CON0_PLL_SHARED1, NULL), + PLL(pll_1031x, PLL_AUDIO, "fout_pll_audio", "fin_pll", + PLL_LOCKTIME_PLL_AUDIO, PLL_CON0_PLL_AUDIO, artpec8_pll_audio_rates), +}; + +PNAME(mout_clkcmu_bus_bus_p) =3D { + "dout_pll_shared1_div2", "dout_pll_shared0_div3", + "dout_pll_shared1_div3", "dout_pll_shared1_div4" }; +PNAME(mout_clkcmu_bus_dlp_p) =3D { + "dout_pll_shared0_div2", "dout_pll_shared0_div4", + "dout_pll_shared1_div2", "dout_pll_shared1_div4" }; +PNAME(mout_clkcmu_core_bus_p) =3D { + "dout_pll_shared1_div2", "dout_pll_shared0_div3", + "dout_pll_shared0_div4", "dout_pll_shared1_div3" }; +PNAME(mout_clkcmu_core_dlp_p) =3D { + "dout_pll_shared0_div2", "dout_pll_sahred1_div2", + "dout_pll_shared0_div3", "dout_pll_shared1_div3" }; +PNAME(mout_clkcmu_cpucl_switch_p) =3D { + "dout_pll_shared0_div2", "dout_pll_shared1_div2", + "dout_pll_shared0_div3", "dout_pll_shared1_div3" }; +PNAME(mout_clkcmu_fsys_bus_p) =3D { + "dout_pll_shared1_div2", "dout_pll_shared0_div2", + "dout_pll_shared1_div4", "dout_pll_shared1_div3" }; +PNAME(mout_clkcmu_fsys_ip_p) =3D { + "dout_pll_shared0_div2", "dout_pll_shared1_div3", + "dout_pll_shared1_div2", "dout_pll_shared0_div3" }; +PNAME(mout_clkcmu_fsys_sfmc_p) =3D { + "dout_pll_shared1_div3", "dout_pll_shared0_div2", + "dout_pll_shared1_div2", "dout_pll_shared0_div3" }; +PNAME(mout_clkcmu_fsys_scan0_p) =3D { + "dout_pll_shared0_div4", "dout_pll_shared1_div4" }; +PNAME(mout_clkcmu_fsys_scan1_p) =3D { + "dout_pll_shared0_div4", "dout_pll_shared1_div4" }; +PNAME(mout_clkcmu_imem_imem_p) =3D { + "dout_pll_shared1_div4", "dout_pll_shared0_div3", + "dout_pll_shared1_div3", "dout_pll_shared1_div2" }; +PNAME(mout_clkcmu_imem_jpeg_p) =3D { + "dout_pll_shared0_div2", "dout_pll_shared0_div3", + "dout_pll_shared1_div2", "dout_pll_shared1_div3" }; +PNAME(mout_clkcmu_cdc_core_p) =3D { + "dout_pll_shared1_div2", "dout_pll_shared0_div3", + "dout_pll_shared1_div3", "dout_pll_shared1_div4" }; +PNAME(mout_clkcmu_dlp_core_p) =3D { + "dout_pll_shared0_div2", "dout_pll_shared1_div2", + "dout_pll_shared0_div3", "dout_pll_shared1_div3" }; +PNAME(mout_clkcmu_3d_p) =3D { + "dout_pll_shared0_div2", "dout_pll_shared1_div2", + "dout_pll_shared0_div3", "dout_pll_shared1_div3" }; +PNAME(mout_clkcmu_2d_p) =3D { + "dout_pll_shared0_div2", "dout_pll_shared1_div2", + "dout_pll_shared0_div3", "dout_pll_shared1_div3" }; +PNAME(mout_clkcmu_mif_switch_p) =3D { + "dout_pll_shared0", "dout_pll_shared1", + "dout_pll_shared0_div2", "dout_pll_shared0_div3" }; +PNAME(mout_clkcmu_mif_busp_p) =3D { + "dout_pll_shared0_div3", "dout_pll_shared1_div4", + "dout_pll_shared0_div4", "dout_pll_shared0_div2" }; +PNAME(mout_clkcmu_peri_disp_p) =3D { + "dout_pll_shared1_div2", "dout_pll_shared0_div2", + "dout_pll_shared1_div4", "dout_pll_shared1_div3" }; +PNAME(mout_clkcmu_peri_ip_p) =3D { + "dout_pll_shared1_div2", "dout_pll_shared0_div4", + "dout_pll_shared1_div4", "dout_pll_shared0_div2" }; +PNAME(mout_clkcmu_rsp_core_p) =3D { + "dout_pll_shared1_div2", "dout_pll_shared0_div3", + "dout_pll_shared1_div3", "dout_pll_shared1_div4" }; +PNAME(mout_clkcmu_trfm_core_p) =3D { + "dout_pll_shared1_div2", "dout_pll_shared0_div3", + "dout_pll_shared1_div3", "dout_pll_shared1_div4" }; +PNAME(mout_clkcmu_vca_ace_p) =3D { + "dout_pll_shared1_div2", "dout_pll_shared0_div3", + "dout_pll_shared1_div3", "dout_pll_shared1_div4" }; +PNAME(mout_clkcmu_vca_od_p) =3D { + "dout_pll_shared1_div2", "dout_pll_shared0_div3", + "dout_pll_shared1_div3", "dout_pll_shared1_div4" }; +PNAME(mout_clkcmu_vio_core_p) =3D { + "dout_pll_shared0_div3", "dout_pll_shared0_div2", + "dout_pll_shared1_div2", "dout_pll_shared1_div3" }; +PNAME(mout_clkcmu_vip0_core_p) =3D { + "dout_pll_shared1_div2", "dout_pll_shared0_div3", + "dout_pll_shared1_div3", "dout_pll_shared1_div4" }; +PNAME(mout_clkcmu_vip1_core_p) =3D { + "dout_pll_shared1_div2", "dout_pll_shared0_div3", + "dout_pll_shared1_div3", "dout_pll_shared1_div4" }; +PNAME(mout_clkcmu_vpp_core_p) =3D { + "dout_pll_shared1_div2", "dout_pll_shared0_div3", + "dout_pll_shared1_div3", "dout_pll_shared1_div4" }; +PNAME(mout_clkcmu_pll_shared0_p) =3D { "fin_pll", "fout_pll_shared0" }; +PNAME(mout_clkcmu_pll_shared1_p) =3D { "fin_pll", "fout_pll_shared1" }; +PNAME(mout_clkcmu_pll_audio_p) =3D { "fin_pll", "fout_pll_audio" }; + +static const struct samsung_fixed_factor_clock cmu_fixed_factor_clks[] __i= nitconst =3D { + FFACTOR(DOUT_CLKCMU_OTP, "dout_clkcmu_otp", "fin_pll", 1, 8, 0), +}; + +static const struct samsung_mux_clock cmu_cmu_mux_clks[] __initconst =3D { + MUX(0, "mout_clkcmu_pll_shared0", mout_clkcmu_pll_shared0_p, + PLL_CON0_PLL_SHARED0, 4, 1), + MUX(0, "mout_clkcmu_pll_shared1", mout_clkcmu_pll_shared1_p, + PLL_CON0_PLL_SHARED1, 4, 1), + MUX(0, "mout_clkcmu_pll_audio", mout_clkcmu_pll_audio_p, + PLL_CON0_PLL_AUDIO, 4, 1), + MUX(0, "mout_clkcmu_bus_bus", mout_clkcmu_bus_bus_p, + MUX_CLKCMU_BUS_BUS, 0, 2), + MUX(0, "mout_clkcmu_bus_dlp", mout_clkcmu_bus_dlp_p, + MUX_CLKCMU_BUS_DLP, 0, 2), + MUX(0, "mout_clkcmu_core_bus", mout_clkcmu_core_bus_p, + MUX_CLKCMU_CORE_BUS, 0, 2), + MUX(0, "mout_clkcmu_core_dlp", mout_clkcmu_core_dlp_p, + MUX_CLKCMU_CORE_DLP, 0, 2), + MUX(0, "mout_clkcmu_cpucl_switch", mout_clkcmu_cpucl_switch_p, + MUX_CLKCMU_CPUCL_SWITCH, 0, 3), + MUX(0, "mout_clkcmu_fsys_bus", mout_clkcmu_fsys_bus_p, + MUX_CLKCMU_FSYS_BUS, 0, 2), + MUX(0, "mout_clkcmu_fsys_ip", mout_clkcmu_fsys_ip_p, + MUX_CLKCMU_FSYS_IP, 0, 2), + MUX(0, "mout_clkcmu_fsys_scan0", mout_clkcmu_fsys_scan0_p, + MUX_CLKCMU_FSYS_SCAN0, 0, 1), + MUX(0, "mout_clkcmu_fsys_scan1", mout_clkcmu_fsys_scan1_p, + MUX_CLKCMU_FSYS_SCAN1, 0, 1), + MUX(0, "mout_clkcmu_imem_imem", mout_clkcmu_imem_imem_p, + MUX_CLKCMU_IMEM_ACLK, 0, 2), + MUX(0, "mout_clkcmu_imem_jpeg", mout_clkcmu_imem_jpeg_p, + MUX_CLKCMU_IMEM_JPEG, 0, 2), + nMUX(0, "mout_clkcmu_cdc_core", mout_clkcmu_cdc_core_p, + MUX_CLKCMU_CDC_CORE, 0, 2), + nMUX(0, "mout_clkcmu_dlp_core", mout_clkcmu_dlp_core_p, + MUX_CLKCMU_DLP_CORE, 0, 2), + MUX(0, "mout_clkcmu_3d", mout_clkcmu_3d_p, + MUX_CLKCMU_3D, 0, 2), + MUX(0, "mout_clkcmu_2d", mout_clkcmu_2d_p, + MUX_CLKCMU_2D, 0, 2), + MUX(0, "mout_clkcmu_mif_switch", mout_clkcmu_mif_switch_p, + MUX_CLKCMU_MIF_SWITCH, 0, 2), + MUX(0, "mout_clkcmu_mif_busp", mout_clkcmu_mif_busp_p, + MUX_CLKCMU_MIF_BUSP, 0, 2), + MUX(0, "mout_clkcmu_peri_disp", mout_clkcmu_peri_disp_p, + MUX_CLKCMU_PERI_DISP, 0, 2), + MUX(0, "mout_clkcmu_peri_ip", mout_clkcmu_peri_ip_p, + MUX_CLKCMU_PERI_IP, 0, 2), + MUX(0, "mout_clkcmu_rsp_core", mout_clkcmu_rsp_core_p, + MUX_CLKCMU_RSP_CORE, 0, 2), + nMUX(0, "mout_clkcmu_trfm_core", mout_clkcmu_trfm_core_p, + MUX_CLKCMU_TRFM_CORE, 0, 2), + MUX(0, "mout_clkcmu_vca_ace", mout_clkcmu_vca_ace_p, + MUX_CLKCMU_VCA_ACE, 0, 2), + MUX(0, "mout_clkcmu_vca_od", mout_clkcmu_vca_od_p, + MUX_CLKCMU_VCA_OD, 0, 2), + MUX(0, "mout_clkcmu_vio_core", mout_clkcmu_vio_core_p, + MUX_CLKCMU_VIO_CORE, 0, 2), + nMUX(0, "mout_clkcmu_vip0_core", mout_clkcmu_vip0_core_p, + MUX_CLKCMU_VIP0_CORE, 0, 2), + nMUX(0, "mout_clkcmu_vip1_core", mout_clkcmu_vip1_core_p, + MUX_CLKCMU_VIP1_CORE, 0, 2), + nMUX(0, "mout_clkcmu_vpp_core", mout_clkcmu_vpp_core_p, + MUX_CLKCMU_VPP_CORE, 0, 2), +}; + +static const struct samsung_div_clock cmu_cmu_div_clks[] __initconst =3D { + DIV(DOUT_PLL_SHARED0_DIV2, "dout_pll_shared0_div2", + "mout_clkcmu_pll_shared0", DIV_PLL_SHARED0_DIV2, 0, 1), + DIV(DOUT_PLL_SHARED0_DIV3, "dout_pll_shared0_div3", + "mout_clkcmu_pll_shared0", DIV_PLL_SHARED0_DIV3, 0, 2), + DIV(DOUT_PLL_SHARED0_DIV4, "dout_pll_shared0_div4", + "dout_pll_shared0_div2", DIV_PLL_SHARED0_DIV4, 0, 1), + DIV(DOUT_PLL_SHARED1_DIV2, "dout_pll_shared1_div2", + "mout_clkcmu_pll_shared1", DIV_PLL_SHARED1_DIV2, 0, 1), + DIV(DOUT_PLL_SHARED1_DIV3, "dout_pll_shared1_div3", + "mout_clkcmu_pll_shared1", DIV_PLL_SHARED1_DIV3, 0, 2), + DIV(DOUT_PLL_SHARED1_DIV4, "dout_pll_shared1_div4", + "dout_pll_shared1_div2", DIV_PLL_SHARED1_DIV4, 0, 1), + DIV(DOUT_CLKCMU_BUS_BUS, "dout_clkcmu_bus_bus", + "mout_clkcmu_bus_bus", DIV_CLKCMU_BUS_BUS, 0, 4), + DIV(DOUT_CLKCMU_BUS_DLP, "dout_clkcmu_bus_dlp", + "mout_clkcmu_bus_dlp", DIV_CLKCMU_BUS_DLP, 0, 4), + DIV(DOUT_CLKCMU_CORE_MAIN, "dout_clkcmu_core_main", + "mout_clkcmu_core_bus", DIV_CLKCMU_CORE_MAIN, 0, 4), + DIV(DOUT_CLKCMU_CORE_DLP, "dout_clkcmu_core_dlp", + "mout_clkcmu_core_dlp", DIV_CLKCMU_CORE_DLP, 0, 4), + DIV(DOUT_CLKCMU_CPUCL_SWITCH, "dout_clkcmu_cpucl_switch", + "mout_clkcmu_cpucl_switch", DIV_CLKCMU_CPUCL_SWITCH, 0, 3), + DIV(DOUT_CLKCMU_FSYS_BUS, "dout_clkcmu_fsys_bus", + "mout_clkcmu_fsys_bus", DIV_CLKCMU_FSYS_BUS, 0, 4), + DIV(DOUT_CLKCMU_FSYS_IP, "dout_clkcmu_fsys_ip", + "mout_clkcmu_fsys_ip", DIV_CLKCMU_FSYS_IP, 0, 9), + DIV(DOUT_CLKCMU_FSYS_SCAN0, "dout_clkcmu_fsys_scan0", + "mout_clkcmu_fsys_scan0", DIV_CLKCMU_FSYS_SCAN0, 0, 4), + DIV(DOUT_CLKCMU_FSYS_SCAN1, "dout_clkcmu_fsys_scan1", + "mout_clkcmu_fsys_scan1", DIV_CLKCMU_FSYS_SCAN1, 0, 4), + DIV(DOUT_CLKCMU_IMEM_ACLK, "dout_clkcmu_imem_aclk", + "mout_clkcmu_imem_imem", DIV_CLKCMU_IMEM_ACLK, 0, 4), + DIV(DOUT_CLKCMU_IMEM_JPEG, "dout_clkcmu_imem_jpeg", + "mout_clkcmu_imem_jpeg", DIV_CLKCMU_IMEM_JPEG, 0, 4), + DIV_F(DOUT_CLKCMU_CDC_CORE, "dout_clkcmu_cdc_core", + "mout_clkcmu_cdc_core", DIV_CLKCMU_CDC_CORE, 0, 4, + CLK_SET_RATE_PARENT, 0), + DIV_F(DOUT_CLKCMU_DLP_CORE, "dout_clkcmu_dlp_core", + "mout_clkcmu_dlp_core", DIV_CLKCMU_DLP_CORE, 0, 4, + CLK_SET_RATE_PARENT, 0), + DIV(DOUT_CLKCMU_GPU_3D, "dout_clkcmu_gpu_3d", + "mout_clkcmu_3d", DIV_CLKCMU_GPU_3D, 0, 3), + DIV(DOUT_CLKCMU_GPU_2D, "dout_clkcmu_gpu_2d", + "mout_clkcmu_2d", DIV_CLKCMU_GPU_2D, 0, 4), + DIV(DOUT_CLKCMU_MIF_SWITCH, "dout_clkcmu_mif_switch", + "mout_clkcmu_mif_switch", DIV_CLKCMU_MIF_SWITCH, 0, 4), + DIV(DOUT_CLKCMU_MIF_BUSP, "dout_clkcmu_mif_busp", + "mout_clkcmu_mif_busp", DIV_CLKCMU_MIF_BUSP, 0, 3), + DIV(DOUT_CLKCMU_PERI_DISP, "dout_clkcmu_peri_disp", + "mout_clkcmu_peri_disp", DIV_CLKCMU_PERI_DISP, 0, 4), + DIV(DOUT_CLKCMU_PERI_IP, "dout_clkcmu_peri_ip", + "mout_clkcmu_peri_ip", DIV_CLKCMU_PERI_IP, 0, 4), + DIV(DOUT_CLKCMU_PERI_AUDIO, "dout_clkcmu_peri_audio", + "mout_clkcmu_pll_audio", DIV_CLKCMU_PERI_AUDIO, 0, 4), + DIV(DOUT_CLKCMU_RSP_CORE, "dout_clkcmu_rsp_core", + "mout_clkcmu_rsp_core", DIV_CLKCMU_RSP_CORE, 0, 4), + DIV_F(DOUT_CLKCMU_TRFM_CORE, "dout_clkcmu_trfm_core", + "mout_clkcmu_trfm_core", DIV_CLKCMU_TRFM_CORE, 0, 4, + CLK_SET_RATE_PARENT, 0), + DIV(DOUT_CLKCMU_VCA_ACE, "dout_clkcmu_vca_ace", + "mout_clkcmu_vca_ace", DIV_CLKCMU_VCA_ACE, 0, 4), + DIV(DOUT_CLKCMU_VCA_OD, "dout_clkcmu_vca_od", + "mout_clkcmu_vca_od", DIV_CLKCMU_VCA_OD, 0, 4), + DIV(DOUT_CLKCMU_VIO_CORE, "dout_clkcmu_vio_core", + "mout_clkcmu_vio_core", DIV_CLKCMU_VIO_CORE, 0, 4), + DIV(DOUT_CLKCMU_VIO_AUDIO, "dout_clkcmu_vio_audio", + "mout_clkcmu_pll_audio", DIV_CLKCMU_VIO_AUDIO, 0, 4), + DIV_F(DOUT_CLKCMU_VIP0_CORE, "dout_clkcmu_vip0_core", + "mout_clkcmu_vip0_core", DIV_CLKCMU_VIP0_CORE, 0, 4, + CLK_SET_RATE_PARENT, 0), + DIV_F(DOUT_CLKCMU_VIP1_CORE, "dout_clkcmu_vip1_core", + "mout_clkcmu_vip1_core", DIV_CLKCMU_VIP1_CORE, 0, 4, + CLK_SET_RATE_PARENT, 0), + DIV_F(DOUT_CLKCMU_VPP_CORE, "dout_clkcmu_vpp_core", + "mout_clkcmu_vpp_core", DIV_CLKCMU_VPP_CORE, 0, 4, + CLK_SET_RATE_PARENT, 0), +}; + +static const struct samsung_cmu_info cmu_cmu_info __initconst =3D { + .pll_clks =3D cmu_cmu_pll_clks, + .nr_pll_clks =3D ARRAY_SIZE(cmu_cmu_pll_clks), + .fixed_factor_clks =3D cmu_fixed_factor_clks, + .nr_fixed_factor_clks =3D ARRAY_SIZE(cmu_fixed_factor_clks), + .mux_clks =3D cmu_cmu_mux_clks, + .nr_mux_clks =3D ARRAY_SIZE(cmu_cmu_mux_clks), + .div_clks =3D cmu_cmu_div_clks, + .nr_div_clks =3D ARRAY_SIZE(cmu_cmu_div_clks), + .nr_clk_ids =3D CMU_CMU_NR_CLK, + .clk_regs =3D cmu_cmu_clk_regs, + .nr_clk_regs =3D ARRAY_SIZE(cmu_cmu_clk_regs), +}; + +static void __init artpec8_clk_cmu_cmu_init(struct device_node *np) +{ + samsung_cmu_register_one(np, &cmu_cmu_info); +} + +CLK_OF_DECLARE(artpec8_clk_cmu_cmu, "axis,artpec8-cmu-cmu", + artpec8_clk_cmu_cmu_init); + /* Register Offset definitions for CMU_IMEM (0x10010000) */ #define PLL_CON0_MUX_CLK_IMEM_ACLK_USER 0x0100 #define PLL_CON0_MUX_CLK_IMEM_JPEG_USER 0x0120 --=20 2.34.1 From nobody Tue Dec 23 12:18:25 2025 Received: from spam.coasia.com (mail2.coasia.com [112.168.119.159]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8CA511A29A for ; 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(ksk4725@coasia.com@115.23.218.194) by 192.168.10.159 with ESMTP; 10 Jul 2025 09:20:56 +0900 X-Original-SENDERIP: 115.23.218.194 X-Original-SENDERCOUNTRY: KR, South Korea X-Original-MAILFROM: ksk4725@coasia.com X-Original-RCPTTO: jesper.nilsson@axis.com, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, krzk@kernel.org, s.nawrocki@samsung.com, cw00.choi@samsung.com, alim.akhtar@samsung.com, linus.walleij@linaro.org, tomasz.figa@gmail.com, catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de, ravi.patel@samsung.com, ksk4725@coasia.com, smn1196@coasia.com, kenkim@coasia.com, pjsin865@coasia.com, gwk1013@coasia.com, hgkim05@coasia.com, mingyoungbo@coasia.com, pankaj.dubey@samsung.com, shradha.t@samsung.com, inbaraj.e@samsung.com, swathi.ks@samsung.com, hrishikesh.d@samsung.com, dj76.yang@samsung.com, hypmean.kim@samsung.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@axis.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, soc@lists.linux.dev, v.pavani@samsung.com From: ksk4725@coasia.com To: Jesper Nilsson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krzysztof Kozlowski , Sylwester Nawrocki , Chanwoo Choi , Alim Akhtar , Linus Walleij , Tomasz Figa , Catalin Marinas , Will Deacon , Arnd Bergmann , Ravi Patel , SeonGu Kang , SungMin Park Cc: kenkim , Jongshin Park , GunWoo Kim , HaGyeong Kim , GyoungBo Min , Pankaj Dubey , Shradha Todi , Inbaraj E , Swathi K S , Hrishikesh , Dongjin Yang , Sang Min Kim , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@axis.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, soc@lists.linux.dev, Varada Pavani Subject: [PATCH 06/16] clk: samsung: artpec-8: Add clock support for CMU_BUS block Date: Thu, 10 Jul 2025 09:20:36 +0900 Message-Id: <20250710002047.1573841-7-ksk4725@coasia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250710002047.1573841-1-ksk4725@coasia.com> References: <20250710002047.1573841-1-ksk4725@coasia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Hakyeong Kim Add clock support for below CMU block in ARTPEC-8 SoC. - CMU_BUS Signed-off-by: Varada Pavani Signed-off-by: Hakyeong Kim --- drivers/clk/samsung/clk-artpec8.c | 45 +++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/drivers/clk/samsung/clk-artpec8.c b/drivers/clk/samsung/clk-ar= tpec8.c index 1ef9e52ad24b..648abdd2f510 100644 --- a/drivers/clk/samsung/clk-artpec8.c +++ b/drivers/clk/samsung/clk-artpec8.c @@ -15,6 +15,7 @@ =20 /* NOTE: Must be equal to the last clock ID increased by one */ #define CMU_CMU_NR_CLK (DOUT_CLKCMU_VPP_CORE + 1) +#define CMU_BUS_NR_CLK (DOUT_CLK_BUS_PCLK + 1) #define CMU_IMEM_NR_CLK (MOUT_IMEM_JPEG_USER + 1) =20 /* register offset definitions for cmu_cmu (0x12400000) */ @@ -431,6 +432,50 @@ static void __init artpec8_clk_cmu_cmu_init(struct dev= ice_node *np) CLK_OF_DECLARE(artpec8_clk_cmu_cmu, "axis,artpec8-cmu-cmu", artpec8_clk_cmu_cmu_init); =20 +/* Register Offset definitions for CMU_BUS (0x12c10000) */ +#define PLL_CON0_MUX_CLK_BUS_ACLK_USER 0x0100 +#define PLL_CON0_MUX_CLK_BUS_DLP_USER 0x0120 +#define DIV_CLK_BUS_PCLK 0x1800 + +static const unsigned long cmu_bus_clk_regs[] __initconst =3D { + PLL_CON0_MUX_CLK_BUS_ACLK_USER, + PLL_CON0_MUX_CLK_BUS_DLP_USER, + DIV_CLK_BUS_PCLK, +}; + +PNAME(mout_clk_bus_aclk_user_p) =3D { "fin_pll", "dout_clkcmu_bus_bus" }; +PNAME(mout_clk_bus_dlp_user_p) =3D { "fin_pll", "dout_clkcmu_bus_dlp" }; + +static const struct samsung_mux_clock cmu_bus_mux_clks[] __initconst =3D { + MUX(MOUT_CLK_BUS_ACLK_USER, "mout_clk_bus_aclk_user", + mout_clk_bus_aclk_user_p, PLL_CON0_MUX_CLK_BUS_ACLK_USER, 4, 1), + MUX(MOUT_CLK_BUS_DLP_USER, "mout_clk_bus_dlp_user", + mout_clk_bus_dlp_user_p, PLL_CON0_MUX_CLK_BUS_DLP_USER, 4, 1), +}; + +static const struct samsung_div_clock cmu_bus_div_clks[] __initconst =3D { + DIV(DOUT_CLK_BUS_PCLK, "dout_clk_bus_pclk", "mout_clk_bus_aclk_user", + DIV_CLK_BUS_PCLK, 0, 4), +}; + +static const struct samsung_cmu_info cmu_bus_info __initconst =3D { + .mux_clks =3D cmu_bus_mux_clks, + .nr_mux_clks =3D ARRAY_SIZE(cmu_bus_mux_clks), + .div_clks =3D cmu_bus_div_clks, + .nr_div_clks =3D ARRAY_SIZE(cmu_bus_div_clks), + .nr_clk_ids =3D CMU_BUS_NR_CLK, + .clk_regs =3D cmu_bus_clk_regs, + .nr_clk_regs =3D ARRAY_SIZE(cmu_bus_clk_regs), +}; + +static void __init artpec8_clk_cmu_bus_init(struct device_node *np) +{ + samsung_cmu_register_one(np, &cmu_bus_info); +} + +CLK_OF_DECLARE(artpec8_clk_cmu_bus, "axis,artpec8-cmu-bus", + artpec8_clk_cmu_bus_init); + /* Register Offset definitions for CMU_IMEM (0x10010000) */ #define PLL_CON0_MUX_CLK_IMEM_ACLK_USER 0x0100 #define PLL_CON0_MUX_CLK_IMEM_JPEG_USER 0x0120 --=20 2.34.1 From nobody Tue Dec 23 12:18:25 2025 Received: from spam.coasia.com (mail2.coasia.com [112.168.119.159]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 61E321EB36 for ; Thu, 10 Jul 2025 00:20:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=112.168.119.159 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752106863; cv=none; b=nQCjx3G09dylLeaTlA2l/oc5JSGxt9KBTW7fwM3KVHsNiPk6yysEmGaSbCE3kxjgVQog0hU+oY4LKxm+we9/QeV62/dEegCustsk2dDgMd+ybghCOjO2kYdvDg4CCwKDf8iD1WMjGfwqQGfYgeMl4rsygwwzBTjZjtARND8Pugk= ARC-Message-Signature: i=1; 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(ksk4725@coasia.com@115.23.218.194) by 192.168.10.159 with ESMTP; 10 Jul 2025 09:20:58 +0900 X-Original-SENDERIP: 115.23.218.194 X-Original-SENDERCOUNTRY: KR, South Korea X-Original-MAILFROM: ksk4725@coasia.com X-Original-RCPTTO: jesper.nilsson@axis.com, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, krzk@kernel.org, s.nawrocki@samsung.com, cw00.choi@samsung.com, alim.akhtar@samsung.com, linus.walleij@linaro.org, tomasz.figa@gmail.com, catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de, ravi.patel@samsung.com, ksk4725@coasia.com, smn1196@coasia.com, kenkim@coasia.com, pjsin865@coasia.com, gwk1013@coasia.com, hgkim05@coasia.com, mingyoungbo@coasia.com, pankaj.dubey@samsung.com, shradha.t@samsung.com, inbaraj.e@samsung.com, swathi.ks@samsung.com, hrishikesh.d@samsung.com, dj76.yang@samsung.com, hypmean.kim@samsung.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@axis.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, soc@lists.linux.dev, v.pavani@samsung.com From: ksk4725@coasia.com To: Jesper Nilsson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krzysztof Kozlowski , Sylwester Nawrocki , Chanwoo Choi , Alim Akhtar , Linus Walleij , Tomasz Figa , Catalin Marinas , Will Deacon , Arnd Bergmann , Ravi Patel , SeonGu Kang , SungMin Park Cc: kenkim , Jongshin Park , GunWoo Kim , HaGyeong Kim , GyoungBo Min , Pankaj Dubey , Shradha Todi , Inbaraj E , Swathi K S , Hrishikesh , Dongjin Yang , Sang Min Kim , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@axis.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, soc@lists.linux.dev, Varada Pavani Subject: [PATCH 07/16] clk: samsung: artpec-8: Add clock support for CMU_CORE block Date: Thu, 10 Jul 2025 09:20:37 +0900 Message-Id: <20250710002047.1573841-8-ksk4725@coasia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250710002047.1573841-1-ksk4725@coasia.com> References: <20250710002047.1573841-1-ksk4725@coasia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Hakyeong Kim Add clock support for below CMU block in ARTPEC-8 SoC. - CMU_CORE Signed-off-by: Varada Pavani Signed-off-by: Hakyeong Kim --- drivers/clk/samsung/clk-artpec8.c | 45 +++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/drivers/clk/samsung/clk-artpec8.c b/drivers/clk/samsung/clk-ar= tpec8.c index 648abdd2f510..f41b7941c630 100644 --- a/drivers/clk/samsung/clk-artpec8.c +++ b/drivers/clk/samsung/clk-artpec8.c @@ -16,6 +16,7 @@ /* NOTE: Must be equal to the last clock ID increased by one */ #define CMU_CMU_NR_CLK (DOUT_CLKCMU_VPP_CORE + 1) #define CMU_BUS_NR_CLK (DOUT_CLK_BUS_PCLK + 1) +#define CMU_CORE_NR_CLK (DOUT_CLK_CORE_PCLK + 1) #define CMU_IMEM_NR_CLK (MOUT_IMEM_JPEG_USER + 1) =20 /* register offset definitions for cmu_cmu (0x12400000) */ @@ -476,6 +477,50 @@ static void __init artpec8_clk_cmu_bus_init(struct dev= ice_node *np) CLK_OF_DECLARE(artpec8_clk_cmu_bus, "axis,artpec8-cmu-bus", artpec8_clk_cmu_bus_init); =20 +/* Register Offset definitions for CMU_CORE (0x12410000) */ +#define PLL_CON0_MUX_CLK_CORE_ACLK_USER 0x0100 +#define PLL_CON0_MUX_CLK_CORE_DLP_USER 0x0120 +#define DIV_CLK_CORE_PCLK 0x1800 + +static const unsigned long cmu_core_clk_regs[] __initconst =3D { + PLL_CON0_MUX_CLK_CORE_ACLK_USER, + PLL_CON0_MUX_CLK_CORE_DLP_USER, + DIV_CLK_CORE_PCLK, +}; + +PNAME(mout_clk_core_aclk_user_p) =3D { "fin_pll", "dout_clkcmu_core_main" = }; +PNAME(mout_clk_core_dlp_user_p) =3D { "fin_pll", "dout_clkcmu_core_dlp" }; + +static const struct samsung_mux_clock cmu_core_mux_clks[] __initconst =3D { + MUX(MOUT_CLK_CORE_ACLK_USER, "mout_clk_core_aclk_user", + mout_clk_core_aclk_user_p, PLL_CON0_MUX_CLK_CORE_ACLK_USER, 4, 1), + MUX(MOUT_CLK_CORE_DLP_USER, "mout_clk_core_dlp_user", + mout_clk_core_dlp_user_p, PLL_CON0_MUX_CLK_CORE_DLP_USER, 4, 1), +}; + +static const struct samsung_div_clock cmu_core_div_clks[] __initconst =3D { + DIV(DOUT_CLK_CORE_PCLK, "dout_clk_core_pclk", + "mout_clk_core_aclk_user", DIV_CLK_CORE_PCLK, 0, 4), +}; + +static const struct samsung_cmu_info cmu_core_info __initconst =3D { + .mux_clks =3D cmu_core_mux_clks, + .nr_mux_clks =3D ARRAY_SIZE(cmu_core_mux_clks), + .div_clks =3D cmu_core_div_clks, + .nr_div_clks =3D ARRAY_SIZE(cmu_core_div_clks), + .nr_clk_ids =3D CMU_CORE_NR_CLK, + .clk_regs =3D cmu_core_clk_regs, + .nr_clk_regs =3D ARRAY_SIZE(cmu_core_clk_regs), +}; + +static void __init artpec8_clk_cmu_core_init(struct device_node *np) +{ + samsung_cmu_register_one(np, &cmu_core_info); +} + +CLK_OF_DECLARE(artpec8_clk_cmu_core, "axis,artpec8-cmu-core", + artpec8_clk_cmu_core_init); + /* Register Offset definitions for CMU_IMEM (0x10010000) */ #define PLL_CON0_MUX_CLK_IMEM_ACLK_USER 0x0100 #define PLL_CON0_MUX_CLK_IMEM_JPEG_USER 0x0120 --=20 2.34.1 From nobody Tue Dec 23 12:18:25 2025 Received: from spam.coasia.com (mail2.coasia.com [112.168.119.159]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8CC352576 for ; Thu, 10 Jul 2025 00:21:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=112.168.119.159 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752106866; cv=none; b=arO9sPkn+09cuOVb7KyAcEglsjiQN99Ao16/7FWMiTCXv8J9kfxDbHWTZur5OQ2HPviy8UtO6BdNMavHb+7KOwCoiJNdzeIHOoVBU/2XvWRBXsO7lTiCOO96+W+ufzOiknCW6pcO8TNiBymBmrHdrc58pmrahw6v8jlwCqbWw/4= ARC-Message-Signature: i=1; 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(ksk4725@coasia.com@115.23.218.194) by 192.168.10.159 with ESMTP; 10 Jul 2025 09:20:58 +0900 X-Original-SENDERIP: 115.23.218.194 X-Original-SENDERCOUNTRY: KR, South Korea X-Original-MAILFROM: ksk4725@coasia.com X-Original-RCPTTO: jesper.nilsson@axis.com, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, krzk@kernel.org, s.nawrocki@samsung.com, cw00.choi@samsung.com, alim.akhtar@samsung.com, linus.walleij@linaro.org, tomasz.figa@gmail.com, catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de, ravi.patel@samsung.com, ksk4725@coasia.com, smn1196@coasia.com, kenkim@coasia.com, pjsin865@coasia.com, gwk1013@coasia.com, hgkim05@coasia.com, mingyoungbo@coasia.com, pankaj.dubey@samsung.com, shradha.t@samsung.com, inbaraj.e@samsung.com, swathi.ks@samsung.com, hrishikesh.d@samsung.com, dj76.yang@samsung.com, hypmean.kim@samsung.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@axis.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, soc@lists.linux.dev, v.pavani@samsung.com From: ksk4725@coasia.com To: Jesper Nilsson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krzysztof Kozlowski , Sylwester Nawrocki , Chanwoo Choi , Alim Akhtar , Linus Walleij , Tomasz Figa , Catalin Marinas , Will Deacon , Arnd Bergmann , Ravi Patel , SeonGu Kang , SungMin Park Cc: kenkim , Jongshin Park , GunWoo Kim , HaGyeong Kim , GyoungBo Min , Pankaj Dubey , Shradha Todi , Inbaraj E , Swathi K S , Hrishikesh , Dongjin Yang , Sang Min Kim , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@axis.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, soc@lists.linux.dev, Varada Pavani Subject: [PATCH 08/16] clk: samsung: artpec-8: Add clock support for CMU_CPUCL block Date: Thu, 10 Jul 2025 09:20:38 +0900 Message-Id: <20250710002047.1573841-9-ksk4725@coasia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250710002047.1573841-1-ksk4725@coasia.com> References: <20250710002047.1573841-1-ksk4725@coasia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Hakyeong Kim Add clock support for below CMU block in ARTPEC-8 SoC. - CMU_CPUCL Signed-off-by: Varada Pavani Signed-off-by: Hakyeong Kim --- drivers/clk/samsung/clk-artpec8.c | 99 +++++++++++++++++++++++++++++++ 1 file changed, 99 insertions(+) diff --git a/drivers/clk/samsung/clk-artpec8.c b/drivers/clk/samsung/clk-ar= tpec8.c index f41b7941c630..15c90fe29308 100644 --- a/drivers/clk/samsung/clk-artpec8.c +++ b/drivers/clk/samsung/clk-artpec8.c @@ -17,6 +17,7 @@ #define CMU_CMU_NR_CLK (DOUT_CLKCMU_VPP_CORE + 1) #define CMU_BUS_NR_CLK (DOUT_CLK_BUS_PCLK + 1) #define CMU_CORE_NR_CLK (DOUT_CLK_CORE_PCLK + 1) +#define CMU_CPUCL_NR_CLK (DOUT_CLK_CPUCL_PCLKDBG + 1) #define CMU_IMEM_NR_CLK (MOUT_IMEM_JPEG_USER + 1) =20 /* register offset definitions for cmu_cmu (0x12400000) */ @@ -521,6 +522,104 @@ static void __init artpec8_clk_cmu_core_init(struct d= evice_node *np) CLK_OF_DECLARE(artpec8_clk_cmu_core, "axis,artpec8-cmu-core", artpec8_clk_cmu_core_init); =20 +/* Register Offset definitions for CMU_CPUCL (0x11410000) */ +#define PLL_LOCKTIME_PLL_CPUCL 0x0000 +#define PLL_CON0_MUX_CLKCMU_CPUCL_SWITCH_USER 0x0120 +#define PLL_CON0_PLL_CPUCL 0x0140 +#define MUX_CLK_CPUCL_PLL 0x1000 +#define DIV_CLK_CLUSTER_ACLK 0x1800 +#define DIV_CLK_CLUSTER_CNTCLK 0x1804 +#define DIV_CLK_CLUSTER_PCLKDBG 0x1808 +#define DIV_CLK_CPUCL_CMUREF 0x180c +#define DIV_CLK_CPUCL_PCLK 0x1814 +#define DIV_CLK_CLUSTER_ATCLK 0x1818 +#define DIV_CLK_CPUCL_DBG 0x181c +#define DIV_CLK_CPUCL_PCLKDBG 0x1820 + +static const unsigned long cmu_cpucl_clk_regs[] __initconst =3D { + PLL_LOCKTIME_PLL_CPUCL, + PLL_CON0_MUX_CLKCMU_CPUCL_SWITCH_USER, + PLL_CON0_PLL_CPUCL, + MUX_CLK_CPUCL_PLL, + DIV_CLK_CLUSTER_ACLK, + DIV_CLK_CLUSTER_CNTCLK, + DIV_CLK_CLUSTER_PCLKDBG, + DIV_CLK_CPUCL_CMUREF, + DIV_CLK_CPUCL_PCLK, + DIV_CLK_CLUSTER_ATCLK, + DIV_CLK_CPUCL_DBG, + DIV_CLK_CPUCL_PCLKDBG, +}; + +static const struct samsung_pll_clock cmu_cpucl_pll_clks[] __initconst =3D= { + PLL(pll_1017x, PLL_CPUCL, "fout_pll_cpucl", "fin_pll", + PLL_LOCKTIME_PLL_CPUCL, PLL_CON0_PLL_CPUCL, NULL), +}; + +PNAME(mout_clkcmu_cpucl_switch_user_p) =3D { + "fin_pll", "dout_clkcmu_cpucl_switch" }; +PNAME(mout_pll_cpucl_p) =3D { + "fin_pll", "fout_pll_cpucl" }; +PNAME(mout_clk_cpucl_pll_p) =3D { + "mout_pll_cpucl", "mout_clkcmu_cpucl_switch_user" }; + +static const struct samsung_mux_clock cmu_cpucl_mux_clks[] __initconst =3D= { + MUX_F(0, "mout_pll_cpucl", mout_pll_cpucl_p, + PLL_CON0_PLL_CPUCL, 4, 1, + CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0), + MUX(MOUT_CLKCMU_CPUCL_SWITCH_USER, "mout_clkcmu_cpucl_switch_user", + mout_clkcmu_cpucl_switch_user_p, + PLL_CON0_MUX_CLKCMU_CPUCL_SWITCH_USER, 4, 1), + MUX_F(MOUT_CLK_CPUCL_PLL, "mout_clk_cpucl_pll", mout_clk_cpucl_pll_p, + MUX_CLK_CPUCL_PLL, 0, 1, CLK_SET_RATE_PARENT, 0), +}; + +static const struct samsung_fixed_factor_clock cpucl_ffactor_clks[] __init= const =3D { + FFACTOR(DOUT_CLK_CPUCL_CPU, "dout_clk_cpucl_cpu", + "mout_clk_cpucl_pll", 1, 1, CLK_SET_RATE_PARENT), +}; + +static const struct samsung_div_clock cmu_cpucl_div_clks[] __initconst =3D= { + DIV(DOUT_CLK_CLUSTER_ACLK, "dout_clk_cluster_aclk", + "dout_clk_cpucl_cpu", DIV_CLK_CLUSTER_ACLK, 0, 4), + DIV(DOUT_CLK_CLUSTER_PCLKDBG, "dout_clk_cluster_pclkdbg", + "dout_clk_cpucl_cpu", DIV_CLK_CLUSTER_PCLKDBG, 0, 4), + DIV(DOUT_CLK_CLUSTER_CNTCLK, "dout_clk_cluster_cntclk", + "dout_clk_cpucl_cpu", DIV_CLK_CLUSTER_CNTCLK, 0, 4), + DIV(DOUT_CLK_CLUSTER_ATCLK, "dout_clk_cluster_atclk", + "dout_clk_cpucl_cpu", DIV_CLK_CLUSTER_ATCLK, 0, 4), + DIV(DOUT_CLK_CPUCL_PCLK, "dout_clk_cpucl_pclk", + "dout_clk_cpucl_cpu", DIV_CLK_CPUCL_PCLK, 0, 4), + DIV(DOUT_CLK_CPUCL_CMUREF, "dout_clk_cpucl_cmuref", + "dout_clk_cpucl_cpu", DIV_CLK_CPUCL_CMUREF, 0, 3), + DIV(DOUT_CLK_CPUCL_DBG, "dout_clk_cpucl_dbg", + "dout_clk_cpucl_cpu", DIV_CLK_CPUCL_DBG, 0, 4), + DIV(DOUT_CLK_CPUCL_PCLKDBG, "dout_clk_cpucl_pclkdbg", + "dout_clk_cpucl_dbg", DIV_CLK_CPUCL_PCLKDBG, 0, 4), +}; + +static const struct samsung_cmu_info cmu_cpucl_info __initconst =3D { + .pll_clks =3D cmu_cpucl_pll_clks, + .nr_pll_clks =3D ARRAY_SIZE(cmu_cpucl_pll_clks), + .fixed_factor_clks =3D cpucl_ffactor_clks, + .nr_fixed_factor_clks =3D ARRAY_SIZE(cpucl_ffactor_clks), + .mux_clks =3D cmu_cpucl_mux_clks, + .nr_mux_clks =3D ARRAY_SIZE(cmu_cpucl_mux_clks), + .div_clks =3D cmu_cpucl_div_clks, + .nr_div_clks =3D ARRAY_SIZE(cmu_cpucl_div_clks), + .nr_clk_ids =3D CMU_CPUCL_NR_CLK, + .clk_regs =3D cmu_cpucl_clk_regs, + .nr_clk_regs =3D ARRAY_SIZE(cmu_cpucl_clk_regs), +}; + +static void __init artpec8_clk_cmu_cpucl_init(struct device_node *np) +{ + samsung_cmu_register_one(np, &cmu_cpucl_info); +} + +CLK_OF_DECLARE(artpec8_clk_cmu_cpucl, "axis,artpec8-cmu-cpucl", + artpec8_clk_cmu_cpucl_init); + /* Register Offset definitions for CMU_IMEM (0x10010000) */ #define PLL_CON0_MUX_CLK_IMEM_ACLK_USER 0x0100 #define PLL_CON0_MUX_CLK_IMEM_JPEG_USER 0x0120 --=20 2.34.1 From nobody Tue Dec 23 12:18:25 2025 Received: from spam.coasia.com (mail2.coasia.com [112.168.119.159]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 308D2469D for ; Thu, 10 Jul 2025 00:27:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=112.168.119.159 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752107263; cv=none; b=rERtCM22jlP5bemX3Kt68adfOZEnTfWfZu2XgAkkalqc0Td22W4FEPHyIasJPRow6qaLnJCBfko7wKTvUGSEvK5Gq0M7A2+Rw78qrq1Mmk6hoeagcQduwW1xcqQtG4oeXTpdrwK5Y6Qf8+r6GuGZSWi9uph3cVUG2kQkUkiQq40= ARC-Message-Signature: i=1; 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(ksk4725@coasia.com@115.23.218.194) by 192.168.10.159 with ESMTP; 10 Jul 2025 09:20:59 +0900 X-Original-SENDERIP: 115.23.218.194 X-Original-SENDERCOUNTRY: KR, South Korea X-Original-MAILFROM: ksk4725@coasia.com X-Original-RCPTTO: jesper.nilsson@axis.com, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, krzk@kernel.org, s.nawrocki@samsung.com, cw00.choi@samsung.com, alim.akhtar@samsung.com, linus.walleij@linaro.org, tomasz.figa@gmail.com, catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de, ravi.patel@samsung.com, ksk4725@coasia.com, smn1196@coasia.com, kenkim@coasia.com, pjsin865@coasia.com, gwk1013@coasia.com, hgkim05@coasia.com, mingyoungbo@coasia.com, pankaj.dubey@samsung.com, shradha.t@samsung.com, inbaraj.e@samsung.com, swathi.ks@samsung.com, hrishikesh.d@samsung.com, dj76.yang@samsung.com, hypmean.kim@samsung.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@axis.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, soc@lists.linux.dev, v.pavani@samsung.com From: ksk4725@coasia.com To: Jesper Nilsson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krzysztof Kozlowski , Sylwester Nawrocki , Chanwoo Choi , Alim Akhtar , Linus Walleij , Tomasz Figa , Catalin Marinas , Will Deacon , Arnd Bergmann , Ravi Patel , SeonGu Kang , SungMin Park Cc: kenkim , Jongshin Park , GunWoo Kim , HaGyeong Kim , GyoungBo Min , Pankaj Dubey , Shradha Todi , Inbaraj E , Swathi K S , Hrishikesh , Dongjin Yang , Sang Min Kim , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@axis.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, soc@lists.linux.dev, Varada Pavani Subject: [PATCH 09/16] clk: samsung: artpec-8: Add clock support for CMU_FSYS block Date: Thu, 10 Jul 2025 09:20:39 +0900 Message-Id: <20250710002047.1573841-10-ksk4725@coasia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250710002047.1573841-1-ksk4725@coasia.com> References: <20250710002047.1573841-1-ksk4725@coasia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Hakyeong Kim Add clock support for below CMU block in ARTPEC-8 SoC. - CMU_FSYS Signed-off-by: Varada Pavani Signed-off-by: Hakyeong Kim --- drivers/clk/samsung/clk-artpec8.c | 134 ++++++++++++++++++++++++++++++ 1 file changed, 134 insertions(+) diff --git a/drivers/clk/samsung/clk-artpec8.c b/drivers/clk/samsung/clk-ar= tpec8.c index 15c90fe29308..7ccec4ff8f70 100644 --- a/drivers/clk/samsung/clk-artpec8.c +++ b/drivers/clk/samsung/clk-artpec8.c @@ -18,6 +18,7 @@ #define CMU_BUS_NR_CLK (DOUT_CLK_BUS_PCLK + 1) #define CMU_CORE_NR_CLK (DOUT_CLK_CORE_PCLK + 1) #define CMU_CPUCL_NR_CLK (DOUT_CLK_CPUCL_PCLKDBG + 1) +#define CMU_FSYS_NR_CLK (DOUT_SCAN_CLK_FSYS_MMC + 1) #define CMU_IMEM_NR_CLK (MOUT_IMEM_JPEG_USER + 1) =20 /* register offset definitions for cmu_cmu (0x12400000) */ @@ -620,6 +621,139 @@ static void __init artpec8_clk_cmu_cpucl_init(struct = device_node *np) CLK_OF_DECLARE(artpec8_clk_cmu_cpucl, "axis,artpec8-cmu-cpucl", artpec8_clk_cmu_cpucl_init); =20 +/* Register Offset definitions for CMU_FSYS (0x16c10000) */ +#define PLL_LOCKTIME_PLL_FSYS 0x0004 +#define PLL_CON0_MUX_CLK_FSYS_BUS_USER 0x0120 +#define PLL_CON0_MUX_CLK_FSYS_MMC_USER 0x0140 +#define PLL_CON0_MUX_CLK_FSYS_SCAN0_USER 0x0160 +#define PLL_CON0_MUX_CLK_FSYS_SCAN1_USER 0x0180 +#define PLL_CON0_PLL_FSYS 0x01c0 +#define DIV_CLK_FSYS_ADC 0x1804 +#define DIV_CLK_FSYS_BUS300 0x1808 +#define DIV_CLK_FSYS_BUS_QSPI 0x180c +#define DIV_CLK_FSYS_EQOS_25 0x1810 +#define DIV_CLK_FSYS_EQOS_2P5 0x1814 +#define DIV_CLK_FSYS_EQOS_500 0x1818 +#define DIV_CLK_FSYS_EQOS_INT125 0x181c +#define DIV_CLK_FSYS_MMC_CARD0 0x1820 +#define DIV_CLK_FSYS_MMC_CARD1 0x1824 +#define DIV_CLK_FSYS_OTP_MEM 0x1828 +#define DIV_CLK_FSYS_PCIE_PHY_REFCLK_SYSPLL 0x182c +#define DIV_CLK_FSYS_QSPI 0x1830 +#define DIV_CLK_FSYS_SCLK_UART 0x1834 +#define DIV_CLK_FSYS_SFMC_NAND 0x1838 +#define DIV_SCAN_CLK_FSYS_125 0x183c +#define DIV_SCAN_CLK_FSYS_MMC 0x1840 +#define DIV_SCAN_CLK_FSYS_PCIE_PIPE 0x1844 + +static const unsigned long cmu_fsys_clk_regs[] __initconst =3D { + PLL_LOCKTIME_PLL_FSYS, + PLL_CON0_MUX_CLK_FSYS_BUS_USER, + PLL_CON0_MUX_CLK_FSYS_MMC_USER, + PLL_CON0_MUX_CLK_FSYS_SCAN0_USER, + PLL_CON0_MUX_CLK_FSYS_SCAN1_USER, + PLL_CON0_PLL_FSYS, + DIV_CLK_FSYS_ADC, + DIV_CLK_FSYS_BUS300, + DIV_CLK_FSYS_BUS_QSPI, + DIV_CLK_FSYS_EQOS_25, + DIV_CLK_FSYS_EQOS_2P5, + DIV_CLK_FSYS_EQOS_500, + DIV_CLK_FSYS_EQOS_INT125, + DIV_CLK_FSYS_MMC_CARD0, + DIV_CLK_FSYS_MMC_CARD1, + DIV_CLK_FSYS_OTP_MEM, + DIV_CLK_FSYS_PCIE_PHY_REFCLK_SYSPLL, + DIV_CLK_FSYS_QSPI, + DIV_CLK_FSYS_SCLK_UART, + DIV_CLK_FSYS_SFMC_NAND, + DIV_SCAN_CLK_FSYS_125, + DIV_SCAN_CLK_FSYS_MMC, + DIV_SCAN_CLK_FSYS_PCIE_PIPE, +}; + +static const struct samsung_pll_clock cmu_fsys_pll_clks[] __initconst =3D { + PLL(pll_1017x, PLL_FSYS, "fout_pll_fsys", "fin_pll", + PLL_LOCKTIME_PLL_FSYS, PLL_CON0_PLL_FSYS, NULL), +}; + +PNAME(mout_fsys_scan0_user_p) =3D { "fin_pll", "dout_clkcmu_fsys_scan0" }; +PNAME(mout_fsys_scan1_user_p) =3D { "fin_pll", "dout_clkcmu_fsys_scan1" }; +PNAME(mout_fsys_bus_user_p) =3D { "fin_pll", "dout_clkcmu_fsys_bus" }; +PNAME(mout_fsys_mmc_user_p) =3D { "fin_pll", "dout_clkcmu_fsys_ip" }; +PNAME(mout_fsys_pll_fsys_p) =3D { "fin_pll", "fout_pll_fsys" }; + +static const struct samsung_mux_clock cmu_fsys_mux_clks[] __initconst =3D { + MUX(0, "mout_clk_pll_fsys", mout_fsys_pll_fsys_p, PLL_CON0_PLL_FSYS, 4, 1= ), + MUX(MOUT_FSYS_SCAN0_USER, "mout_fsys_scan0_user", + mout_fsys_scan0_user_p, PLL_CON0_MUX_CLK_FSYS_SCAN0_USER, 4, 1), + MUX(MOUT_FSYS_SCAN1_USER, "mout_fsys_scan1_user", + mout_fsys_scan1_user_p, PLL_CON0_MUX_CLK_FSYS_SCAN1_USER, 4, 1), + MUX(MOUT_FSYS_BUS_USER, "mout_fsys_bus_user", + mout_fsys_bus_user_p, PLL_CON0_MUX_CLK_FSYS_BUS_USER, 4, 1), + MUX(MOUT_FSYS_MMC_USER, "mout_fsys_mmc_user", + mout_fsys_mmc_user_p, PLL_CON0_MUX_CLK_FSYS_MMC_USER, 4, 1), +}; + +static const struct samsung_div_clock cmu_fsys_div_clks[] __initconst =3D { + DIV(DOUT_FSYS_PCIE_PIPE, "dout_fsys_pcie_pipe", "mout_clk_pll_fsys", + DIV_SCAN_CLK_FSYS_PCIE_PIPE, 0, 4), + DIV(DOUT_FSYS_ADC, "dout_fsys_adc", "mout_clk_pll_fsys", + DIV_CLK_FSYS_ADC, 0, 7), + DIV(DOUT_FSYS_PCIE_PHY_REFCLK_SYSPLL, + "dout_fsys_pcie_phy_refclk_syspll", "mout_clk_pll_fsys", + DIV_CLK_FSYS_PCIE_PHY_REFCLK_SYSPLL, 0, 8), + DIV(DOUT_FSYS_QSPI, "dout_fsys_qspi", "mout_fsys_mmc_user", + DIV_CLK_FSYS_QSPI, 0, 4), + DIV(DOUT_FSYS_EQOS_INT125, "dout_fsys_eqos_int125", "mout_clk_pll_fsys", + DIV_CLK_FSYS_EQOS_INT125, 0, 4), + DIV(DOUT_FSYS_OTP_MEM, "dout_fsys_otp_mem", "fin_pll", + DIV_CLK_FSYS_OTP_MEM, 0, 9), + DIV(DOUT_FSYS_SCLK_UART, "dout_fsys_sclk_uart", "mout_clk_pll_fsys", + DIV_CLK_FSYS_SCLK_UART, 0, 10), + DIV(DOUT_FSYS_SFMC_NAND, "dout_fsys_sfmc_nand", "mout_fsys_mmc_user", + DIV_CLK_FSYS_SFMC_NAND, 0, 4), + DIV(DOUT_SCAN_CLK_FSYS_125, + "dout_scan_clk_fsys_125", "mout_clk_pll_fsys", + DIV_SCAN_CLK_FSYS_125, 0, 4), + DIV(DOUT_SCAN_CLK_FSYS_MMC, "dout_scan_clk_fsys_mmc", "fout_pll_fsys", + DIV_SCAN_CLK_FSYS_MMC, 0, 4), + DIV(DOUT_FSYS_EQOS_25, "dout_fsys_eqos_25", "dout_fsys_eqos_int125", + DIV_CLK_FSYS_EQOS_25, 0, 4), + DIV_F(DOUT_FSYS_EQOS_2p5, "dout_fsys_eqos_2p5", "dout_fsys_eqos_25", + DIV_CLK_FSYS_EQOS_2P5, 0, 4, CLK_SET_RATE_PARENT, 0), + DIV(0, "dout_fsys_eqos_500", "mout_clk_pll_fsys", + DIV_CLK_FSYS_EQOS_500, 0, 4), + DIV(DOUT_FSYS_BUS300, "dout_fsys_bus300", "mout_fsys_bus_user", + DIV_CLK_FSYS_BUS300, 0, 4), + DIV(DOUT_FSYS_BUS_QSPI, "dout_fsys_bus_qspi", "mout_fsys_mmc_user", + DIV_CLK_FSYS_BUS_QSPI, 0, 4), + DIV(DOUT_FSYS_MMC_CARD0, "dout_fsys_mmc_card0", "mout_fsys_mmc_user", + DIV_CLK_FSYS_MMC_CARD0, 0, 10), + DIV(DOUT_FSYS_MMC_CARD1, "dout_fsys_mmc_card1", "mout_fsys_mmc_user", + DIV_CLK_FSYS_MMC_CARD1, 0, 10), +}; + +static const struct samsung_cmu_info cmu_fsys_info __initconst =3D { + .pll_clks =3D cmu_fsys_pll_clks, + .nr_pll_clks =3D ARRAY_SIZE(cmu_fsys_pll_clks), + .mux_clks =3D cmu_fsys_mux_clks, + .nr_mux_clks =3D ARRAY_SIZE(cmu_fsys_mux_clks), + .div_clks =3D cmu_fsys_div_clks, + .nr_div_clks =3D ARRAY_SIZE(cmu_fsys_div_clks), + .nr_clk_ids =3D CMU_FSYS_NR_CLK, + .clk_regs =3D cmu_fsys_clk_regs, + .nr_clk_regs =3D ARRAY_SIZE(cmu_fsys_clk_regs), +}; + +static void __init artpec8_clk_cmu_fsys_init(struct device_node *np) +{ + samsung_cmu_register_one(np, &cmu_fsys_info); +} + +CLK_OF_DECLARE(artpec8_clk_cmu_fsys, "axis,artpec8-cmu-fsys", + artpec8_clk_cmu_fsys_init); + /* Register Offset definitions for CMU_IMEM (0x10010000) */ #define PLL_CON0_MUX_CLK_IMEM_ACLK_USER 0x0100 #define PLL_CON0_MUX_CLK_IMEM_JPEG_USER 0x0120 --=20 2.34.1 From nobody Tue Dec 23 12:18:25 2025 Received: from spam.coasia.com (mail2.coasia.com [112.168.119.159]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 91029EAF6 for ; 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(ksk4725@coasia.com@115.23.218.194) by 192.168.10.159 with ESMTP; 10 Jul 2025 09:21:00 +0900 X-Original-SENDERIP: 115.23.218.194 X-Original-SENDERCOUNTRY: KR, South Korea X-Original-MAILFROM: ksk4725@coasia.com X-Original-RCPTTO: jesper.nilsson@axis.com, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, krzk@kernel.org, s.nawrocki@samsung.com, cw00.choi@samsung.com, alim.akhtar@samsung.com, linus.walleij@linaro.org, tomasz.figa@gmail.com, catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de, ravi.patel@samsung.com, ksk4725@coasia.com, smn1196@coasia.com, kenkim@coasia.com, pjsin865@coasia.com, gwk1013@coasia.com, hgkim05@coasia.com, mingyoungbo@coasia.com, pankaj.dubey@samsung.com, shradha.t@samsung.com, inbaraj.e@samsung.com, swathi.ks@samsung.com, hrishikesh.d@samsung.com, dj76.yang@samsung.com, hypmean.kim@samsung.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@axis.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, soc@lists.linux.dev, v.pavani@samsung.com From: ksk4725@coasia.com To: Jesper Nilsson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krzysztof Kozlowski , Sylwester Nawrocki , Chanwoo Choi , Alim Akhtar , Linus Walleij , Tomasz Figa , Catalin Marinas , Will Deacon , Arnd Bergmann , Ravi Patel , SeonGu Kang , SungMin Park Cc: kenkim , Jongshin Park , GunWoo Kim , HaGyeong Kim , GyoungBo Min , Pankaj Dubey , Shradha Todi , Inbaraj E , Swathi K S , Hrishikesh , Dongjin Yang , Sang Min Kim , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@axis.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, soc@lists.linux.dev, Varada Pavani Subject: [PATCH 10/16] clk: samsung: artpec-8: Add clock support for CMU_PERI block Date: Thu, 10 Jul 2025 09:20:40 +0900 Message-Id: <20250710002047.1573841-11-ksk4725@coasia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250710002047.1573841-1-ksk4725@coasia.com> References: <20250710002047.1573841-1-ksk4725@coasia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Hakyeong Kim Add clock support for below CMU block in ARTPEC-8 SoC. - CMU_PERI Signed-off-by: Varada Pavani Signed-off-by: Hakyeong Kim --- drivers/clk/samsung/clk-artpec8.c | 90 +++++++++++++++++++++++++++++++ 1 file changed, 90 insertions(+) diff --git a/drivers/clk/samsung/clk-artpec8.c b/drivers/clk/samsung/clk-ar= tpec8.c index 7ccec4ff8f70..f45bc9c113f0 100644 --- a/drivers/clk/samsung/clk-artpec8.c +++ b/drivers/clk/samsung/clk-artpec8.c @@ -20,6 +20,7 @@ #define CMU_CPUCL_NR_CLK (DOUT_CLK_CPUCL_PCLKDBG + 1) #define CMU_FSYS_NR_CLK (DOUT_SCAN_CLK_FSYS_MMC + 1) #define CMU_IMEM_NR_CLK (MOUT_IMEM_JPEG_USER + 1) +#define CMU_PERI_NR_CLK (DOUT_PERI_DSIM + 1) =20 /* register offset definitions for cmu_cmu (0x12400000) */ #define PLL_LOCKTIME_PLL_AUDIO 0x0000 @@ -798,3 +799,92 @@ static void __init artpec8_clk_cmu_imem_init(struct de= vice_node *np) =20 CLK_OF_DECLARE(artpec8_clk_cmu_imem, "axis,artpec8-cmu-imem", artpec8_clk_cmu_imem_init); + +/* Register Offset definitions for CMU_PERI (0x16410000) */ +#define PLL_CON0_MUX_CLK_PERI_AUDIO_USER 0x0100 +#define PLL_CON0_MUX_CLK_PERI_DISP_USER 0x0120 +#define PLL_CON0_MUX_CLK_PERI_IP_USER 0x0140 +#define MUX_CLK_PERI_I2S0 0x1000 +#define MUX_CLK_PERI_I2S1 0x1004 +#define DIV_CLK_PERI_DSIM 0x1800 +#define DIV_CLK_PERI_I2S0 0x1804 +#define DIV_CLK_PERI_I2S1 0x1808 +#define DIV_CLK_PERI_PCLK 0x180c +#define DIV_CLK_PERI_SPI 0x1810 +#define DIV_CLK_PERI_UART1 0x1814 +#define DIV_CLK_PERI_UART2 0x1818 + +static const unsigned long cmu_peri_clk_regs[] __initconst =3D { + PLL_CON0_MUX_CLK_PERI_AUDIO_USER, + PLL_CON0_MUX_CLK_PERI_DISP_USER, + PLL_CON0_MUX_CLK_PERI_IP_USER, + MUX_CLK_PERI_I2S0, + MUX_CLK_PERI_I2S1, + DIV_CLK_PERI_DSIM, + DIV_CLK_PERI_I2S0, + DIV_CLK_PERI_I2S1, + DIV_CLK_PERI_PCLK, + DIV_CLK_PERI_SPI, + DIV_CLK_PERI_UART1, + DIV_CLK_PERI_UART2, +}; + +static const struct samsung_fixed_rate_clock peri_fixed_clks[] __initconst= =3D { + FRATE(0, "clk_peri_audio", NULL, 0, 100000000), +}; + +PNAME(mout_peri_ip_user_p) =3D { "fin_pll", "dout_clkcmu_peri_ip" }; +PNAME(mout_peri_audio_user_p) =3D { "fin_pll", "dout_clkcmu_peri_audio" }; +PNAME(mout_peri_disp_user_p) =3D { "fin_pll", "dout_clkcmu_peri_disp" }; +PNAME(mout_peri_i2s0_p) =3D { "dout_peri_i2s0", "clk_peri_audio" }; +PNAME(mout_peri_i2s1_p) =3D { "dout_peri_i2s1", "clk_peri_audio" }; + +static const struct samsung_mux_clock cmu_peri_mux_clks[] __initconst =3D { + MUX(MOUT_PERI_IP_USER, "mout_peri_ip_user", mout_peri_ip_user_p, + PLL_CON0_MUX_CLK_PERI_IP_USER, 4, 1), + MUX(MOUT_PERI_AUDIO_USER, "mout_peri_audio_user", + mout_peri_audio_user_p, PLL_CON0_MUX_CLK_PERI_AUDIO_USER, 4, 1), + MUX(MOUT_PERI_DISP_USER, "mout_peri_disp_user", mout_peri_disp_user_p, + PLL_CON0_MUX_CLK_PERI_DISP_USER, 4, 1), + MUX(MOUT_PERI_I2S0, "mout_peri_i2s0", mout_peri_i2s0_p, + MUX_CLK_PERI_I2S0, 0, 1), + MUX(MOUT_PERI_I2S1, "mout_peri_i2s1", mout_peri_i2s1_p, + MUX_CLK_PERI_I2S1, 0, 1), +}; + +static const struct samsung_div_clock cmu_peri_div_clks[] __initconst =3D { + DIV(DOUT_PERI_SPI, "dout_peri_spi", "mout_peri_ip_user", + DIV_CLK_PERI_SPI, 0, 10), + DIV(DOUT_PERI_UART1, "dout_peri_uart1", "mout_peri_ip_user", + DIV_CLK_PERI_UART1, 0, 10), + DIV(DOUT_PERI_UART2, "dout_peri_uart2", "mout_peri_ip_user", + DIV_CLK_PERI_UART2, 0, 10), + DIV(DOUT_PERI_PCLK, "dout_peri_pclk", "mout_peri_ip_user", + DIV_CLK_PERI_PCLK, 0, 4), + DIV(DOUT_PERI_I2S0, "dout_peri_i2s0", "mout_peri_audio_user", + DIV_CLK_PERI_I2S0, 0, 4), + DIV(DOUT_PERI_I2S1, "dout_peri_i2s1", "mout_peri_audio_user", + DIV_CLK_PERI_I2S1, 0, 4), + DIV(DOUT_PERI_DSIM, "dout_peri_dsim", "mout_peri_disp_user", + DIV_CLK_PERI_DSIM, 0, 4), +}; + +static const struct samsung_cmu_info cmu_peri_info __initconst =3D { + .mux_clks =3D cmu_peri_mux_clks, + .nr_mux_clks =3D ARRAY_SIZE(cmu_peri_mux_clks), + .div_clks =3D cmu_peri_div_clks, + .nr_div_clks =3D ARRAY_SIZE(cmu_peri_div_clks), + .fixed_clks =3D peri_fixed_clks, + .nr_fixed_clks =3D ARRAY_SIZE(peri_fixed_clks), + .nr_clk_ids =3D CMU_PERI_NR_CLK, + .clk_regs =3D cmu_peri_clk_regs, + .nr_clk_regs =3D ARRAY_SIZE(cmu_peri_clk_regs), +}; + +static void __init artpec8_clk_cmu_peri_init(struct device_node *np) +{ + samsung_cmu_register_one(np, &cmu_peri_info); +} + +CLK_OF_DECLARE(artpec8_clk_cmu_peri, "axis,artpec8-cmu-peri", + artpec8_clk_cmu_peri_init); --=20 2.34.1 From nobody Tue Dec 23 12:18:25 2025 Received: from spam.coasia.com (mail2.coasia.com [112.168.119.159]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D0508DF49 for ; Thu, 10 Jul 2025 00:21:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=112.168.119.159 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752106867; cv=none; b=GNNoL5eU2uNySY2xZInlnmNLsq+nC86QPqy4l+rcZ7vwNH7G1F3WD2XZ469GmXpx1YJa2Xh8yI310A98rMNiyHkAon8n9pVexwrc2B3oW4FqkV1Di/L8T5uJSoB+5h/OFsZuuCIVPY+cwRmKmhpF0U0/E5nGfgXDHSxzSJj5+p8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752106867; c=relaxed/simple; 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(ksk4725@coasia.com@115.23.218.194) by 192.168.10.159 with ESMTP; 10 Jul 2025 09:21:01 +0900 X-Original-SENDERIP: 115.23.218.194 X-Original-SENDERCOUNTRY: KR, South Korea X-Original-MAILFROM: ksk4725@coasia.com X-Original-RCPTTO: jesper.nilsson@axis.com, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, krzk@kernel.org, s.nawrocki@samsung.com, cw00.choi@samsung.com, alim.akhtar@samsung.com, linus.walleij@linaro.org, tomasz.figa@gmail.com, catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de, kenkim@coasia.com, pjsin865@coasia.com, gwk1013@coasia.com, ksk4725@coasia.com, hgkim05@coasia.com, mingyoungbo@coasia.com, smn1196@coasia.com, pankaj.dubey@samsung.com, shradha.t@samsung.com, ravi.patel@samsung.com, inbaraj.e@samsung.com, swathi.ks@samsung.com, hrishikesh.d@samsung.com, dj76.yang@samsung.com, hypmean.kim@samsung.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@axis.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, soc@lists.linux.dev From: ksk4725@coasia.com To: Jesper Nilsson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krzysztof Kozlowski , Sylwester Nawrocki , Chanwoo Choi , Alim Akhtar , Linus Walleij , Tomasz Figa , Catalin Marinas , Will Deacon , Arnd Bergmann Cc: kenkim , Jongshin Park , GunWoo Kim , SeonGu Kang , HaGyeong Kim , GyoungBo Min , SungMin Park , Pankaj Dubey , Shradha Todi , Ravi Patel , Inbaraj E , Swathi K S , Hrishikesh , Dongjin Yang , Sang Min Kim , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@axis.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, soc@lists.linux.dev Subject: [PATCH 11/16] dt-bindings: pinctrl: samsung: Add compatible for ARTPEC-8 SoC Date: Thu, 10 Jul 2025 09:20:41 +0900 Message-Id: <20250710002047.1573841-12-ksk4725@coasia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250710002047.1573841-1-ksk4725@coasia.com> References: <20250710002047.1573841-1-ksk4725@coasia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: SeonGu Kang Document the compatible string for ARTPEC-8 SoC pinctrl block, which is similar to other Samsung SoC pinctrl blocks. Signed-off-by: SeonGu Kang --- Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml= b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml index de8460856141..9386dcd418c2 100644 --- a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml @@ -35,6 +35,7 @@ properties: =20 compatible: enum: + - axis,artpec8-pinctrl - google,gs101-pinctrl - samsung,s3c2412-pinctrl - samsung,s3c2416-pinctrl --=20 2.34.1 From nobody Tue Dec 23 12:18:25 2025 Received: from spam.coasia.com (mail2.coasia.com [112.168.119.159]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E657A13B293 for ; Thu, 10 Jul 2025 00:21:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=112.168.119.159 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752106868; cv=none; b=h/m19Shlr2vNuysRWfged6YUF8ICVKOckW8F26V0PfZyggAUYvkgpU2zz400gIh7sEH/YnIEUlOqwkPpFzIUozh6B2yNZWHK7jSq6Dm/FFls+mhSphuLErcdJr2iV1AZ1xfyA+DQP6xwfYS88gRaaFIt3KMauxYuSG6R9rm1m7w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752106868; c=relaxed/simple; bh=+XyIYQMf2ncS8t1GTxr8ifxgcrmBt2eK7n4z1pjGkos=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=DhaErYWzVtASlYW0b7H4M8PXT8nvt4er0WIKrU7LW/otgTwFThitMa97ikfS71gwaqDLCTK0XMSOewAwigyLncJ+LMrITFASVCARKTKXwyGQY76g3Hc17NV1JfPIwnRlFbdG4fymNvWDHAYmgbr2ClgEVxPhdn4Z0wqqZJ7/Acg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=coasia.com; spf=pass smtp.mailfrom=coasia.com; dkim=pass (1024-bit key) header.d=coasia.com header.i=@coasia.com header.b=CLBeIJS3; arc=none smtp.client-ip=112.168.119.159 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=coasia.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=coasia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=coasia.com header.i=@coasia.com header.b="CLBeIJS3" DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=coasia.com; s=coasia; t=1752106862; bh=+XyIYQMf2ncS8t1GTxr8ifxgcrmBt2eK7n4z1pjGkos=; l=5043; h=From:To:Subject:Date:Message-Id:MIME-Version; b=CLBeIJS3n60wpYNDups7Nio9xhosNVGFpQAF3qL7/2yUt4YEWblol0a3YJ4SmFmIK wymByngctjyAPt7mrMJ42KGtKne/t0sAcWg/krccR5qApOg4woyWO6cFu6bcQWlu+/ e9aCN3JZA8gWNllwv7NxTN6Pr8F1e+dLEHfnMoAo= Received: from unknown (HELO kangseongu..) (ksk4725@coasia.com@115.23.218.194) by 192.168.10.159 with ESMTP; 10 Jul 2025 09:21:02 +0900 X-Original-SENDERIP: 115.23.218.194 X-Original-SENDERCOUNTRY: KR, South Korea X-Original-MAILFROM: ksk4725@coasia.com X-Original-RCPTTO: jesper.nilsson@axis.com, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, krzk@kernel.org, s.nawrocki@samsung.com, cw00.choi@samsung.com, alim.akhtar@samsung.com, linus.walleij@linaro.org, tomasz.figa@gmail.com, catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de, kenkim@coasia.com, pjsin865@coasia.com, gwk1013@coasia.com, ksk4725@coasia.com, hgkim05@coasia.com, mingyoungbo@coasia.com, smn1196@coasia.com, pankaj.dubey@samsung.com, shradha.t@samsung.com, ravi.patel@samsung.com, inbaraj.e@samsung.com, swathi.ks@samsung.com, hrishikesh.d@samsung.com, dj76.yang@samsung.com, hypmean.kim@samsung.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@axis.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, soc@lists.linux.dev, priya.ganesh@samsung.com From: ksk4725@coasia.com To: Jesper Nilsson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krzysztof Kozlowski , Sylwester Nawrocki , Chanwoo Choi , Alim Akhtar , Linus Walleij , Tomasz Figa , Catalin Marinas , Will Deacon , Arnd Bergmann Cc: kenkim , Jongshin Park , GunWoo Kim , SeonGu Kang , HaGyeong Kim , GyoungBo Min , SungMin Park , Pankaj Dubey , Shradha Todi , Ravi Patel , Inbaraj E , Swathi K S , Hrishikesh , Dongjin Yang , Sang Min Kim , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@axis.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, soc@lists.linux.dev, Priyadarsini G Subject: [PATCH 12/16] pinctrl: samsung: Add ARTPEC-8 SoC specific configuration Date: Thu, 10 Jul 2025 09:20:42 +0900 Message-Id: <20250710002047.1573841-13-ksk4725@coasia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250710002047.1573841-1-ksk4725@coasia.com> References: <20250710002047.1573841-1-ksk4725@coasia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: SeonGu Kang Add Axis ARTPEC-8 SoC specific configuration data to enable pinctrl. It is similar to other Samsung SoC pinctrl blocks. Signed-off-by: Priyadarsini G Signed-off-by: SeonGu Kang --- .../pinctrl/samsung/pinctrl-exynos-arm64.c | 50 +++++++++++++++++++ drivers/pinctrl/samsung/pinctrl-exynos.h | 10 ++++ drivers/pinctrl/samsung/pinctrl-samsung.c | 2 + drivers/pinctrl/samsung/pinctrl-samsung.h | 1 + 4 files changed, 63 insertions(+) diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinct= rl/samsung/pinctrl-exynos-arm64.c index dd07720e32cc..ee3b488b00ff 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c @@ -76,6 +76,15 @@ static const struct samsung_pin_bank_type exynos8895_ban= k_type_off =3D { .reg_offset =3D { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, }, }; =20 +/* + * Bank type for non-alive type. Bit fields: + * CON: 4, DAT: 1, PUD: 4, DRV: 4 + */ +static const struct samsung_pin_bank_type artpec_bank_type_off =3D { + .fld_width =3D { 4, 1, 4, 4, }, + .reg_offset =3D { 0x00, 0x04, 0x08, 0x0c, }, +}; + /* Pad retention control code for accessing PMU regmap */ static atomic_t exynos_shared_retention_refcnt; =20 @@ -1814,3 +1823,44 @@ const struct samsung_pinctrl_of_match_data gs101_of_= data __initconst =3D { .ctrl =3D gs101_pin_ctrl, .num_ctrl =3D ARRAY_SIZE(gs101_pin_ctrl), }; + +/* pin banks of artpec8 pin-controller (FSYS0) */ +static const struct samsung_pin_bank_data artpec8_pin_banks0[] __initconst= =3D { + ARTPEC_PIN_BANK_EINTG(5, 0x000, "gpf0", 0x00), + ARTPEC_PIN_BANK_EINTG(4, 0x020, "gpf1", 0x04), + ARTPEC_PIN_BANK_EINTG(8, 0x040, "gpf2", 0x08), + ARTPEC_PIN_BANK_EINTG(4, 0x060, "gpf3", 0x0c), + ARTPEC_PIN_BANK_EINTG(7, 0x080, "gpf4", 0x10), + ARTPEC_PIN_BANK_EINTG(8, 0x0a0, "gpe0", 0x14), + ARTPEC_PIN_BANK_EINTG(8, 0x0c0, "gpe1", 0x18), + ARTPEC_PIN_BANK_EINTG(6, 0x0e0, "gpe2", 0x1c), + ARTPEC_PIN_BANK_EINTG(8, 0x100, "gps0", 0x20), + ARTPEC_PIN_BANK_EINTG(8, 0x120, "gps1", 0x24), +}; + +/* pin banks of artpec8 pin-controller (PERIC) */ +static const struct samsung_pin_bank_data artpec8_pin_banks1[] __initconst= =3D { + ARTPEC_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), + ARTPEC_PIN_BANK_EINTG(8, 0x020, "gpa1", 0x04), + ARTPEC_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08), + ARTPEC_PIN_BANK_EINTG(2, 0x060, "gpk0", 0x0c), +}; + +static const struct samsung_pin_ctrl artpec8_pin_ctrl[] __initconst =3D { + { + /* pin-controller instance 0 FSYS data */ + .pin_banks =3D artpec8_pin_banks0, + .nr_banks =3D ARRAY_SIZE(artpec8_pin_banks0), + .eint_gpio_init =3D exynos_eint_gpio_init, + }, { + /* pin-controller instance 1 PERIC data */ + .pin_banks =3D artpec8_pin_banks1, + .nr_banks =3D ARRAY_SIZE(artpec8_pin_banks1), + .eint_gpio_init =3D exynos_eint_gpio_init, + }, +}; + +const struct samsung_pinctrl_of_match_data artpec8_of_data __initconst =3D= { + .ctrl =3D artpec8_pin_ctrl, + .num_ctrl =3D ARRAY_SIZE(artpec8_pin_ctrl), +}; diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.h b/drivers/pinctrl/sam= sung/pinctrl-exynos.h index b483270ddc53..6bc04cb5ac9f 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos.h +++ b/drivers/pinctrl/samsung/pinctrl-exynos.h @@ -216,6 +216,16 @@ .name =3D id \ } =20 +#define ARTPEC_PIN_BANK_EINTG(pins, reg, id, offs) \ + { \ + .type =3D &artpec_bank_type_off, \ + .pctl_offset =3D reg, \ + .nr_pins =3D pins, \ + .eint_type =3D EINT_TYPE_GPIO, \ + .eint_offset =3D offs, \ + .name =3D id \ + } + /** * struct exynos_weint_data: irq specific data for all the wakeup interrup= ts * generated by the external wakeup interrupt controller. diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/sa= msung/pinctrl-samsung.c index 2896eb2de2c0..993efba5a9ad 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.c +++ b/drivers/pinctrl/samsung/pinctrl-samsung.c @@ -1468,6 +1468,8 @@ static const struct of_device_id samsung_pinctrl_dt_m= atch[] =3D { .data =3D &s5pv210_of_data }, #endif #ifdef CONFIG_PINCTRL_EXYNOS_ARM64 + { .compatible =3D "axis,artpec8-pinctrl", + .data =3D &artpec8_of_data }, { .compatible =3D "google,gs101-pinctrl", .data =3D &gs101_of_data }, { .compatible =3D "samsung,exynos2200-pinctrl", diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/sa= msung/pinctrl-samsung.h index 3cf758df7d69..bfd88ad2f3ff 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.h +++ b/drivers/pinctrl/samsung/pinctrl-samsung.h @@ -377,6 +377,7 @@ struct samsung_pmx_func { }; =20 /* list of all exported SoC specific data */ +extern const struct samsung_pinctrl_of_match_data artpec8_of_data; extern const struct samsung_pinctrl_of_match_data exynos2200_of_data; extern const struct samsung_pinctrl_of_match_data exynos3250_of_data; extern const struct samsung_pinctrl_of_match_data exynos4210_of_data; --=20 2.34.1 From nobody Tue Dec 23 12:18:25 2025 Received: from spam.coasia.com (mail2.coasia.com [112.168.119.159]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5C5CA29D0D for ; Thu, 10 Jul 2025 00:21:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=112.168.119.159 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752106868; cv=none; b=HLSpK33Ufytxfs/jAqiytOAMFNzv2MF3x0Cr/IVXHkWOZLcKrvmTeUrWVWW19P77DrT6Pq+bd4PyeHlG8SrQXj9hthup2mxYcAqGFvJMAafRp0UDBzrhB6dey+dkzzQSW2h6qXHJXvqrUwDWanEDlv898rKTJWnF6WI+MESnE/o= ARC-Message-Signature: i=1; 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(ksk4725@coasia.com@115.23.218.194) by 192.168.10.159 with ESMTP; 10 Jul 2025 09:21:03 +0900 X-Original-SENDERIP: 115.23.218.194 X-Original-SENDERCOUNTRY: KR, South Korea X-Original-MAILFROM: ksk4725@coasia.com X-Original-RCPTTO: jesper.nilsson@axis.com, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, krzk@kernel.org, s.nawrocki@samsung.com, cw00.choi@samsung.com, alim.akhtar@samsung.com, linus.walleij@linaro.org, tomasz.figa@gmail.com, catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de, ksk4725@coasia.com, smn1196@coasia.com, ravi.patel@samsung.com, linux-arm-kernel@axis.com, kenkim@coasia.com, pjsin865@coasia.com, gwk1013@coasia.com, hgkim05@coasia.com, mingyoungbo@coasia.com, pankaj.dubey@samsung.com, shradha.t@samsung.com, inbaraj.e@samsung.com, swathi.ks@samsung.com, hrishikesh.d@samsung.com, dj76.yang@samsung.com, hypmean.kim@samsung.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, soc@lists.linux.dev From: ksk4725@coasia.com To: Jesper Nilsson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krzysztof Kozlowski , Sylwester Nawrocki , Chanwoo Choi , Alim Akhtar , Linus Walleij , Tomasz Figa , Catalin Marinas , Will Deacon , Arnd Bergmann , SeonGu Kang , SungMin Park , Ravi Patel , linux-arm-kernel@axis.com Cc: kenkim , Jongshin Park , GunWoo Kim , HaGyeong Kim , GyoungBo Min , Pankaj Dubey , Shradha Todi , Inbaraj E , Swathi K S , Hrishikesh , Dongjin Yang , Sang Min Kim , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, soc@lists.linux.dev Subject: [PATCH 13/16] dt-bindings: arm: Add Axis ARTPEC SoC platform Date: Thu, 10 Jul 2025 09:20:43 +0900 Message-Id: <20250710002047.1573841-14-ksk4725@coasia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250710002047.1573841-1-ksk4725@coasia.com> References: <20250710002047.1573841-1-ksk4725@coasia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Ravi Patel Add device tree bindings for the Axis ARTPEC-8 SoC platform and ARTPEC-8 Grizzly board. Also move the existing ARTPEC-6 related bindings from .txt to yaml format. Signed-off-by: sungminpark Signed-off-by: Ravi Patel --- .../devicetree/bindings/arm/axis.txt | 13 ------- .../devicetree/bindings/arm/axis.yaml | 35 +++++++++++++++++++ 2 files changed, 35 insertions(+), 13 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/axis.txt create mode 100644 Documentation/devicetree/bindings/arm/axis.yaml diff --git a/Documentation/devicetree/bindings/arm/axis.txt b/Documentation= /devicetree/bindings/arm/axis.txt deleted file mode 100644 index ebd33a88776f..000000000000 --- a/Documentation/devicetree/bindings/arm/axis.txt +++ /dev/null @@ -1,13 +0,0 @@ -Axis Communications AB -ARTPEC series SoC Device Tree Bindings - -ARTPEC-6 ARM SoC -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D - -Required root node properties: -- compatible =3D "axis,artpec6"; - -ARTPEC-6 Development board: ---------------------------- -Required root node properties: -- compatible =3D "axis,artpec6-dev-board", "axis,artpec6"; diff --git a/Documentation/devicetree/bindings/arm/axis.yaml b/Documentatio= n/devicetree/bindings/arm/axis.yaml new file mode 100644 index 000000000000..70fb3caa70df --- /dev/null +++ b/Documentation/devicetree/bindings/arm/axis.yaml @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/axis.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Axis ARTPEC platforms + +maintainers: + - Jesper Nilsson + - SeonGu Kang + - SungMin Park + - Ravi Patel + - linux-arm-kernel@axis.com + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: Axis ARTPEC-6 Development board + items: + - enum: + - axis,artpec6-dev-board + - const: axis,artpec6 + + - description: Axis ARTPEC-8 Grizzly board + items: + - enum: + - axis,artpec8-grizzly + - const: axis,artpec8 + +additionalProperties: true + +... --=20 2.34.1 From nobody Tue Dec 23 12:18:25 2025 Received: from spam.coasia.com (mail2.coasia.com [112.168.119.159]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E627472602 for ; Thu, 10 Jul 2025 00:21:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=112.168.119.159 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752106871; cv=none; b=NBCVAN7AtE2FoUk5N6NJ7ZtRFJp3a3ax16RIcVWlcXK48HEnVH/uzX6Y1UCLKp3b7E0pktrCy62UHbsinoIx1vLXVkizIvgnznvM8WKMg7jfi2LIaMrGfWnxG2nd2FoKczB+cKbR7cBxnS0TW8nv1jkjmXgpir3jZN16If8Xj+o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752106871; c=relaxed/simple; bh=5GPEh4zg18KRWwJgxxkzuyxM5vmaI0kXf99LFNAueyQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=MkdkMG8NP72bM7HLePidPd/qWPiULRM+FSjRQqiNtEMENmez+Rsf0PzwaDynY4Lmq4NbV67FxLjjNW2SXGzRSfKIDduGrYI09sT0zQ4CdITzFUwA0qFw4RZInCSexBzeE3ja6sb9pQlskYK4IB9WupVfhPCUBcMru2K/EbCzCUY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=coasia.com; spf=pass smtp.mailfrom=coasia.com; dkim=pass (1024-bit key) header.d=coasia.com header.i=@coasia.com header.b=aAPEVMLH; arc=none smtp.client-ip=112.168.119.159 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=coasia.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=coasia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=coasia.com header.i=@coasia.com header.b="aAPEVMLH" DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=coasia.com; s=coasia; t=1752106865; bh=5GPEh4zg18KRWwJgxxkzuyxM5vmaI0kXf99LFNAueyQ=; l=11826; h=From:To:Subject:Date:Message-Id:MIME-Version; b=aAPEVMLHb6ZHij/W89LXF/yT61IvwjOeMGhq+c+TnFCgAwIr4fkQ9BPTRrauxE93C E9FXnvgtP2QuKlsfSDEYeCpnpzGfMx3FRIzstdHFrHMSlvDUz5+gtwkqD/ud3Kdi94 9WN9oQsD+fcPKOwr2DsWkRBdDN0Cv9Omdir6q9NI= Received: from unknown (HELO kangseongu..) (ksk4725@coasia.com@115.23.218.194) by 192.168.10.159 with ESMTP; 10 Jul 2025 09:21:05 +0900 X-Original-SENDERIP: 115.23.218.194 X-Original-SENDERCOUNTRY: KR, South Korea X-Original-MAILFROM: ksk4725@coasia.com X-Original-RCPTTO: jesper.nilsson@axis.com, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, krzk@kernel.org, s.nawrocki@samsung.com, cw00.choi@samsung.com, alim.akhtar@samsung.com, linus.walleij@linaro.org, tomasz.figa@gmail.com, catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de, ravi.patel@samsung.com, ksk4725@coasia.com, smn1196@coasia.com, kenkim@coasia.com, pjsin865@coasia.com, gwk1013@coasia.com, hgkim05@coasia.com, mingyoungbo@coasia.com, pankaj.dubey@samsung.com, shradha.t@samsung.com, inbaraj.e@samsung.com, swathi.ks@samsung.com, hrishikesh.d@samsung.com, dj76.yang@samsung.com, hypmean.kim@samsung.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@axis.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, soc@lists.linux.dev From: ksk4725@coasia.com To: Jesper Nilsson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krzysztof Kozlowski , Sylwester Nawrocki , Chanwoo Choi , Alim Akhtar , Linus Walleij , Tomasz Figa , Catalin Marinas , Will Deacon , Arnd Bergmann , Ravi Patel , SeonGu Kang , SungMin Park Cc: kenkim , Jongshin Park , GunWoo Kim , HaGyeong Kim , GyoungBo Min , Pankaj Dubey , Shradha Todi , Inbaraj E , Swathi K S , Hrishikesh , Dongjin Yang , Sang Min Kim , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@axis.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, soc@lists.linux.dev Subject: [PATCH 14/16] arm64: dts: axis: Add initial device tree support Date: Thu, 10 Jul 2025 09:20:44 +0900 Message-Id: <20250710002047.1573841-15-ksk4725@coasia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250710002047.1573841-1-ksk4725@coasia.com> References: <20250710002047.1573841-1-ksk4725@coasia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: sungminpark Add initial device tree support for Axis ARTPEC-8 SoC and Grizzly board. This SoC contains four cores of cortex-a53 CPUs and other various peripheral IPs. Signed-off-by: Ravi Patel Signed-off-by: sungminpark --- MAINTAINERS | 14 ++ arch/arm64/Kconfig.platforms | 13 + arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/axis/Makefile | 4 + arch/arm64/boot/dts/axis/artpec8-grizzly.dts | 67 +++++ arch/arm64/boot/dts/axis/artpec8.dtsi | 252 +++++++++++++++++++ 6 files changed, 351 insertions(+) create mode 100644 arch/arm64/boot/dts/axis/Makefile create mode 100644 arch/arm64/boot/dts/axis/artpec8-grizzly.dts create mode 100644 arch/arm64/boot/dts/axis/artpec8.dtsi diff --git a/MAINTAINERS b/MAINTAINERS index fa1e04e87d1d..371005f3f41a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2320,6 +2320,20 @@ F: drivers/crypto/axis F: drivers/mmc/host/usdhi6rol0.c F: drivers/pinctrl/pinctrl-artpec* =20 +ARM/ARTPEC ARM64 MACHINE SUPPORT +M: Jesper Nilsson +M: Ravi Patel +M: SeonGu Kang +M: SungMin Park +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) +L: linux-samsung-soc@vger.kernel.org +L: linux-arm-kernel@axis.com +S: Maintained +F: Documentation/devicetree/bindings/clock/axis,artpec*-clock.yaml +F: arch/arm64/boot/dts/axis/ +F: drivers/clk/samsung/clk-artpec*.c +F: include/dt-bindings/clock/axis,artpec*-clk.h + ARM/ASPEED I2C DRIVER M: Ryan Chen R: Benjamin Herrenschmidt diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 8b76821f190f..418ee47227c1 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -40,6 +40,19 @@ config ARCH_APPLE This enables support for Apple's in-house ARM SoC family, such as the Apple M1. =20 +config ARCH_ARTPEC + bool "Axis Communications ARTPEC SoC Family" + help + This enables support for the ARMv8 based ARTPEC SoC Family. + +config ARCH_ARTPEC8 + bool "Axis ARTPEC-8 SoC Platform" + depends on ARCH_ARTPEC + depends on ARCH_EXYNOS + select ARM_GIC + help + This enables support for the Axis ARTPEC-8 SoC. + menuconfig ARCH_BCM bool "Broadcom SoC Support" =20 diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile index 79b73a21ddc2..6b6a3aedc2ed 100644 --- a/arch/arm64/boot/dts/Makefile +++ b/arch/arm64/boot/dts/Makefile @@ -9,6 +9,7 @@ subdir-y +=3D amlogic subdir-y +=3D apm subdir-y +=3D apple subdir-y +=3D arm +subdir-y +=3D axis subdir-y +=3D bitmain subdir-y +=3D blaize subdir-y +=3D broadcom diff --git a/arch/arm64/boot/dts/axis/Makefile b/arch/arm64/boot/dts/axis/M= akefile new file mode 100644 index 000000000000..ccf00de64016 --- /dev/null +++ b/arch/arm64/boot/dts/axis/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 + +dtb-$(CONFIG_ARCH_ARTPEC) +=3D \ + artpec8-grizzly.dtb diff --git a/arch/arm64/boot/dts/axis/artpec8-grizzly.dts b/arch/arm64/boot= /dts/axis/artpec8-grizzly.dts new file mode 100644 index 000000000000..7671130a0333 --- /dev/null +++ b/arch/arm64/boot/dts/axis/artpec8-grizzly.dts @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Axis ARTPEC-8 Grizzly board device tree source + * + * Copyright (c) 2022-2025 Samsung Electronics Co., Ltd. + * https://www.samsung.com + * Copyright (c) 2022-2025 Axis Communications AB. + * https://www.axis.com + */ + +/dts-v1/; +#include "artpec8.dtsi" +#include +/ { + model =3D "ARTPEC-8 grizzly board"; + compatible =3D "axis,artpec8-grizzly", "axis,artpec8"; + + aliases { + serial0 =3D &serial_0; + }; + + chosen { + stdout-path =3D &serial_0; + }; + + memory@80000000 { + device_type =3D "memory"; + reg =3D <0x0 0x80000000 0x0 0x80000000>; + }; +}; + +&osc_clk { + clock-frequency =3D <50000000>; + status =3D "okay"; +}; + +&serial_0 { + status =3D "okay"; +}; + +&cmu_cmu { + status =3D "okay"; +}; + +&cmu_bus { + status =3D "okay"; +}; + +&cmu_core { + status =3D "okay"; +}; + +&cmu_cpucl { + status =3D "okay"; +}; + +&cmu_fsys { + status =3D "okay"; +}; + +&cmu_imem { + status =3D "okay"; +}; + +&cmu_peri { + status =3D "okay"; +}; diff --git a/arch/arm64/boot/dts/axis/artpec8.dtsi b/arch/arm64/boot/dts/ax= is/artpec8.dtsi new file mode 100644 index 000000000000..296192560adf --- /dev/null +++ b/arch/arm64/boot/dts/axis/artpec8.dtsi @@ -0,0 +1,252 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Axis ARTPEC-8 SoC device tree source + * + * Copyright (c) 2022-2025 Samsung Electronics Co., Ltd. + * https://www.samsung.com + * Copyright (c) 2022-2025 Axis Communications AB. + * https://www.axis.com + */ + +#include +#include + +/ { + compatible =3D "axis,artpec8"; + interrupt-parent =3D <&gic>; + #address-cells =3D <2>; + #size-cells =3D <2>; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu0: cpu@0 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x0>; + cpu-idle-states =3D <&cpu_sleep>; + enable-method =3D "psci"; + clocks =3D <&cmu_cpucl DOUT_CLK_CPUCL_CPU>; + clock-names =3D "dout_clk_cpucl_cpu"; + clock-frequency =3D <1200000000>; + }; + + cpu1: cpu@1 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x1>; + cpu-idle-states =3D <&cpu_sleep>; + enable-method =3D "psci"; + clock-frequency =3D <1200000000>; + }; + + cpu2: cpu@2 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x2>; + cpu-idle-states =3D <&cpu_sleep>; + enable-method =3D "psci"; + clock-frequency =3D <1200000000>; + }; + + cpu3: cpu@3 { + device_type =3D "cpu"; + compatible =3D "arm,cortex-a53"; + reg =3D <0x3>; + cpu-idle-states =3D <&cpu_sleep>; + enable-method =3D "psci"; + clock-frequency =3D <1200000000>; + }; + + idle-states { + entry-method =3D "psci"; + + cpu_sleep: cpu-sleep { + compatible =3D "arm,idle-state"; + arm,psci-suspend-param =3D <0x0010000>; + local-timer-stop; + entry-latency-us =3D <300>; + exit-latency-us =3D <1200>; + min-residency-us =3D <2000>; + }; + }; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupts =3D , + , + , + ; + }; + + pmu { + compatible =3D "arm,cortex-a53-pmu"; + interrupts =3D , + , + , + ; + interrupt-affinity =3D <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + + psci { + compatible =3D "arm,psci-0.2"; + method =3D "smc"; + }; + + osc_clk: xxti { + compatible =3D "fixed-clock"; + clock-output-names =3D "xxti"; + #clock-cells =3D <0>; + }; + + fin_pll: fin_pll { + compatible =3D "fixed-factor-clock"; + clocks =3D <&osc_clk>; + #clock-cells =3D <0>; + clock-div =3D <2>; + clock-mult =3D <1>; + clock-output-names =3D "fin_pll"; + }; + + soc: soc@0 { + compatible =3D "simple-bus"; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x0 0x0 0x0 0x17000000>; + + mct@10040000 { + compatible =3D "samsung,exynos4210-mct"; + reg =3D <0x10040000 0x1000>; + clocks =3D <&fin_pll>, <&cmu_imem MOUT_IMEM_ACLK_USER>; + clock-names =3D "fin_pll", "mct"; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + ; + }; + + gic: interrupt-controller@10201000 { + compatible =3D "arm,gic-400"; + #interrupt-cells =3D <3>; + #address-cells =3D <0>; + interrupt-controller; + reg =3D <0x10201000 0x00001000>, + <0x10202000 0x00002000>, + <0x10204000 0x00002000>, + <0x10206000 0x00002000>; + }; + + cmu_cmu: clock-controller@12400000 { + compatible =3D "axis,artpec8-cmu-cmu"; + reg =3D <0x12400000 0x4000>; + #clock-cells =3D <1>; + clocks =3D <&fin_pll>; + clock-names =3D "fin_pll"; + status =3D "disabled"; + }; + + cmu_bus: clock-controller@12c10000 { + compatible =3D "axis,artpec8-cmu-bus"; + reg =3D <0x12c10000 0x4000>; + #clock-cells =3D <1>; + clocks =3D <&fin_pll>, + <&cmu_cmu DOUT_CLKCMU_BUS_BUS>, + <&cmu_cmu DOUT_CLKCMU_BUS_DLP>; + clock-names =3D "fin_pll", + "dout_clkcmu_bus_bus", + "dout_clkcmu_bus_dlp"; + status =3D "disabled"; + }; + + cmu_core: clock-controller@12410000 { + compatible =3D "axis,artpec8-cmu-core"; + reg =3D <0x12410000 0x4000>; + #clock-cells =3D <1>; + clocks =3D <&fin_pll>, + <&cmu_cmu DOUT_CLKCMU_CORE_MAIN>, + <&cmu_cmu DOUT_CLKCMU_CORE_DLP>; + clock-names =3D "fin_pll", + "dout_clkcmu_core_main", + "dout_clkcmu_core_dlp"; + status =3D "disabled"; + }; + + cmu_cpucl: clock-controller@11410000 { + compatible =3D "axis,artpec8-cmu-cpucl"; + reg =3D <0x11410000 0x4000>; + #clock-cells =3D <1>; + clocks =3D <&fin_pll>, + <&cmu_cmu DOUT_CLKCMU_CPUCL_SWITCH>; + clock-names =3D "fin_pll", + "dout_clkcmu_cpucl_switch"; + status =3D "disabled"; + }; + + cmu_fsys: clock-controller@16c10000 { + compatible =3D "axis,artpec8-cmu-fsys"; + reg =3D <0x16c10000 0x4000>; + #clock-cells =3D <1>; + clocks =3D <&fin_pll>, + <&cmu_cmu DOUT_CLKCMU_FSYS_SCAN0>, + <&cmu_cmu DOUT_CLKCMU_FSYS_SCAN1>, + <&cmu_cmu DOUT_CLKCMU_FSYS_BUS>, + <&cmu_cmu DOUT_CLKCMU_FSYS_IP>; + clock-names =3D "fin_pll", + "dout_clkcmu_fsys_scan0", + "dout_clkcmu_fsys_scan1", + "dout_clkcmu_fsys_bus", + "dout_clkcmu_fsys_ip"; + status =3D "disabled"; + }; + + cmu_imem: clock-controller@10010000 { + compatible =3D "axis,artpec8-cmu-imem"; + reg =3D <0x10010000 0x4000>; + #clock-cells =3D <1>; + clocks =3D <&fin_pll>, + <&cmu_cmu DOUT_CLKCMU_IMEM_ACLK>, + <&cmu_cmu DOUT_CLKCMU_IMEM_JPEG>; + clock-names =3D "fin_pll", + "dout_clkcmu_imem_aclk", + "dout_clkcmu_imem_jpeg"; + status =3D "disabled"; + }; + + cmu_peri: clock-controller@16410000 { + compatible =3D "axis,artpec8-cmu-peri"; + reg =3D <0x16410000 0x4000>; + #clock-cells =3D <1>; + clocks =3D <&fin_pll>, + <&cmu_cmu DOUT_CLKCMU_PERI_IP>, + <&cmu_cmu DOUT_CLKCMU_PERI_AUDIO>, + <&cmu_cmu DOUT_CLKCMU_PERI_DISP>; + clock-names =3D "fin_pll", + "dout_clkcmu_peri_ip", + "dout_clkcmu_peri_audio", + "dout_clkcmu_peri_disp"; + status =3D "disabled"; + }; + + serial_0: serial@16cc0000 { + compatible =3D "axis,artpec8-uart"; + reg =3D <0x16cc0000 0x100>; + clocks =3D <&cmu_fsys DOUT_FSYS_BUS300>, + <&cmu_fsys DOUT_FSYS_SCLK_UART>; + clock-names =3D "uart", "clk_uart_baud0"; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&serial0_bus>; + status =3D "disabled"; + }; + }; +}; --=20 2.34.1 From nobody Tue Dec 23 12:18:25 2025 Received: from spam.coasia.com (mail2.coasia.com [112.168.119.159]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 66E19154BF5 for ; Thu, 10 Jul 2025 00:21:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=112.168.119.159 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752106874; cv=none; b=fUEKv+3Ec+0T0DrI/1Wsd7az1FWnnai/eIC5PiqhmonEmQLkeSWW6kH0NnOGB5Kp73IPdiBBeyP1Hfp/hqA/5YuZ/XRtl5E1hohJyJsPMaXGA0VQe7jTHjNNecxWqpVOCO+igvWnUjRpjSrs+FiIpAjTxcA9iCJDjF8GfVBnZ/E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752106874; c=relaxed/simple; bh=VXMeEzCpt7byvNMipZoteX6Lo9p/O94MNW8zdQ1oez8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; 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(ksk4725@coasia.com@115.23.218.194) by 192.168.10.159 with ESMTP; 10 Jul 2025 09:21:08 +0900 X-Original-SENDERIP: 115.23.218.194 X-Original-SENDERCOUNTRY: KR, South Korea X-Original-MAILFROM: ksk4725@coasia.com X-Original-RCPTTO: jesper.nilsson@axis.com, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, krzk@kernel.org, s.nawrocki@samsung.com, cw00.choi@samsung.com, alim.akhtar@samsung.com, linus.walleij@linaro.org, tomasz.figa@gmail.com, catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de, ravi.patel@samsung.com, ksk4725@coasia.com, smn1196@coasia.com, kenkim@coasia.com, pjsin865@coasia.com, gwk1013@coasia.com, hgkim05@coasia.com, mingyoungbo@coasia.com, pankaj.dubey@samsung.com, shradha.t@samsung.com, inbaraj.e@samsung.com, swathi.ks@samsung.com, hrishikesh.d@samsung.com, dj76.yang@samsung.com, hypmean.kim@samsung.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@axis.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, soc@lists.linux.dev From: ksk4725@coasia.com To: Jesper Nilsson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krzysztof Kozlowski , Sylwester Nawrocki , Chanwoo Choi , Alim Akhtar , Linus Walleij , Tomasz Figa , Catalin Marinas , Will Deacon , Arnd Bergmann , Ravi Patel , SeonGu Kang , SungMin Park Cc: kenkim , Jongshin Park , GunWoo Kim , HaGyeong Kim , GyoungBo Min , Pankaj Dubey , Shradha Todi , Inbaraj E , Swathi K S , Hrishikesh , Dongjin Yang , Sang Min Kim , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@axis.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, soc@lists.linux.dev Subject: [PATCH 15/16] arm64: dts: axis: Add initial pinctrl support Date: Thu, 10 Jul 2025 09:20:45 +0900 Message-Id: <20250710002047.1573841-16-ksk4725@coasia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250710002047.1573841-1-ksk4725@coasia.com> References: <20250710002047.1573841-1-ksk4725@coasia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: SeonGu Kang Add initial pin configuration nodes for the Axis ARTPEC-8 SoC. Signed-off-by: Ravi Patel Signed-off-by: SeonGu Kang --- arch/arm64/boot/dts/axis/artpec-pinctrl.h | 36 ++ arch/arm64/boot/dts/axis/artpec8-grizzly.dts | 1 + arch/arm64/boot/dts/axis/artpec8-pinctrl.dtsi | 373 ++++++++++++++++++ arch/arm64/boot/dts/axis/artpec8.dtsi | 17 + 4 files changed, 427 insertions(+) create mode 100644 arch/arm64/boot/dts/axis/artpec-pinctrl.h create mode 100644 arch/arm64/boot/dts/axis/artpec8-pinctrl.dtsi diff --git a/arch/arm64/boot/dts/axis/artpec-pinctrl.h b/arch/arm64/boot/dt= s/axis/artpec-pinctrl.h new file mode 100644 index 000000000000..c2c1e25b7f6a --- /dev/null +++ b/arch/arm64/boot/dts/axis/artpec-pinctrl.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Axis ARTPEC-8 SoC device tree pinctrl constants + * + * Copyright (c) 2022-2025 Samsung Electronics Co., Ltd. + * https://www.samsung.com + * Copyright (c) 2022-2025 Axis Communications AB. + * https://www.axis.com + */ + +#ifndef __DTS_ARM64_AXIS_ARTPEC_PINCTRL_H__ +#define __DTS_ARM64_AXIS_ARTPEC_PINCTRL_H__ + +#define ARTPEC_PIN_PULL_NONE 0 +#define ARTPEC_PIN_PULL_DOWN 1 +#define ARTPEC_PIN_PULL_UP 3 + +#define ARTPEC_PIN_FUNC_INPUT 0 +#define ARTPEC_PIN_FUNC_OUTPUT 1 +#define ARTPEC_PIN_FUNC_2 2 +#define ARTPEC_PIN_FUNC_3 3 +#define ARTPEC_PIN_FUNC_4 4 +#define ARTPEC_PIN_FUNC_5 5 +#define ARTPEC_PIN_FUNC_6 6 +#define ARTPEC_PIN_FUNC_EINT 0xf +#define ARTPEC_PIN_FUNC_F ARTPEC_PIN_FUNC_EINT + +/* Drive strength for ARTPEC */ +#define ARTPEC_PIN_DRV_SR1 0x8 +#define ARTPEC_PIN_DRV_SR2 0x9 +#define ARTPEC_PIN_DRV_SR3 0xa +#define ARTPEC_PIN_DRV_SR4 0xb +#define ARTPEC_PIN_DRV_SR5 0xc +#define ARTPEC_PIN_DRV_SR6 0xd + +#endif /* __DTS_ARM64_AXIS_ARTPEC_PINCTRL_H__ */ diff --git a/arch/arm64/boot/dts/axis/artpec8-grizzly.dts b/arch/arm64/boot= /dts/axis/artpec8-grizzly.dts index 7671130a0333..f14420e76188 100644 --- a/arch/arm64/boot/dts/axis/artpec8-grizzly.dts +++ b/arch/arm64/boot/dts/axis/artpec8-grizzly.dts @@ -10,6 +10,7 @@ =20 /dts-v1/; #include "artpec8.dtsi" +#include "artpec8-pinctrl.dtsi" #include / { model =3D "ARTPEC-8 grizzly board"; diff --git a/arch/arm64/boot/dts/axis/artpec8-pinctrl.dtsi b/arch/arm64/boo= t/dts/axis/artpec8-pinctrl.dtsi new file mode 100644 index 000000000000..2d22a8be9d61 --- /dev/null +++ b/arch/arm64/boot/dts/axis/artpec8-pinctrl.dtsi @@ -0,0 +1,373 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Axis ARTPEC-8 SoC pin-mux and pin-config device tree source + * + * Copyright (c) 2022-2025 Samsung Electronics Co., Ltd. + * https://www.samsung.com + * Copyright (c) 2022-2025 Axis Communications AB. + * https://www.axis.com + */ + +#include "artpec-pinctrl.h" + +&pinctrl_fsys { + serial0_bus: serial0-bus-pins { + samsung,pins =3D "gpf4-4", "gpf4-5"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + samsung,pin-drv =3D ; + }; + + qspi_clk: qspi-clk-pins { + samsung,pins =3D "gpf0-2"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + samsung,pin-drv =3D ; + }; + + qspi_data: qspi-data-pins { + samsung,pins =3D "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + samsung,pin-drv =3D ; + }; + + gpf0: gpf0-gpio-bank { + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + gpf1: gpf1-gpio-bank { + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + gpf2: gpf2-gpio-bank { + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + gpf3: gpf3-gpio-bank { + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + gpf4: gpf4-gpio-bank { + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + gpe0: gpe0-gpio-bank { + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + gpe1: gpe1-gpio-bank { + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + gpe2: gpe2-gpio-bank { + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + gps0: gps0-gpio-bank { + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + gps1: gps1-gpio-bank { + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + hsi2c0_bus: hsi2c0-bus-pins { + samsung,pins =3D "gpf4-0", "gpf4-1"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + samsung,pin-drv =3D ; + }; + + hsi2c1_bus: hsi2c1-bus-pins { + samsung,pins =3D "gpf4-2", "gpf4-3"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + samsung,pin-drv =3D ; + }; + + pwm0_out: pwm0-out-pins { + samsung,pins =3D "gpf3-0"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + samsung,pin-drv =3D ; + }; + + pwm1_out: pwm1-out-pins { + samsung,pins =3D "gpf3-1"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + samsung,pin-drv =3D ; + }; + + pwm2_out: pwm2-out-pins { + samsung,pins =3D "gpf3-2"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + samsung,pin-drv =3D ; + }; + + pwm3_out: pwm3-out-pins { + samsung,pins =3D "gpf3-3"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + samsung,pin-drv =3D ; + }; + + mmc0_clk: mmc0-clk-pins { + samsung,pins =3D "gps0-0"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + samsung,pin-drv =3D ; + }; + + mmc0_bus: mmc0-bus-pins { + samsung,pins =3D "gps0-1", "gps0-2", "gps0-3", "gps0-4", "gps0-5"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + samsung,pin-drv =3D ; + }; + + mmc0_cd: mmc0-cd-pins { + samsung,pins =3D "gps0-6"; + samsung,pin-pud =3D ; + samsung,pin-drv =3D ; + }; + + mmc0_wp: mmc0-wp-pins { + samsung,pins =3D "gps0-7"; + samsung,pin-pud =3D ; + samsung,pin-drv =3D ; + }; + + mmc0_rst: mmc0-rst-pins { + samsung,pins =3D "gps0-7"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + samsung,pin-drv =3D ; + }; + + mmc1_clk: mmc1-clk-pins { + samsung,pins =3D "gps1-0"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + samsung,pin-drv =3D ; + }; + + mmc1_bus: mmc1-bus-pins { + samsung,pins =3D "gps1-1", "gps1-2", "gps1-3", "gps1-4", "gps1-5"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + samsung,pin-drv =3D ; + }; + + mmc1_cd: mmc1-cd-pins { + samsung,pins =3D "gps1-6"; + samsung,pin-pud =3D ; + samsung,pin-drv =3D ; + }; + + mmc1_wp: mmc1-wp-pins { + samsung,pins =3D "gps1-7"; + samsung,pin-pud =3D ; + samsung,pin-drv =3D ; + }; + + mmc1_rst: mmc1-rst-pins { + samsung,pins =3D "gps1-7"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + samsung,pin-drv =3D ; + }; + + eth_gpio: eth-gpio-pins { + samsung,pins =3D "gpe1-0", "gpe1-1", "gpe1-2", "gpe1-3", "gpe1-4", + "gpe1-5", "gpe1-6", "gpe1-7", "gpe0-0", "gpe0-1", + "gpe0-2", "gpe0-3", "gpe0-4", "gpe0-5", "gpe0-6", + "gpe0-7", "gpe2-1"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + samsung,pin-drv =3D ; + }; + + eth_mdio: eth-mdio-pins { + samsung,pins =3D "gpe2-0"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + samsung,pin-drv =3D ; + }; + + eth_ref_clk: eth-ref-clk-pins { + samsung,pins =3D "gpe2-2"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + samsung,pin-drv =3D ; + }; + + eth_gtx_clk: eth-gtx-clk-pins { + samsung,pins =3D "gpe2-2"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + samsung,pin-drv =3D ; + }; + + eth_phy_intr: eth-phy-intr-pins { + samsung,pins =3D "gpe2-4"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + samsung,pin-drv =3D ; + }; + + eth_pps: eth-pps-pins { + samsung,pins =3D "gpf4-6"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + samsung,pin-drv =3D ; + }; + + sfmc_ctrl: sfmc-ctrl-pins { + samsung,pins =3D "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3", + "gpf0-4", "gpf1-0", "gpf1-1", "gpf1-2"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + samsung,pin-drv =3D ; + }; + + sfmc_io: sfmc-io-pins { + samsung,pins =3D "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3", "gpf2-4", + "gpf2-5", "gpf2-6", "gpf2-7"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + samsung,pin-drv =3D ; + }; +}; + +&pinctrl_peric { + serial1_bus: serial1-bus-pins { + samsung,pins =3D "gpa2-0", "gpa2-1", "gpa2-2", "gpa2-3"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + samsung,pin-drv =3D ; + }; + + serial2_bus: serial2-bus-pins { + samsung,pins =3D "gpa2-4", "gpa2-5", "gpa2-6", "gpa2-7"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + samsung,pin-drv =3D ; + }; + + spi0_bus: spi0-bus-pins { + samsung,pins =3D "gpa0-0", "gpa0-1", "gpa0-2", "gpa0-3"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + samsung,pin-drv =3D ; + }; + + spi0_bus_nocs: spi0-bus-nocs-pins { + samsung,pins =3D "gpa0-0", "gpa0-1", "gpa0-2"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + samsung,pin-drv =3D ; + }; + + gpa0: gpa0-gpio-bank { + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + gpa1: gpa1-gpio-bank { + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + gpa2: gpa2-gpio-bank { + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + gpk0: gpk0-gpio-bank { + gpio-controller; + #gpio-cells =3D <2>; + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + i2s0_bus: i2s0-bus-pins { + samsung,pins =3D "gpa1-4", "gpa1-5", "gpa1-6", "gpa1-7"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + samsung,pin-drv =3D ; + }; + + i2s0_idle: i2s0-idle-pins { + samsung,pins =3D "gpa1-4", "gpa1-5", "gpa1-6", "gpa1-7"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + samsung,pin-drv =3D ; + }; + + i2s1_bus: i2s1-bus-pins { + samsung,pins =3D "gpa1-0", "gpa1-1", "gpa1-2", "gpa1-3"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + samsung,pin-drv =3D ; + }; + + i2s1_idle: i2s1-idle-pins { + samsung,pins =3D "gpa1-0", "gpa1-1", "gpa1-2", "gpa1-3"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + samsung,pin-drv =3D ; + }; + + hsi2c2_bus: hsi2c2-bus-pins { + samsung,pins =3D "gpa0-6", "gpa0-7"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + samsung,pin-drv =3D ; + }; + + hsi2c3_bus: hsi2c3-bus-pins { + samsung,pins =3D "gpa0-4", "gpa0-5"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + samsung,pin-drv =3D ; + }; +}; diff --git a/arch/arm64/boot/dts/axis/artpec8.dtsi b/arch/arm64/boot/dts/ax= is/artpec8.dtsi index 296192560adf..9c2afbac75b9 100644 --- a/arch/arm64/boot/dts/axis/artpec8.dtsi +++ b/arch/arm64/boot/dts/axis/artpec8.dtsi @@ -17,6 +17,11 @@ / { #address-cells =3D <2>; #size-cells =3D <2>; =20 + aliases { + pinctrl0 =3D &pinctrl_fsys; + pinctrl1 =3D &pinctrl_peric; + }; + cpus { #address-cells =3D <1>; #size-cells =3D <0>; @@ -237,6 +242,18 @@ cmu_peri: clock-controller@16410000 { status =3D "disabled"; }; =20 + pinctrl_fsys: pinctrl@16c30000 { + compatible =3D "axis,artpec8-pinctrl"; + reg =3D <0x16c30000 0x1000>; + interrupts =3D ; + }; + + pinctrl_peric: pinctrl@165f0000 { + compatible =3D "axis,artpec8-pinctrl"; + reg =3D <0x165f0000 0x1000>; + interrupts =3D ; + }; + serial_0: serial@16cc0000 { compatible =3D "axis,artpec8-uart"; reg =3D <0x16cc0000 0x100>; --=20 2.34.1 From nobody Tue Dec 23 12:18:25 2025 Received: from spam.coasia.com (mail2.coasia.com [112.168.119.159]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 882AD1DFDB9 for ; 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(ksk4725@coasia.com@115.23.218.194) by 192.168.10.159 with ESMTP; 10 Jul 2025 09:21:10 +0900 X-Original-SENDERIP: 115.23.218.194 X-Original-SENDERCOUNTRY: KR, South Korea X-Original-MAILFROM: ksk4725@coasia.com X-Original-RCPTTO: jesper.nilsson@axis.com, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, krzk@kernel.org, s.nawrocki@samsung.com, cw00.choi@samsung.com, alim.akhtar@samsung.com, linus.walleij@linaro.org, tomasz.figa@gmail.com, catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de, kenkim@coasia.com, pjsin865@coasia.com, gwk1013@coasia.com, ksk4725@coasia.com, hgkim05@coasia.com, mingyoungbo@coasia.com, smn1196@coasia.com, pankaj.dubey@samsung.com, shradha.t@samsung.com, ravi.patel@samsung.com, inbaraj.e@samsung.com, swathi.ks@samsung.com, hrishikesh.d@samsung.com, dj76.yang@samsung.com, hypmean.kim@samsung.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@axis.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, soc@lists.linux.dev From: ksk4725@coasia.com To: Jesper Nilsson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krzysztof Kozlowski , Sylwester Nawrocki , Chanwoo Choi , Alim Akhtar , Linus Walleij , Tomasz Figa , Catalin Marinas , Will Deacon , Arnd Bergmann Cc: kenkim , Jongshin Park , GunWoo Kim , SeonGu Kang , HaGyeong Kim , GyoungBo Min , SungMin Park , Pankaj Dubey , Shradha Todi , Ravi Patel , Inbaraj E , Swathi K S , Hrishikesh , Dongjin Yang , Sang Min Kim , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@axis.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, soc@lists.linux.dev Subject: [PATCH 16/16] arm64: defconfig: Enable Axis ARTPEC SoC Date: Thu, 10 Jul 2025 09:20:46 +0900 Message-Id: <20250710002047.1573841-17-ksk4725@coasia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250710002047.1573841-1-ksk4725@coasia.com> References: <20250710002047.1573841-1-ksk4725@coasia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: sungminpark Enable the Axis ARTPEC-8 SoC in arm64 defconfig. Signed-off-by: sungminpark --- arch/arm64/configs/defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 5bb8f09422a2..00b902c2d997 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -38,6 +38,8 @@ CONFIG_ARCH_AIROHA=3Dy CONFIG_ARCH_SUNXI=3Dy CONFIG_ARCH_ALPINE=3Dy CONFIG_ARCH_APPLE=3Dy +CONFIG_ARCH_ARTPEC=3Dy +CONFIG_ARCH_ARTPEC8=3Dy CONFIG_ARCH_BCM=3Dy CONFIG_ARCH_BCM2835=3Dy CONFIG_ARCH_BCM_IPROC=3Dy --=20 2.34.1