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Thu, 10 Jul 2025 05:27:58 +0000 (GMT) Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 56A5RvHt018797 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 10 Jul 2025 05:27:57 GMT Received: from yuanfang4-gv.ap.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 9 Jul 2025 22:27:53 -0700 From: Yuanfang Zhang Date: Thu, 10 Jul 2025 13:27:20 +0800 Subject: [PATCH v11 1/2] dt-bindings: arm: Add device Trace Network On Chip definition Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250710-trace-noc-v11-1-f849075c40b8@quicinc.com> References: <20250710-trace-noc-v11-0-f849075c40b8@quicinc.com> In-Reply-To: <20250710-trace-noc-v11-0-f849075c40b8@quicinc.com> To: Suzuki K Poulose , Mike Leach , James Clark , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alexander Shishkin CC: , , , , , , Yuanfang Zhang , Krzysztof Kozlowski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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TNOC is an integration hierarchy which is a hardware component that integrates the functionalities of TPDA and funnels. It collects trace form subsystems and transfers to coresight sink. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Yuanfang Zhang --- .../bindings/arm/qcom,coresight-tnoc.yaml | 113 +++++++++++++++++= ++++ 1 file changed, 113 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-tnoc.yaml= b/Documentation/devicetree/bindings/arm/qcom,coresight-tnoc.yaml new file mode 100644 index 0000000000000000000000000000000000000000..9d1c93a9ade3ff14ede4a8d1481= 782776cf47be9 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-tnoc.yaml @@ -0,0 +1,113 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/qcom,coresight-tnoc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Trace Network On Chip - TNOC + +maintainers: + - Yuanfang Zhang + +description: > + The Trace Network On Chip (TNOC) is an integration hierarchy hardware + component that integrates the functionalities of TPDA and funnels. + + It sits in the different subsystem of SOC and aggregates the trace and + transports it to Aggregation TNOC or to coresight trace sink eventually. + TNOC embeds bridges for all the interfaces APB, ATB, TPDA and NTS (Narrow + Time Stamp). + + TNOC can take inputs from different trace sources i.e. ATB, TPDM. + + Note this binding is specifically intended for Aggregator TNOC instances. + +# Need a custom select here or 'arm,primecell' will match on lots of nodes +select: + properties: + compatible: + contains: + enum: + - qcom,coresight-tnoc + required: + - compatible + +properties: + $nodename: + pattern: "^tn(@[0-9a-f]+)$" + + compatible: + items: + - const: qcom,coresight-tnoc + - const: arm,primecell + + reg: + maxItems: 1 + + clock-names: + items: + - const: apb_pclk + + clocks: + items: + - description: APB register access clock + + in-ports: + $ref: /schemas/graph.yaml#/properties/ports + + patternProperties: + '^port(@[0-9a-f]{1,2})?$': + description: Input connections from CoreSight Trace Bus + $ref: /schemas/graph.yaml#/properties/port + + out-ports: + $ref: /schemas/graph.yaml#/properties/ports + additionalProperties: false + + properties: + port: + description: + Output connection to CoreSight Trace Bus + $ref: /schemas/graph.yaml#/properties/port + +required: + - compatible + - reg + - clocks + - clock-names + - in-ports + - out-ports + +additionalProperties: false + +examples: + - | + tn@109ab000 { + compatible =3D "qcom,coresight-tnoc", "arm,primecell"; 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It aggregates the trace and transports to coresight trace bus. Compared to current configuration, it has the following advantages: 1. Reduce wires between subsystems. 2. Continue cleaning the infrastructure. 3. Reduce Data overhead by transporting raw data from source to target. +------------------------+ +-------------------------+ | Video Subsystem | |Video Subsystem | | +-------------+ | | +------------+ | | | Video TPDM | | | | Video TPDM | | | +-------------+ | | +------------+ | | | | | | | | v | | v | | +---------------+ | | +-----------+ | | | Video funnel | | | |Video TNOC | | | +---------------+ | | +-----------+ | +------------|-----------+ +------------|------------+ | | v-----+ | +--------------------|---------+ | | Multimedia v | | | Subsystem +--------+ | | | | TPDA | | v | +----|---+ | +---------------------+ | | | | Aggregator TNOC | | | | +----------|----------+ | +-- | | | | | | | | | | | +------v-----+ | | | | Funnel | | | | +------------+ | | +----------------|-------------+ | | | v v +--------------------+ +------------------+ | Coresight Sink | | Coresight Sink | +--------------------+ +------------------+ Current Configuration TNOC Reviewed-by: Leo Yan Signed-off-by: Yuanfang Zhang Reviewed-by: Mike Leach --- drivers/hwtracing/coresight/Kconfig | 12 ++ drivers/hwtracing/coresight/Makefile | 1 + drivers/hwtracing/coresight/coresight-tnoc.c | 242 +++++++++++++++++++++++= ++++ 3 files changed, 255 insertions(+) diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresi= ght/Kconfig index f064e3d172b3d630515bb3a11450e883a6b5b4bf..6a4239ebb582e95f0ebe8e9c873= 8a726f27f60a1 100644 --- a/drivers/hwtracing/coresight/Kconfig +++ b/drivers/hwtracing/coresight/Kconfig @@ -268,4 +268,16 @@ config CORESIGHT_KUNIT_TESTS Enable Coresight unit tests. Only useful for development and not intended for production. =20 +config CORESIGHT_TNOC + tristate "Coresight Trace Network On Chip driver" + help + This driver provides support for Trace Network On Chip (TNOC) component. + TNOC is an interconnect used to collect traces from various subsystems + and transport to a coresight trace sink. It sits in the different + tiles of SOC and aggregates the trace local to the tile and transports + it another tile or to coresight trace sink eventually. + + To compile this driver as a module, choose M here: the module will be + called coresight-tnoc. + endif diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/cores= ight/Makefile index 4e7cc3c5bf994d4066adc3b6c203edd19e88a823..ab16d06783a572ea1308dfb3a30= c96df9e5ffdb7 100644 --- a/drivers/hwtracing/coresight/Makefile +++ b/drivers/hwtracing/coresight/Makefile @@ -36,6 +36,7 @@ obj-$(CONFIG_CORESIGHT_SINK_TPIU) +=3D coresight-tpiu.o obj-$(CONFIG_CORESIGHT_SINK_ETBV10) +=3D coresight-etb10.o obj-$(CONFIG_CORESIGHT_LINKS_AND_SINKS) +=3D coresight-funnel.o \ coresight-replicator.o +obj-$(CONFIG_CORESIGHT_TNOC) +=3D coresight-tnoc.o obj-$(CONFIG_CORESIGHT_SOURCE_ETM3X) +=3D coresight-etm3x.o coresight-etm3x-y :=3D coresight-etm3x-core.o coresight-etm-cp14.o \ coresight-etm3x-sysfs.o diff --git a/drivers/hwtracing/coresight/coresight-tnoc.c b/drivers/hwtraci= ng/coresight/coresight-tnoc.c new file mode 100644 index 0000000000000000000000000000000000000000..0e4164707eea974e6f34d2de016= 93354d6eefdcd --- /dev/null +++ b/drivers/hwtracing/coresight/coresight-tnoc.c @@ -0,0 +1,242 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. + */ + + #include + #include + #include + #include + #include + #include + #include + #include + +#include "coresight-priv.h" +#include "coresight-trace-id.h" + +#define TRACE_NOC_CTRL 0x008 +#define TRACE_NOC_XLD 0x010 +#define TRACE_NOC_FREQVAL 0x018 +#define TRACE_NOC_SYNCR 0x020 + +/* Enable generation of output ATB traffic.*/ +#define TRACE_NOC_CTRL_PORTEN BIT(0) +/* Sets the type of issued ATB FLAG packets.*/ +#define TRACE_NOC_CTRL_FLAGTYPE BIT(7) +/* Sets the type of issued ATB FREQ packet*/ +#define TRACE_NOC_CTRL_FREQTYPE BIT(8) + +#define TRACE_NOC_SYNC_INTERVAL 0xFFFF + +/* + * struct trace_noc_drvdata - specifics associated to a trace noc component + * @base: memory mapped base address for this component. + * @dev: device node for trace_noc_drvdata. + * @csdev: component vitals needed by the framework. + * @spinlock: serialize enable/disable operation. + * @atid: id for the trace packet. + */ +struct trace_noc_drvdata { + void __iomem *base; + struct device *dev; + struct coresight_device *csdev; + spinlock_t spinlock; + u32 atid; +}; + +DEFINE_CORESIGHT_DEVLIST(trace_noc_devs, "traceNoc"); + +static void trace_noc_enable_hw(struct trace_noc_drvdata *drvdata) +{ + u32 val; + + /* Set ATID */ + writel_relaxed(drvdata->atid, drvdata->base + TRACE_NOC_XLD); + + /* Set the data word count between 'SYNC' packets */ + writel_relaxed(TRACE_NOC_SYNC_INTERVAL, drvdata->base + TRACE_NOC_SYNCR); + + /* Set the Control register: + * - Set the FLAG packets to 'FLAG' packets + * - Set the FREQ packets to 'FREQ_TS' packets + * - Enable generation of output ATB traffic + */ + + val =3D readl_relaxed(drvdata->base + TRACE_NOC_CTRL); + + val &=3D ~TRACE_NOC_CTRL_FLAGTYPE; + val |=3D TRACE_NOC_CTRL_FREQTYPE; + val |=3D TRACE_NOC_CTRL_PORTEN; + + writel(val, drvdata->base + TRACE_NOC_CTRL); +} + +static int trace_noc_enable(struct coresight_device *csdev, struct coresig= ht_connection *inport, + struct coresight_connection *outport) +{ + struct trace_noc_drvdata *drvdata =3D dev_get_drvdata(csdev->dev.parent); + + scoped_guard(spinlock, &drvdata->spinlock) { + if (csdev->refcnt =3D=3D 0) + trace_noc_enable_hw(drvdata); + + csdev->refcnt++; + } + + dev_dbg(drvdata->dev, "Trace NOC is enabled\n"); + return 0; +} + +static void trace_noc_disable(struct coresight_device *csdev, struct cores= ight_connection *inport, + struct coresight_connection *outport) +{ + struct trace_noc_drvdata *drvdata =3D dev_get_drvdata(csdev->dev.parent); + + scoped_guard(spinlock, &drvdata->spinlock) { + if (--csdev->refcnt =3D=3D 0) + writel(0x0, drvdata->base + TRACE_NOC_CTRL); + } + dev_dbg(drvdata->dev, "Trace NOC is disabled\n"); +} + +static int trace_noc_id(struct coresight_device *csdev, __maybe_unused enu= m cs_mode mode, + __maybe_unused struct coresight_device *sink) +{ + struct trace_noc_drvdata *drvdata; + + drvdata =3D dev_get_drvdata(csdev->dev.parent); + + return drvdata->atid; +} + +static const struct coresight_ops_link trace_noc_link_ops =3D { + .enable =3D trace_noc_enable, + .disable =3D trace_noc_disable, +}; + +static const struct coresight_ops trace_noc_cs_ops =3D { + .trace_id =3D trace_noc_id, + .link_ops =3D &trace_noc_link_ops, +}; + +static int trace_noc_init_default_data(struct trace_noc_drvdata *drvdata) +{ + int atid; + + atid =3D coresight_trace_id_get_system_id(); + if (atid < 0) + return atid; + + drvdata->atid =3D atid; + + return 0; +} + +static ssize_t traceid_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + unsigned long val; + struct trace_noc_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + + val =3D drvdata->atid; + return sprintf(buf, "%#lx\n", val); +} +static DEVICE_ATTR_RO(traceid); + +static struct attribute *coresight_tnoc_attrs[] =3D { + &dev_attr_traceid.attr, + NULL, +}; + +static const struct attribute_group coresight_tnoc_group =3D { + .attrs =3D coresight_tnoc_attrs, +}; + +static const struct attribute_group *coresight_tnoc_groups[] =3D { + &coresight_tnoc_group, + NULL, +}; + +static int trace_noc_probe(struct amba_device *adev, const struct amba_id = *id) +{ + struct device *dev =3D &adev->dev; + struct coresight_platform_data *pdata; + struct trace_noc_drvdata *drvdata; + struct coresight_desc desc =3D { 0 }; + int ret; + + desc.name =3D coresight_alloc_device_name(&trace_noc_devs, dev); + if (!desc.name) + return -ENOMEM; + + pdata =3D coresight_get_platform_data(dev); + if (IS_ERR(pdata)) + return PTR_ERR(pdata); + adev->dev.platform_data =3D pdata; + + drvdata =3D devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); + if (!drvdata) + return -ENOMEM; + + drvdata->dev =3D &adev->dev; + dev_set_drvdata(dev, drvdata); + + drvdata->base =3D devm_ioremap_resource(dev, &adev->res); + if (!drvdata->base) + return -ENOMEM; + + spin_lock_init(&drvdata->spinlock); + + ret =3D trace_noc_init_default_data(drvdata); + if (ret) + return ret; + + desc.ops =3D &trace_noc_cs_ops; + desc.type =3D CORESIGHT_DEV_TYPE_LINK; + desc.subtype.link_subtype =3D CORESIGHT_DEV_SUBTYPE_LINK_MERG; + desc.pdata =3D adev->dev.platform_data; + desc.dev =3D &adev->dev; + desc.access =3D CSDEV_ACCESS_IOMEM(drvdata->base); + desc.groups =3D coresight_tnoc_groups; + drvdata->csdev =3D coresight_register(&desc); + if (IS_ERR(drvdata->csdev)) { + coresight_trace_id_put_system_id(drvdata->atid); + return PTR_ERR(drvdata->csdev); + } + pm_runtime_put(&adev->dev); + + return 0; +} + +static void trace_noc_remove(struct amba_device *adev) +{ + struct trace_noc_drvdata *drvdata =3D dev_get_drvdata(&adev->dev); + + coresight_unregister(drvdata->csdev); + coresight_trace_id_put_system_id(drvdata->atid); +} + +static struct amba_id trace_noc_ids[] =3D { + { + .id =3D 0x000f0c00, + .mask =3D 0x00ffff00, + }, + {}, +}; +MODULE_DEVICE_TABLE(amba, trace_noc_ids); + +static struct amba_driver trace_noc_driver =3D { + .drv =3D { + .name =3D "coresight-trace-noc", + .suppress_bind_attrs =3D true, + }, + .probe =3D trace_noc_probe, + .remove =3D trace_noc_remove, + .id_table =3D trace_noc_ids, +}; + +module_amba_driver(trace_noc_driver); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Trace NOC driver"); --=20 2.34.1