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Thu, 10 Jul 2025 08:59:06 +0000 (GMT) Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 56A8x5N5009818 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 10 Jul 2025 08:59:05 GMT Received: from hu-vpernami-hyd.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Thu, 10 Jul 2025 01:59:04 -0700 From: Vivek.Pernamitta@quicinc.com Date: Thu, 10 Jul 2025 14:28:34 +0530 Subject: [PATCH v2 3/5] bus: mhi: host: pci_generic: Remove MHI driver and ensure graceful device recovery Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250710-sriov_vdev_next-20250630-v2-3-4bd862b822e8@quicinc.com> References: <20250710-sriov_vdev_next-20250630-v2-0-4bd862b822e8@quicinc.com> In-Reply-To: <20250710-sriov_vdev_next-20250630-v2-0-4bd862b822e8@quicinc.com> To: Manivannan Sadhasivam CC: , , , Vivek Pernamitta X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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To achieve this, the host driver will perform the following steps: 1. Disable SRIOV for any SRIOV-enabled devices on the Physical Function. 2. Perform a SOC_RESET on Physical Function (PF). Disabling SRIOV ensures that all virtual functions are properly shut down, preventing any potential issues during the reset process. Performing SOC_RESET on each physical function guarantees that the device is fully reset and ready for subsequent operations. Signed-off-by: Vivek Pernamitta --- drivers/bus/mhi/host/pci_generic.c | 26 +++++++++++++++++++++++++- 1 file changed, 25 insertions(+), 1 deletion(-) diff --git a/drivers/bus/mhi/host/pci_generic.c b/drivers/bus/mhi/host/pci_= generic.c index 4bafe93b56c54e2b091786e7fcd68a36c8247b8e..2d1381006293412fbc593316e5c= 7f0f59ac74da8 100644 --- a/drivers/bus/mhi/host/pci_generic.c +++ b/drivers/bus/mhi/host/pci_generic.c @@ -45,6 +45,8 @@ * @sideband_wake: Devices using dedicated sideband GPIO for wakeup instead * of inband wake support (such as sdx24) * @no_m3: M3 not supported + * @reset_on_driver_unbind: Set true for devices support SOC reset and + * perform it when unbinding driver */ struct mhi_pci_dev_info { const struct mhi_controller_config *config; @@ -58,6 +60,7 @@ struct mhi_pci_dev_info { unsigned int mru_default; bool sideband_wake; bool no_m3; + bool reset_on_driver_unbind; }; =20 #define MHI_CHANNEL_CONFIG_UL(ch_num, ch_name, el_count, ev_ring) \ @@ -300,6 +303,7 @@ static const struct mhi_pci_dev_info mhi_qcom_qdu100_in= fo =3D { .dma_data_width =3D 32, .sideband_wake =3D false, .no_m3 =3D true, + .reset_on_driver_unbind =3D true, }; =20 static const struct mhi_channel_config mhi_qcom_sa8775p_channels[] =3D { @@ -970,6 +974,7 @@ struct mhi_pci_device { struct work_struct recovery_work; struct timer_list health_check_timer; unsigned long status; + bool reset_on_driver_unbind; }; =20 static int mhi_pci_read_reg(struct mhi_controller *mhi_cntrl, @@ -1270,6 +1275,11 @@ static int mhi_pci_probe(struct pci_dev *pdev, const= struct pci_device_id *id) mhi_cntrl->mru =3D info->mru_default; mhi_cntrl->name =3D info->name; =20 + /* Assign reset functionalities only for PF */ + if (pdev->is_physfn) + mhi_pdev->reset_on_driver_unbind =3D info->reset_on_driver_unbind; + + if (info->edl_trigger) mhi_cntrl->edl_trigger =3D mhi_pci_generic_edl_trigger; =20 @@ -1336,7 +1346,7 @@ static int mhi_pci_probe(struct pci_dev *pdev, const = struct pci_device_id *id) return err; } =20 -static void mhi_pci_remove(struct pci_dev *pdev) +static void mhi_pci_resource_deinit(struct pci_dev *pdev) { struct mhi_pci_device *mhi_pdev =3D pci_get_drvdata(pdev); struct mhi_controller *mhi_cntrl =3D &mhi_pdev->mhi_cntrl; @@ -1352,6 +1362,20 @@ static void mhi_pci_remove(struct pci_dev *pdev) /* balancing probe put_noidle */ if (pci_pme_capable(pdev, PCI_D3hot)) pm_runtime_get_noresume(&pdev->dev); +} + +static void mhi_pci_remove(struct pci_dev *pdev) +{ + struct mhi_pci_device *mhi_pdev =3D pci_get_drvdata(pdev); + struct mhi_controller *mhi_cntrl =3D &mhi_pdev->mhi_cntrl; + + /* Disable SRIOV */ + pci_disable_sriov(pdev); + mhi_pci_resource_deinit(pdev); + if (mhi_pdev->reset_on_driver_unbind) { + dev_info(&pdev->dev, "perform SOC reset\n"); + mhi_soc_reset(mhi_cntrl); + } =20 mhi_unregister_controller(mhi_cntrl); } --=20 2.34.1