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[73.183.52.120]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-70497d39749sm9670216d6.58.2025.07.10.09.08.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Jul 2025 09:08:22 -0700 (PDT) From: Brian Masney Date: Thu, 10 Jul 2025 12:07:16 -0400 Subject: [PATCH 6/9] phy: mediatek: phy-mtk-mipi-dsi-mt8183: convert from round_rate() to determine_rate() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250710-phy-clk-round-rate-v1-6-0ff274055e42@redhat.com> References: <20250710-phy-clk-round-rate-v1-0-0ff274055e42@redhat.com> In-Reply-To: <20250710-phy-clk-round-rate-v1-0-0ff274055e42@redhat.com> To: Vinod Koul , Kishon Vijay Abraham I , Chun-Kuang Hu , Philipp Zabel , Chunfeng Yun , Matthias Brugger , AngeloGioacchino Del Regno , Heiko Stuebner , Maxime Ripard , Stephen Boyd Cc: linux-clk@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, Brian Masney X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1752163685; l=1507; i=bmasney@redhat.com; s=20250528; h=from:subject:message-id; bh=ZKlsIvlM5HHyda796a+VTO47/qeucu/BCMXwHXG/S40=; b=+r3EuMe/pzh9qF2oPdX67HS2VmnZ350abewNM1edJtWvBPtHINXt26quhidSdRFg7SeVLEzsu YVJmnDogbgKAaAbXcN1nbXJrSBi27Fk+BJ7qXWfiPpZHj+x2CtpRepu X-Developer-Key: i=bmasney@redhat.com; a=ed25519; pk=x20f2BQYftANnik+wvlm4HqLqAlNs/npfVcbhHPOK2U= The round_rate() clk ops is deprecated, so migrate this driver from round_rate() to determine_rate() using the Coccinelle semantic patch on the cover letter of this series. Signed-off-by: Brian Masney --- drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8183.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8183.c b/drivers/phy/m= ediatek/phy-mtk-mipi-dsi-mt8183.c index 553725e1269c9d7ad88f89367dfa1cf367aaf1ce..a54d44ef70ab49937d210f04fdf= 42300e8e5f2de 100644 --- a/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8183.c +++ b/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8183.c @@ -97,16 +97,18 @@ static void mtk_mipi_tx_pll_disable(struct clk_hw *hw) mtk_phy_clear_bits(base + MIPITX_PLL_PWR, AD_DSI_PLL_SDM_PWR_ON); } =20 -static long mtk_mipi_tx_pll_round_rate(struct clk_hw *hw, unsigned long ra= te, - unsigned long *prate) +static int mtk_mipi_tx_pll_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { - return clamp_val(rate, 125000000, 1600000000); + req->rate =3D clamp_val(req->rate, 125000000, 1600000000); + + return 0; } =20 static const struct clk_ops mtk_mipi_tx_pll_ops =3D { .enable =3D mtk_mipi_tx_pll_enable, .disable =3D mtk_mipi_tx_pll_disable, - .round_rate =3D mtk_mipi_tx_pll_round_rate, + .determine_rate =3D mtk_mipi_tx_pll_determine_rate, .set_rate =3D mtk_mipi_tx_pll_set_rate, .recalc_rate =3D mtk_mipi_tx_pll_recalc_rate, }; --=20 2.50.0