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[73.183.52.120]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-70497d39749sm9670216d6.58.2025.07.10.09.08.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Jul 2025 09:08:09 -0700 (PDT) From: Brian Masney Date: Thu, 10 Jul 2025 12:07:11 -0400 Subject: [PATCH 1/9] phy: freescale: phy-fsl-samsung-hdmi: convert from round_rate() to determine_rate() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250710-phy-clk-round-rate-v1-1-0ff274055e42@redhat.com> References: <20250710-phy-clk-round-rate-v1-0-0ff274055e42@redhat.com> In-Reply-To: <20250710-phy-clk-round-rate-v1-0-0ff274055e42@redhat.com> To: Vinod Koul , Kishon Vijay Abraham I , Chun-Kuang Hu , Philipp Zabel , Chunfeng Yun , Matthias Brugger , AngeloGioacchino Del Regno , Heiko Stuebner , Maxime Ripard , Stephen Boyd Cc: linux-clk@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, Brian Masney X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1752163685; l=1978; i=bmasney@redhat.com; s=20250528; h=from:subject:message-id; bh=fKrbnjnqlbXKGKlsruK+qB8Kg9daZJZ+BBb5bsrBbyI=; b=KjDWEK+2W/Nntn7kgVA1LXI5UW998Hy2QzJ7T12w24jbptJPTQ20Hu1na1UrDrlq2m/ybtKHR 1nSX6rsyHP1DjtYMF4VJcw2r9wmw7SB7c7PmH5QSepXY2pM+05ltjYv X-Developer-Key: i=bmasney@redhat.com; a=ed25519; pk=x20f2BQYftANnik+wvlm4HqLqAlNs/npfVcbhHPOK2U= The round_rate() clk ops is deprecated, so migrate this driver from round_rate() to determine_rate() using the Coccinelle semantic patch on the cover letter of this series. Signed-off-by: Brian Masney --- drivers/phy/freescale/phy-fsl-samsung-hdmi.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/drivers/phy/freescale/phy-fsl-samsung-hdmi.c b/drivers/phy/fre= escale/phy-fsl-samsung-hdmi.c index 191c282246d96e3f6c5a8d17abe078892882bf44..d010fec15671d33cc363af79e9f= 1c3f26ecb3464 100644 --- a/drivers/phy/freescale/phy-fsl-samsung-hdmi.c +++ b/drivers/phy/freescale/phy-fsl-samsung-hdmi.c @@ -570,17 +570,20 @@ const struct phy_config *fsl_samsung_hdmi_phy_find_se= ttings(struct fsl_samsung_h return fract_div_phy; } =20 -static long fsl_samsung_hdmi_phy_clk_round_rate(struct clk_hw *hw, - unsigned long rate, unsigned long *parent_rate) +static int fsl_samsung_hdmi_phy_clk_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { struct fsl_samsung_hdmi_phy *phy =3D to_fsl_samsung_hdmi_phy(hw); - const struct phy_config *target_settings =3D fsl_samsung_hdmi_phy_find_se= ttings(phy, rate); + const struct phy_config *target_settings =3D fsl_samsung_hdmi_phy_find_se= ttings(phy, + req->rate); =20 if (target_settings =3D=3D NULL) return -EINVAL; =20 dev_dbg(phy->dev, "round_rate, closest rate =3D %u\n", target_settings->p= ixclk); - return target_settings->pixclk; + req->rate =3D target_settings->pixclk; + + return 0; } =20 static int fsl_samsung_hdmi_phy_clk_set_rate(struct clk_hw *hw, @@ -599,7 +602,7 @@ static int fsl_samsung_hdmi_phy_clk_set_rate(struct clk= _hw *hw, =20 static const struct clk_ops phy_clk_ops =3D { .recalc_rate =3D phy_clk_recalc_rate, - .round_rate =3D fsl_samsung_hdmi_phy_clk_round_rate, + .determine_rate =3D fsl_samsung_hdmi_phy_clk_determine_rate, .set_rate =3D fsl_samsung_hdmi_phy_clk_set_rate, }; =20 --=20 2.50.0 From nobody Tue Oct 7 09:57:02 2025 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A16472EFDB2 for ; Thu, 10 Jul 2025 16:08:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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[73.183.52.120]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-70497d39749sm9670216d6.58.2025.07.10.09.08.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Jul 2025 09:08:12 -0700 (PDT) From: Brian Masney Date: Thu, 10 Jul 2025 12:07:12 -0400 Subject: [PATCH 2/9] phy: mediatek: phy-mtk-hdmi-mt2701: convert from round_rate() to determine_rate() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250710-phy-clk-round-rate-v1-2-0ff274055e42@redhat.com> References: <20250710-phy-clk-round-rate-v1-0-0ff274055e42@redhat.com> In-Reply-To: <20250710-phy-clk-round-rate-v1-0-0ff274055e42@redhat.com> To: Vinod Koul , Kishon Vijay Abraham I , Chun-Kuang Hu , Philipp Zabel , Chunfeng Yun , Matthias Brugger , AngeloGioacchino Del Regno , Heiko Stuebner , Maxime Ripard , Stephen Boyd Cc: linux-clk@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, Brian Masney X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1752163685; l=1429; i=bmasney@redhat.com; s=20250528; h=from:subject:message-id; bh=iJAJsOBdjX5yU2h75u6+b08f3YAfQGGv0k5DSS+fdqc=; b=gM9Vog/PjfK+PD7kK6yqe+FHMUUn8OmRYlp0k9f9lt5ka6hie/ovQ2orPiYAUbVKPreNvVHLO BW8lUYOkRwPB/LUPMWdxoK3stAq+kbRSdWnBg6NGEyKUO9GNQDXxSDY X-Developer-Key: i=bmasney@redhat.com; a=ed25519; pk=x20f2BQYftANnik+wvlm4HqLqAlNs/npfVcbhHPOK2U= The round_rate() clk ops is deprecated, so migrate this driver from round_rate() to determine_rate() using the Coccinelle semantic patch on the cover letter of this series. Signed-off-by: Brian Masney --- drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c b/drivers/phy/media= tek/phy-mtk-hdmi-mt2701.c index e51b2d13eab473dddace48c75c2a8d73c8c65635..b0b6497e7eedcb6867541b573d2= 2156ded29a4d5 100644 --- a/drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c +++ b/drivers/phy/mediatek/phy-mtk-hdmi-mt2701.c @@ -90,10 +90,10 @@ static void mtk_hdmi_pll_unprepare(struct clk_hw *hw) usleep_range(80, 100); } =20 -static long mtk_hdmi_pll_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *parent_rate) +static int mtk_hdmi_pll_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { - return rate; + return 0; } =20 static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate, @@ -170,7 +170,7 @@ static const struct clk_ops mtk_hdmi_phy_pll_ops =3D { .prepare =3D mtk_hdmi_pll_prepare, .unprepare =3D mtk_hdmi_pll_unprepare, .set_rate =3D mtk_hdmi_pll_set_rate, - .round_rate =3D mtk_hdmi_pll_round_rate, + .determine_rate =3D mtk_hdmi_pll_determine_rate, .recalc_rate =3D mtk_hdmi_pll_recalc_rate, }; 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[73.183.52.120]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-70497d39749sm9670216d6.58.2025.07.10.09.08.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Jul 2025 09:08:15 -0700 (PDT) From: Brian Masney Date: Thu, 10 Jul 2025 12:07:13 -0400 Subject: [PATCH 3/9] phy: mediatek: phy-mtk-hdmi-mt8173: convert from round_rate() to determine_rate() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250710-phy-clk-round-rate-v1-3-0ff274055e42@redhat.com> References: <20250710-phy-clk-round-rate-v1-0-0ff274055e42@redhat.com> In-Reply-To: <20250710-phy-clk-round-rate-v1-0-0ff274055e42@redhat.com> To: Vinod Koul , Kishon Vijay Abraham I , Chun-Kuang Hu , Philipp Zabel , Chunfeng Yun , Matthias Brugger , AngeloGioacchino Del Regno , Heiko Stuebner , Maxime Ripard , Stephen Boyd Cc: linux-clk@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, Brian Masney X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1752163685; l=1767; i=bmasney@redhat.com; s=20250528; h=from:subject:message-id; bh=4qM0ky7zv1CT6MbG0sETVffzH28Znb5sgT9aMpTi5PM=; b=OlOFj1qtOHlC4RTSWWBUoK0UK6p8kJw7bEiAXyh697CDgkPWtlCgHYWxO4MvlcT4VtmGy896s MhkQvLZz992BJ4ENElsvaaczY9Qr1s/zBYA7f5mWOE8/m/uo3t62K5q X-Developer-Key: i=bmasney@redhat.com; a=ed25519; pk=x20f2BQYftANnik+wvlm4HqLqAlNs/npfVcbhHPOK2U= The round_rate() clk ops is deprecated, so migrate this driver from round_rate() to determine_rate() using the Coccinelle semantic patch on the cover letter of this series. Signed-off-by: Brian Masney --- drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c b/drivers/phy/media= tek/phy-mtk-hdmi-mt8173.c index d04758396046363ab9edc584ae10bf31e9c5fb0f..58c6596c8c20bdacf96a97709b8= f5709f447e85b 100644 --- a/drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c +++ b/drivers/phy/mediatek/phy-mtk-hdmi-mt8173.c @@ -118,18 +118,18 @@ static void mtk_hdmi_pll_unprepare(struct clk_hw *hw) usleep_range(100, 150); } =20 -static long mtk_hdmi_pll_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *parent_rate) +static int mtk_hdmi_pll_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { struct mtk_hdmi_phy *hdmi_phy =3D to_mtk_hdmi_phy(hw); =20 - hdmi_phy->pll_rate =3D rate; - if (rate <=3D 74250000) - *parent_rate =3D rate; + hdmi_phy->pll_rate =3D req->rate; + if (req->rate <=3D 74250000) + req->best_parent_rate =3D req->rate; else - *parent_rate =3D rate / 2; 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[73.183.52.120]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-70497d39749sm9670216d6.58.2025.07.10.09.08.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Jul 2025 09:08:17 -0700 (PDT) From: Brian Masney Date: Thu, 10 Jul 2025 12:07:14 -0400 Subject: [PATCH 4/9] phy: mediatek: phy-mtk-hdmi-mt8195: convert from round_rate() to determine_rate() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250710-phy-clk-round-rate-v1-4-0ff274055e42@redhat.com> References: <20250710-phy-clk-round-rate-v1-0-0ff274055e42@redhat.com> In-Reply-To: <20250710-phy-clk-round-rate-v1-0-0ff274055e42@redhat.com> To: Vinod Koul , Kishon Vijay Abraham I , Chun-Kuang Hu , Philipp Zabel , Chunfeng Yun , Matthias Brugger , AngeloGioacchino Del Regno , Heiko Stuebner , Maxime Ripard , Stephen Boyd Cc: linux-clk@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, Brian Masney X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1752163685; l=1601; i=bmasney@redhat.com; s=20250528; h=from:subject:message-id; bh=DwS1eyPB/neaQufQvNJoTsoU5XhXKJIB7F14A2pZwIo=; b=4cPcXNvbK3LJUngty9/hS4Cci5iNskdrVCzBboRgMF/vVZq4JO3qCRcMs3ZcshnLpFzqFvn2A ZJ4lm2QjCh4CBdhbHz6OimHjO2IugpTJTJVBSFGBISv7EeMJ0RGydsb X-Developer-Key: i=bmasney@redhat.com; a=ed25519; pk=x20f2BQYftANnik+wvlm4HqLqAlNs/npfVcbhHPOK2U= The round_rate() clk ops is deprecated, so migrate this driver from round_rate() to determine_rate() using the Coccinelle semantic patch on the cover letter of this series. Signed-off-by: Brian Masney --- drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c b/drivers/phy/media= tek/phy-mtk-hdmi-mt8195.c index b38f3ae26b3f3d8c9e73b43d86510acf6cedb471..1426a2db984d53b91125b18f772= 5738c44f19555 100644 --- a/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c +++ b/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c @@ -418,13 +418,13 @@ static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, u= nsigned long rate, return mtk_hdmi_pll_calc(hdmi_phy, hw, rate, parent_rate); } =20 -static long mtk_hdmi_pll_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *parent_rate) +static int mtk_hdmi_pll_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { struct mtk_hdmi_phy *hdmi_phy =3D to_mtk_hdmi_phy(hw); =20 - hdmi_phy->pll_rate =3D rate; - return rate; + hdmi_phy->pll_rate =3D req->rate; + return 0; } =20 static unsigned long mtk_hdmi_pll_recalc_rate(struct clk_hw *hw, @@ -439,7 +439,7 @@ static const struct clk_ops mtk_hdmi_pll_ops =3D { .prepare =3D mtk_hdmi_pll_prepare, .unprepare =3D mtk_hdmi_pll_unprepare, .set_rate =3D mtk_hdmi_pll_set_rate, - .round_rate =3D mtk_hdmi_pll_round_rate, + .determine_rate =3D mtk_hdmi_pll_determine_rate, .recalc_rate =3D mtk_hdmi_pll_recalc_rate, }; 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[73.183.52.120]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-70497d39749sm9670216d6.58.2025.07.10.09.08.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Jul 2025 09:08:19 -0700 (PDT) From: Brian Masney Date: Thu, 10 Jul 2025 12:07:15 -0400 Subject: [PATCH 5/9] phy: mediatek: phy-mtk-mipi-dsi-mt8173: convert from round_rate() to determine_rate() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250710-phy-clk-round-rate-v1-5-0ff274055e42@redhat.com> References: <20250710-phy-clk-round-rate-v1-0-0ff274055e42@redhat.com> In-Reply-To: <20250710-phy-clk-round-rate-v1-0-0ff274055e42@redhat.com> To: Vinod Koul , Kishon Vijay Abraham I , Chun-Kuang Hu , Philipp Zabel , Chunfeng Yun , Matthias Brugger , AngeloGioacchino Del Regno , Heiko Stuebner , Maxime Ripard , Stephen Boyd Cc: linux-clk@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, Brian Masney X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1752163685; l=1519; i=bmasney@redhat.com; s=20250528; h=from:subject:message-id; bh=Sp7TBqvADBjUTdYv865HJDuwxPugQD7l6ebJ7mJAKsk=; b=QdRXZy3WXcCDAKY+nITPfzBZtQ8RpvdKNlvOltT6ZNVcwHEAkVhWAcnk2UBWK7KubiIjAaW2b RaP8yKzs4UnCzedb/XCmTGOR6M6qboXHNuqR38QkPjLse9NBJ4Rx33V X-Developer-Key: i=bmasney@redhat.com; a=ed25519; pk=x20f2BQYftANnik+wvlm4HqLqAlNs/npfVcbhHPOK2U= The round_rate() clk ops is deprecated, so migrate this driver from round_rate() to determine_rate() using the Coccinelle semantic patch on the cover letter of this series. Signed-off-by: Brian Masney --- drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8173.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8173.c b/drivers/phy/m= ediatek/phy-mtk-mipi-dsi-mt8173.c index 673cb0f08959e0e4f2b1ade2ebaf796e8b76f8bc..438ff3605d90121b7bfe02b3ddc= a8194437ed9ba 100644 --- a/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8173.c +++ b/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8173.c @@ -237,16 +237,18 @@ static void mtk_mipi_tx_pll_unprepare(struct clk_hw *= hw) mtk_phy_clear_bits(base + MIPITX_DSI_PLL_CON0, RG_DSI_MPPLL_DIV_MSK); } =20 -static long mtk_mipi_tx_pll_round_rate(struct clk_hw *hw, unsigned long ra= te, - unsigned long *prate) +static int mtk_mipi_tx_pll_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { - return clamp_val(rate, 50000000, 1250000000); + req->rate =3D clamp_val(req->rate, 50000000, 1250000000); + + return 0; } =20 static const struct clk_ops mtk_mipi_tx_pll_ops =3D { .prepare =3D mtk_mipi_tx_pll_prepare, .unprepare =3D mtk_mipi_tx_pll_unprepare, - .round_rate =3D mtk_mipi_tx_pll_round_rate, + .determine_rate =3D mtk_mipi_tx_pll_determine_rate, .set_rate =3D mtk_mipi_tx_pll_set_rate, .recalc_rate =3D mtk_mipi_tx_pll_recalc_rate, }; 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Signed-off-by: Brian Masney --- drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8183.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8183.c b/drivers/phy/m= ediatek/phy-mtk-mipi-dsi-mt8183.c index 553725e1269c9d7ad88f89367dfa1cf367aaf1ce..a54d44ef70ab49937d210f04fdf= 42300e8e5f2de 100644 --- a/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8183.c +++ b/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8183.c @@ -97,16 +97,18 @@ static void mtk_mipi_tx_pll_disable(struct clk_hw *hw) mtk_phy_clear_bits(base + MIPITX_PLL_PWR, AD_DSI_PLL_SDM_PWR_ON); } =20 -static long mtk_mipi_tx_pll_round_rate(struct clk_hw *hw, unsigned long ra= te, - unsigned long *prate) +static int mtk_mipi_tx_pll_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { - return clamp_val(rate, 125000000, 1600000000); + req->rate =3D clamp_val(req->rate, 125000000, 1600000000); + + return 0; } =20 static const struct clk_ops mtk_mipi_tx_pll_ops =3D { .enable =3D mtk_mipi_tx_pll_enable, .disable =3D mtk_mipi_tx_pll_disable, - .round_rate =3D mtk_mipi_tx_pll_round_rate, + .determine_rate =3D mtk_mipi_tx_pll_determine_rate, .set_rate =3D mtk_mipi_tx_pll_set_rate, .recalc_rate =3D mtk_mipi_tx_pll_recalc_rate, }; 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[73.183.52.120]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-70497d39749sm9670216d6.58.2025.07.10.09.08.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Jul 2025 09:08:24 -0700 (PDT) From: Brian Masney Date: Thu, 10 Jul 2025 12:07:17 -0400 Subject: [PATCH 7/9] phy: rockchip: phy-rockchip-inno-hdmi: convert from round_rate() to determine_rate() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250710-phy-clk-round-rate-v1-7-0ff274055e42@redhat.com> References: <20250710-phy-clk-round-rate-v1-0-0ff274055e42@redhat.com> In-Reply-To: <20250710-phy-clk-round-rate-v1-0-0ff274055e42@redhat.com> To: Vinod Koul , Kishon Vijay Abraham I , Chun-Kuang Hu , Philipp Zabel , Chunfeng Yun , Matthias Brugger , AngeloGioacchino Del Regno , Heiko Stuebner , Maxime Ripard , Stephen Boyd Cc: linux-clk@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, Brian Masney X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1752163685; l=3209; i=bmasney@redhat.com; s=20250528; h=from:subject:message-id; bh=NHf2WrVpFvBK9rcSwwdfI+z+ewWwe162I0ZQpinGzTg=; b=iJFp8tAaWU+wHaHcUB7nA5t7RfDvvhf4kk9dD1nEljg5ScIgHcdVuYZrpCfyQ1GumV9HBW7D3 o5sEUuXM1iaDquqPWph1RO6DawQwo5Fhz2pFk4nTpsSuuAzjb7NEMsz X-Developer-Key: i=bmasney@redhat.com; a=ed25519; pk=x20f2BQYftANnik+wvlm4HqLqAlNs/npfVcbhHPOK2U= The round_rate() clk ops is deprecated, so migrate this driver from round_rate() to determine_rate() using the Coccinelle semantic patch on the cover letter of this series. Signed-off-by: Brian Masney --- drivers/phy/rockchip/phy-rockchip-inno-hdmi.c | 30 ++++++++++++++---------= ---- 1 file changed, 16 insertions(+), 14 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c b/drivers/phy/ro= ckchip/phy-rockchip-inno-hdmi.c index 8dcc2bb777b5455d21a10f06c5ad842b2ddbc834..1483907413faa5ce1dc8614db05= e6e929410404d 100644 --- a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c +++ b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c @@ -749,22 +749,23 @@ unsigned long inno_hdmi_phy_rk3228_clk_recalc_rate(st= ruct clk_hw *hw, return vco; } =20 -static long inno_hdmi_phy_rk3228_clk_round_rate(struct clk_hw *hw, - unsigned long rate, - unsigned long *parent_rate) +static int inno_hdmi_phy_rk3228_clk_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { const struct pre_pll_config *cfg =3D pre_pll_cfg_table; =20 - rate =3D (rate / 1000) * 1000; + req->rate =3D (req->rate / 1000) * 1000; =20 for (; cfg->pixclock !=3D 0; cfg++) - if (cfg->pixclock =3D=3D rate && !cfg->fracdiv) + if (cfg->pixclock =3D=3D req->rate && !cfg->fracdiv) break; =20 if (cfg->pixclock =3D=3D 0) return -EINVAL; =20 - return cfg->pixclock; + req->rate =3D cfg->pixclock; + + return 0; } =20 static int inno_hdmi_phy_rk3228_clk_set_rate(struct clk_hw *hw, @@ -835,7 +836,7 @@ static const struct clk_ops inno_hdmi_phy_rk3228_clk_op= s =3D { .unprepare =3D inno_hdmi_phy_rk3228_clk_unprepare, .is_prepared =3D inno_hdmi_phy_rk3228_clk_is_prepared, .recalc_rate =3D inno_hdmi_phy_rk3228_clk_recalc_rate, - .round_rate =3D inno_hdmi_phy_rk3228_clk_round_rate, + .determine_rate =3D inno_hdmi_phy_rk3228_clk_determine_rate, .set_rate =3D inno_hdmi_phy_rk3228_clk_set_rate, }; =20 @@ -906,22 +907,23 @@ unsigned long inno_hdmi_phy_rk3328_clk_recalc_rate(st= ruct clk_hw *hw, return inno->pixclock; } =20 -static long inno_hdmi_phy_rk3328_clk_round_rate(struct clk_hw *hw, - unsigned long rate, - unsigned long *parent_rate) +static int inno_hdmi_phy_rk3328_clk_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { const struct pre_pll_config *cfg =3D pre_pll_cfg_table; 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[73.183.52.120]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-70497d39749sm9670216d6.58.2025.07.10.09.08.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Jul 2025 09:08:27 -0700 (PDT) From: Brian Masney Date: Thu, 10 Jul 2025 12:07:18 -0400 Subject: [PATCH 8/9] phy: rockchip: phy-rockchip-samsung-hdptx: convert from round_rate() to determine_rate() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250710-phy-clk-round-rate-v1-8-0ff274055e42@redhat.com> References: <20250710-phy-clk-round-rate-v1-0-0ff274055e42@redhat.com> In-Reply-To: <20250710-phy-clk-round-rate-v1-0-0ff274055e42@redhat.com> To: Vinod Koul , Kishon Vijay Abraham I , Chun-Kuang Hu , Philipp Zabel , Chunfeng Yun , Matthias Brugger , AngeloGioacchino Del Regno , Heiko Stuebner , Maxime Ripard , Stephen Boyd Cc: linux-clk@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, Brian Masney X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1752163685; l=2561; i=bmasney@redhat.com; s=20250528; h=from:subject:message-id; bh=tFpHMfoqDqhzNTaVv7v0N0qvUtE+54itjjhNS/n95Lc=; b=e7X3yn2YeXeKXrOkS5F+e0IypwltHuyXsyzMnUIUuprHWBg0Yjbm20ihxHiKGf27VyMww7dN8 zNFlSuHfbztAbMvbZ4Tm4rj9g4qefWj2ql3S7qfHwrgGweB+1fYDH7N X-Developer-Key: i=bmasney@redhat.com; a=ed25519; pk=x20f2BQYftANnik+wvlm4HqLqAlNs/npfVcbhHPOK2U= The round_rate() clk ops is deprecated, so migrate this driver from round_rate() to determine_rate() using the Coccinelle semantic patch on the cover letter of this series. Signed-off-by: Brian Masney --- drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 21 +++++++++++++------= -- 1 file changed, 13 insertions(+), 8 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/ph= y/rockchip/phy-rockchip-samsung-hdptx.c index 79db57ee90d1487b51f4ddadde870a275dd7b17b..f027d2caa4c2ebfc0fdec08bceb= f3f415ff1a064 100644 --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c @@ -1869,8 +1869,8 @@ static unsigned long rk_hdptx_phy_clk_recalc_rate(str= uct clk_hw *hw, return hdptx->hw_rate; } =20 -static long rk_hdptx_phy_clk_round_rate(struct clk_hw *hw, unsigned long r= ate, - unsigned long *parent_rate) +static int rk_hdptx_phy_clk_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { struct rk_hdptx_phy *hdptx =3D to_rk_hdptx_phy(hw); =20 @@ -1879,14 +1879,17 @@ static long rk_hdptx_phy_clk_round_rate(struct clk_= hw *hw, unsigned long rate, * To be dropped as soon as the RK DW HDMI QP bridge driver * switches to make use of phy_configure(). */ - if (!hdptx->restrict_rate_change && rate !=3D hdptx->hdmi_cfg.tmds_char_r= ate) { + if (!hdptx->restrict_rate_change && req->rate !=3D hdptx->hdmi_cfg.tmds_c= har_rate) { struct phy_configure_opts_hdmi hdmi =3D { - .tmds_char_rate =3D rate, + .tmds_char_rate =3D req->rate, }; int ret =3D rk_hdptx_phy_verify_hdmi_config(hdptx, &hdmi); =20 - if (ret) - return ret; + if (ret) { + req->rate =3D ret; + + return 0; + } =20 hdptx->hdmi_cfg =3D hdmi; } @@ -1896,7 +1899,9 @@ static long rk_hdptx_phy_clk_round_rate(struct clk_hw= *hw, unsigned long rate, * hence ensure rk_hdptx_phy_clk_set_rate() won't be invoked with * a different rate argument. */ - return hdptx->hdmi_cfg.tmds_char_rate; + req->rate =3D hdptx->hdmi_cfg.tmds_char_rate; + + return 0; } =20 static int rk_hdptx_phy_clk_set_rate(struct clk_hw *hw, unsigned long rate, @@ -1925,7 +1930,7 @@ static const struct clk_ops hdptx_phy_clk_ops =3D { .prepare =3D rk_hdptx_phy_clk_prepare, .unprepare =3D rk_hdptx_phy_clk_unprepare, .recalc_rate =3D rk_hdptx_phy_clk_recalc_rate, - .round_rate =3D rk_hdptx_phy_clk_round_rate, + .determine_rate =3D rk_hdptx_phy_clk_determine_rate, .set_rate =3D rk_hdptx_phy_clk_set_rate, }; =20 --=20 2.50.0 From nobody Tue Oct 7 09:57:02 2025 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2C2DF2F0E30 for ; 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[73.183.52.120]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-70497d39749sm9670216d6.58.2025.07.10.09.08.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Jul 2025 09:08:29 -0700 (PDT) From: Brian Masney Date: Thu, 10 Jul 2025 12:07:19 -0400 Subject: [PATCH 9/9] phy: ti: phy-j721e-wiz: convert from round_rate() to determine_rate() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250710-phy-clk-round-rate-v1-9-0ff274055e42@redhat.com> References: <20250710-phy-clk-round-rate-v1-0-0ff274055e42@redhat.com> In-Reply-To: <20250710-phy-clk-round-rate-v1-0-0ff274055e42@redhat.com> To: Vinod Koul , Kishon Vijay Abraham I , Chun-Kuang Hu , Philipp Zabel , Chunfeng Yun , Matthias Brugger , AngeloGioacchino Del Regno , Heiko Stuebner , Maxime Ripard , Stephen Boyd Cc: linux-clk@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, Brian Masney X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1752163685; l=1629; i=bmasney@redhat.com; s=20250528; h=from:subject:message-id; bh=pMJI6s5tTYu1BzJU7vvw5Y0iwaNTd3NH6yMHjsN8/cM=; b=0nPrE2c6cl5ohekNJUp1MPpsItdutqAcWnGrmBosgKM0YvNyBYPz4zo1bZfpAq6S3ivaSbkgi TWd7oICIP84Cvj784x11Hev/+JYsi8/Mx0kVOHPtXnwdacpkl9MVEHt X-Developer-Key: i=bmasney@redhat.com; a=ed25519; pk=x20f2BQYftANnik+wvlm4HqLqAlNs/npfVcbhHPOK2U= The round_rate() clk ops is deprecated, so migrate this driver from round_rate() to determine_rate() using the Coccinelle semantic patch on the cover letter of this series. Signed-off-by: Brian Masney --- drivers/phy/ti/phy-j721e-wiz.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c index ab2a4f2c0a5bf3aa4b77045f4da8b0ddcc079f7a..12dafb2bd49bc33c13dd49246bc= 26df082e3dd40 100644 --- a/drivers/phy/ti/phy-j721e-wiz.c +++ b/drivers/phy/ti/phy-j721e-wiz.c @@ -934,12 +934,15 @@ static unsigned long wiz_clk_div_recalc_rate(struct c= lk_hw *hw, return divider_recalc_rate(hw, parent_rate, val, div->table, 0x0, 2); } =20 -static long wiz_clk_div_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *prate) +static int wiz_clk_div_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { struct wiz_clk_divider *div =3D to_wiz_clk_div(hw); =20 - return divider_round_rate(hw, rate, prate, div->table, 2, 0x0); + req->rate =3D divider_round_rate(hw, req->rate, &req->best_parent_rate, + div->table, 2, 0x0); + + return 0; } =20 static int wiz_clk_div_set_rate(struct clk_hw *hw, unsigned long rate, @@ -958,7 +961,7 @@ static int wiz_clk_div_set_rate(struct clk_hw *hw, unsi= gned long rate, =20 static const struct clk_ops wiz_clk_div_ops =3D { .recalc_rate =3D wiz_clk_div_recalc_rate, - .round_rate =3D wiz_clk_div_round_rate, + .determine_rate =3D wiz_clk_div_determine_rate, .set_rate =3D wiz_clk_div_set_rate, }; =20 --=20 2.50.0