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[73.183.52.120]) by smtp.gmail.com with ESMTPSA id af79cd13be357-7dcdc5df99asm113487685a.49.2025.07.10.09.27.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Jul 2025 09:27:52 -0700 (PDT) From: Brian Masney Date: Thu, 10 Jul 2025 12:27:29 -0400 Subject: [PATCH 3/7] drm/msm/dsi_phy_28nm_8960: convert from round_rate() to determine_rate() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250710-drm-msm-phy-clk-round-rate-v1-3-364b1d9ee3f8@redhat.com> References: <20250710-drm-msm-phy-clk-round-rate-v1-0-364b1d9ee3f8@redhat.com> In-Reply-To: <20250710-drm-msm-phy-clk-round-rate-v1-0-364b1d9ee3f8@redhat.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maxime Ripard , Stephen Boyd Cc: linux-clk@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Brian Masney X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1752164864; l=3065; i=bmasney@redhat.com; s=20250528; h=from:subject:message-id; bh=LuIdTqZOB0IRg3CTS/bE+68lhiU63BV6cIYBbNqOn1E=; b=f34Vu5Am3Epc8RhAvgL3lZpMgFt7lkFGSFFJPkt5Aq5xZNEfkcTpI3h6rM13pyuzPIwSSvM1F NgAw7WN4IMXByyDaw/F9whWSiB6hkeMO9L2CsMqwBUVASiJ/wkk3IUg X-Developer-Key: i=bmasney@redhat.com; a=ed25519; pk=x20f2BQYftANnik+wvlm4HqLqAlNs/npfVcbhHPOK2U= The round_rate() clk ops is deprecated, so migrate this driver from round_rate() to determine_rate() using the Coccinelle semantic patch on the cover letter of this series. Signed-off-by: Brian Masney --- drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c | 34 +++++++++++++--------= ---- 1 file changed, 18 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c b/drivers/gpu/= drm/msm/dsi/phy/dsi_phy_28nm_8960.c index f3643320ff2f2bae5301bb94f1fe19fa03db584c..8d234685c1aa3d4579e3dc766c0= 00de1909f87f6 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm_8960.c @@ -231,21 +231,21 @@ static void dsi_pll_28nm_vco_unprepare(struct clk_hw = *hw) pll_28nm->phy->pll_on =3D false; } =20 -static long dsi_pll_28nm_clk_round_rate(struct clk_hw *hw, - unsigned long rate, unsigned long *parent_rate) +static int dsi_pll_28nm_clk_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { struct dsi_pll_28nm *pll_28nm =3D to_pll_28nm(hw); =20 - if (rate < pll_28nm->phy->cfg->min_pll_rate) - return pll_28nm->phy->cfg->min_pll_rate; - else if (rate > pll_28nm->phy->cfg->max_pll_rate) - return pll_28nm->phy->cfg->max_pll_rate; - else - return rate; + if (req->rate < pll_28nm->phy->cfg->min_pll_rate) + req->rate =3D pll_28nm->phy->cfg->min_pll_rate; + else if (req->rate > pll_28nm->phy->cfg->max_pll_rate) + req->rate =3D pll_28nm->phy->cfg->max_pll_rate; + + return 0; } =20 static const struct clk_ops clk_ops_dsi_pll_28nm_vco =3D { - .round_rate =3D dsi_pll_28nm_clk_round_rate, + .determine_rate =3D dsi_pll_28nm_clk_determine_rate, .set_rate =3D dsi_pll_28nm_clk_set_rate, .recalc_rate =3D dsi_pll_28nm_clk_recalc_rate, .prepare =3D dsi_pll_28nm_vco_prepare, @@ -296,18 +296,20 @@ static unsigned int get_vco_mul_factor(unsigned long = byte_clk_rate) return 8; } =20 -static long clk_bytediv_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *prate) +static int clk_bytediv_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { unsigned long best_parent; unsigned int factor; =20 - factor =3D get_vco_mul_factor(rate); + factor =3D get_vco_mul_factor(req->rate); + + best_parent =3D req->rate * factor; + req->best_parent_rate =3D clk_hw_round_rate(clk_hw_get_parent(hw), best_p= arent); =20 - best_parent =3D rate * factor; - *prate =3D clk_hw_round_rate(clk_hw_get_parent(hw), best_parent); + req->rate =3D req->best_parent_rate / factor; =20 - return *prate / factor; + return 0; } =20 static int clk_bytediv_set_rate(struct clk_hw *hw, unsigned long rate, @@ -328,7 +330,7 @@ static int clk_bytediv_set_rate(struct clk_hw *hw, unsi= gned long rate, =20 /* Our special byte clock divider ops */ static const struct clk_ops clk_bytediv_ops =3D { - .round_rate =3D clk_bytediv_round_rate, + .determine_rate =3D clk_bytediv_determine_rate, .set_rate =3D clk_bytediv_set_rate, .recalc_rate =3D clk_bytediv_recalc_rate, }; --=20 2.50.0