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Thu, 10 Jul 2025 14:45:54 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEsgW24lNzV6jS3iGpzMSHW5KHXnsxCI6LXpGqmrnkTpsx3BaTOZsXCDQI+JDSCYr9GcAZDTA== X-Received: by 2002:a05:6808:4fe3:b0:407:77e9:a104 with SMTP id 5614622812f47-4151017fdabmr894442b6e.17.1752183954370; Thu, 10 Jul 2025 14:45:54 -0700 (PDT) Received: from [10.144.155.224] ([2600:382:8102:a87a:c1c4:9ad5:f0c:c0f7]) by smtp.gmail.com with ESMTPSA id 5614622812f47-41419baa00dsm345483b6e.22.2025.07.10.14.45.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Jul 2025 14:45:53 -0700 (PDT) From: Brian Masney Date: Thu, 10 Jul 2025 17:45:16 -0400 Subject: [PATCH 4/6] clk: tegra: pll: convert from round_rate() to determine_rate() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250710-clk-tegra-round-rate-v1-4-e48ac3df4279@redhat.com> References: <20250710-clk-tegra-round-rate-v1-0-e48ac3df4279@redhat.com> In-Reply-To: <20250710-clk-tegra-round-rate-v1-0-e48ac3df4279@redhat.com> To: Peter De Schrijver , Prashant Gaikwad , Michael Turquette , Stephen Boyd , Thierry Reding , Jonathan Hunter , Maxime Ripard Cc: linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, Brian Masney X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1752183937; l=5341; i=bmasney@redhat.com; s=20250528; h=from:subject:message-id; bh=KPpqxrbRKKtVjqm1nuEddEThifN10snLNmWpwUh/Uvs=; b=yzOoQ3uzLNxqoYnFziSeszgFxpPsWTe7tkm4m/HTchEdsPmjZ3XQkmqaNSIzmmbMQ6U1VsYAE f/NUcfe/LUbCUPqAKhArpAtwhdj4Q5kmOsH0mNm09fzJyqbuwWp2H3P X-Developer-Key: i=bmasney@redhat.com; a=ed25519; pk=x20f2BQYftANnik+wvlm4HqLqAlNs/npfVcbhHPOK2U= The round_rate() clk ops is deprecated, so migrate this driver from round_rate() to determine_rate() using the Coccinelle semantic patch on the cover letter of this series. Signed-off-by: Brian Masney --- drivers/clk/tegra/clk-pll.c | 52 +++++++++++++++++++++++++++--------------= ---- 1 file changed, 31 insertions(+), 21 deletions(-) diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c index 100b5d9b7e26e906f71963152ad50bd0a89d14d6..591b9f0c155a033ab46fbb0a1de= 742efed560b5c 100644 --- a/drivers/clk/tegra/clk-pll.c +++ b/drivers/clk/tegra/clk-pll.c @@ -840,8 +840,8 @@ static int clk_pll_set_rate(struct clk_hw *hw, unsigned= long rate, return ret; } =20 -static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *prate) +static int clk_pll_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { struct tegra_clk_pll *pll =3D to_clk_pll(hw); struct tegra_clk_pll_freq_table cfg; @@ -849,15 +849,20 @@ static long clk_pll_round_rate(struct clk_hw *hw, uns= igned long rate, if (pll->params->flags & TEGRA_PLL_FIXED) { /* PLLM/MB are used for memory; we do not change rate */ if (pll->params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) - return clk_hw_get_rate(hw); - return pll->params->fixed_rate; + req->rate =3D clk_hw_get_rate(hw); + else + req->rate =3D pll->params->fixed_rate; + + return 0; } =20 - if (_get_table_rate(hw, &cfg, rate, *prate) && - pll->params->calc_rate(hw, &cfg, rate, *prate)) + if (_get_table_rate(hw, &cfg, req->rate, req->best_parent_rate) && + pll->params->calc_rate(hw, &cfg, req->rate, req->best_parent_rate)) return -EINVAL; =20 - return cfg.output_rate; + req->rate =3D cfg.output_rate; + + return 0; } =20 static unsigned long clk_pll_recalc_rate(struct clk_hw *hw, @@ -1057,7 +1062,7 @@ const struct clk_ops tegra_clk_pll_ops =3D { .enable =3D clk_pll_enable, .disable =3D clk_pll_disable, .recalc_rate =3D clk_pll_recalc_rate, - .round_rate =3D clk_pll_round_rate, + .determine_rate =3D clk_pll_determine_rate, .set_rate =3D clk_pll_set_rate, .restore_context =3D tegra_clk_pll_restore_context, }; @@ -1195,7 +1200,7 @@ static const struct clk_ops tegra_clk_pllu_ops =3D { .enable =3D clk_pllu_enable, .disable =3D clk_pll_disable, .recalc_rate =3D clk_pll_recalc_rate, - .round_rate =3D clk_pll_round_rate, + .determine_rate =3D clk_pll_determine_rate, .set_rate =3D clk_pll_set_rate, }; =20 @@ -1353,15 +1358,15 @@ static int clk_pllxc_set_rate(struct clk_hw *hw, un= signed long rate, return ret; } =20 -static long clk_pll_ramp_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *prate) +static int clk_pll_ramp_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { struct tegra_clk_pll *pll =3D to_clk_pll(hw); struct tegra_clk_pll_freq_table cfg; int ret, p_div; - u64 output_rate =3D *prate; + u64 output_rate =3D req->best_parent_rate; =20 - ret =3D _pll_ramp_calc_pll(hw, &cfg, rate, *prate); + ret =3D _pll_ramp_calc_pll(hw, &cfg, req->rate, req->best_parent_rate); if (ret < 0) return ret; =20 @@ -1375,7 +1380,9 @@ static long clk_pll_ramp_round_rate(struct clk_hw *hw= , unsigned long rate, output_rate *=3D cfg.n; do_div(output_rate, cfg.m * p_div); =20 - return output_rate; + req->rate =3D output_rate; + + return 0; } =20 static void _pllcx_strobe(struct tegra_clk_pll *pll) @@ -1598,12 +1605,15 @@ static unsigned long clk_pllre_recalc_rate(struct c= lk_hw *hw, return rate; } =20 -static long clk_pllre_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *prate) +static int clk_pllre_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { struct tegra_clk_pll *pll =3D to_clk_pll(hw); =20 - return _pllre_calc_rate(pll, NULL, rate, *prate); + req->rate =3D _pllre_calc_rate(pll, NULL, req->rate, + req->best_parent_rate); + + return 0; } =20 static int clk_plle_tegra114_enable(struct clk_hw *hw) @@ -2003,7 +2013,7 @@ static const struct clk_ops tegra_clk_pllxc_ops =3D { .enable =3D clk_pll_enable, .disable =3D clk_pll_disable, .recalc_rate =3D clk_pll_recalc_rate, - .round_rate =3D clk_pll_ramp_round_rate, + .determine_rate =3D clk_pll_ramp_determine_rate, .set_rate =3D clk_pllxc_set_rate, }; =20 @@ -2012,7 +2022,7 @@ static const struct clk_ops tegra_clk_pllc_ops =3D { .enable =3D clk_pllc_enable, .disable =3D clk_pllc_disable, .recalc_rate =3D clk_pll_recalc_rate, - .round_rate =3D clk_pll_ramp_round_rate, + .determine_rate =3D clk_pll_ramp_determine_rate, .set_rate =3D clk_pllc_set_rate, }; =20 @@ -2021,7 +2031,7 @@ static const struct clk_ops tegra_clk_pllre_ops =3D { .enable =3D clk_pll_enable, .disable =3D clk_pll_disable, .recalc_rate =3D clk_pllre_recalc_rate, - .round_rate =3D clk_pllre_round_rate, + .determine_rate =3D clk_pllre_determine_rate, .set_rate =3D clk_pllre_set_rate, }; =20 @@ -2321,7 +2331,7 @@ static const struct clk_ops tegra_clk_pllss_ops =3D { .enable =3D clk_pll_enable, .disable =3D clk_pll_disable, .recalc_rate =3D clk_pll_recalc_rate, - .round_rate =3D clk_pll_ramp_round_rate, + .determine_rate =3D clk_pll_ramp_determine_rate, .set_rate =3D clk_pllxc_set_rate, .restore_context =3D tegra_clk_pll_restore_context, }; --=20 2.50.0