From nobody Tue Dec 16 12:19:57 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9D7452836B1; Thu, 10 Jul 2025 03:36:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752118572; cv=none; b=l1oF6LPNA72/AZC0oSwwG4IEEFb1GZDa5+XTYQ1qMHFR5BbFxS/fM232KILl6tCWkMogZrvdUuBknIEDXCvcioL1L9+dQuE6uMjtgqwHRwH1aoe4x4lwILyjif8Aax8AVzyDLtsJ3MRxYhECfCrWevMyy4q/NdPtHK+zOz2Oqlc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752118572; c=relaxed/simple; bh=DhDpQxyB9hAlsPRlDq22ojI9UDgwt4YE9NLjGn5b+uc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=aaR0ceXFGOvRurvF0ham8HVusBMkXQEIiXXayb8U1K54ngF0cDgX7AGdYdbNIr5vSD8JRC3TcFzAfhrsnFpz/rsr8ANAlu4vmuGRD60Pt5omj2x/cjBG13sT96yDKi878Fpw3CHXPN1NVfkEZN2wXKahuWdgths44rrayk6B1JU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=GgzmRrq1; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="GgzmRrq1" Received: by smtp.kernel.org (Postfix) with ESMTPS id 22F35C4CEFF; Thu, 10 Jul 2025 03:36:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1752118572; bh=DhDpQxyB9hAlsPRlDq22ojI9UDgwt4YE9NLjGn5b+uc=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=GgzmRrq1p5QDT84w/Nl143ifzF7pZnnerLO2sl8+/tiK5eug/y3tDlogf0A1AIX4I +mQ2BUpGkOoCCtMaIRuTVWmonP/Utf/y3zWpo0Rz8fdQlZ+lS/TmTQoEPr2LjOWzQC ZCsY0yeyvpfyeqBgzAKAMSA9xANu883LeDn7Sheph9tFNjRPQ2mS/DuZvmTm03/wJS x3VFfMtjRenzrZr3Go3tVxbMVuqj8HpaQC2Tf3ny00EZEryFs/k7XjemxGyd3FtYwg YjQ8J4LA85o0Hftox9c6m+TTUaXhCe3CgNntlAqx5KvctS59yjvj5aNbEzr8ILv3/c ZDCXBwXcH0Zeg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 14A00C83F09; Thu, 10 Jul 2025 03:36:12 +0000 (UTC) From: jiebing chen via B4 Relay Date: Thu, 10 Jul 2025 11:35:41 +0800 Subject: [PATCH v5 5/6] clk: meson: axg-audio: Add the mclk pad div for s4 chip Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250710-audio_drvier-v5-5-d4155f1e7464@amlogic.com> References: <20250710-audio_drvier-v5-0-d4155f1e7464@amlogic.com> In-Reply-To: <20250710-audio_drvier-v5-0-d4155f1e7464@amlogic.com> To: Jerome Brunet , Liam Girdwood , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jaroslav Kysela , Takashi Iwai , Neil Armstrong , Kevin Hilman , Martin Blumenstingl , Michael Turquette , Stephen Boyd Cc: linux-sound@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, jian.xu@amlogic.com, shuai.li@amlogic.com, zhe.wang@amlogic.com, jiebing chen X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1752118569; l=19175; i=jiebing.chen@amlogic.com; s=20250110; h=from:subject:message-id; bh=5phRet6wDDYLB0TyFNKX7t/bGicx3Y4Z1oX45a4I99Q=; b=13qx1kzwBYQaSt/7T8J7xOnWTSdX0xfZlvPYq9p+x9YlaIWZXN2q/0DxXWo6/7HjS+a27oien EP7+PII6U+tDPcKEX96pzQQknWqgZs08ejCZKzd/prFeZaEyC6JdU1+ X-Developer-Key: i=jiebing.chen@amlogic.com; a=ed25519; pk=6rFvvF45A84pLNRy03hfUHeROxHCnZ+1KAGw/DoqKic= X-Endpoint-Received: by B4 Relay for jiebing.chen@amlogic.com/20250110 with auth_id=316 X-Original-From: jiebing chen Reply-To: jiebing.chen@amlogic.com From: jiebing chen Add MCLK pad divider support and expanded LRCLK/SCLK pad count to five. Signed-off-by: jiebing chen --- drivers/clk/meson/axg-audio.c | 435 ++++++++++++++++++++++++++++++++++++++= +++- drivers/clk/meson/axg-audio.h | 6 + 2 files changed, 439 insertions(+), 2 deletions(-) diff --git a/drivers/clk/meson/axg-audio.c b/drivers/clk/meson/axg-audio.c index 9df627b142f89788966ede0262aaaf39e13f0b49..7dc1f464bd55fa33ca3260002ed= 1b3929061f99b 100644 --- a/drivers/clk/meson/axg-audio.c +++ b/drivers/clk/meson/axg-audio.c @@ -323,6 +323,16 @@ static const struct clk_parent_data lrclk_pad_ctrl_par= ent_data[] =3D { AUD_MUX(_name, _reg, 0x7, _shift, 0, _parents, \ CLK_SET_RATE_NO_REPARENT) =20 +#define AUD_MCLK_PAD_MUX(_name, _reg, _shift) \ + AUD_MUX(_name##_sel, _reg, 0x7, _shift, CLK_MUX_ROUND_CLOSEST, \ + mclk_pad_ctrl_parent_data, 0) +#define AUD_MCLK_PAD_DIV(_name, _reg, _shift) \ + AUD_DIV(_name##_div, _reg, _shift, 8, CLK_DIVIDER_ROUND_CLOSEST, \ + aud_##_name##_sel, CLK_SET_RATE_PARENT) +#define AUD_MCLK_PAD_GATE(_name, _reg, _shift) \ + AUD_GATE(_name, _reg, _shift, aud_##_name##_div, \ + CLK_SET_RATE_PARENT) + /* Common Clocks */ static struct clk_regmap ddr_arb =3D AUD_PCLK_GATE(ddr_arb, AUDIO_CLK_GATE_EN, 0); @@ -826,6 +836,49 @@ static struct clk_regmap sm1_tdm_sclk_pad_1 =3D AUD_TD= M_PAD_CTRL( static struct clk_regmap sm1_tdm_sclk_pad_2 =3D AUD_TDM_PAD_CTRL( tdm_sclk_pad_2, AUDIO_SM1_MST_PAD_CTRL1, 8, sclk_pad_ctrl_parent_data); =20 +static struct clk_regmap s4_tdm_mclk_pad0_sel =3D + AUD_MCLK_PAD_MUX(mclk_pad0, AUDIO_S4_MCLK_PAD_CTRL0, 8); +static struct clk_regmap s4_tdm_mclk_pad1_sel =3D + AUD_MCLK_PAD_MUX(mclk_pad1, AUDIO_S4_MCLK_PAD_CTRL0, 24); +static struct clk_regmap s4_tdm_mclk_pad2_sel =3D + AUD_MCLK_PAD_MUX(mclk_pad2, AUDIO_S4_MCLK_PAD_CTRL1, 8); + +static struct clk_regmap s4_tdm_mclk_pad0_div =3D + AUD_MCLK_PAD_DIV(mclk_pad0, AUDIO_S4_MCLK_PAD_CTRL0, 0); +static struct clk_regmap s4_tdm_mclk_pad1_div =3D + AUD_MCLK_PAD_DIV(mclk_pad1, AUDIO_S4_MCLK_PAD_CTRL0, 16); +static struct clk_regmap s4_tdm_mclk_pad2_div =3D + AUD_MCLK_PAD_DIV(mclk_pad2, AUDIO_S4_MCLK_PAD_CTRL1, 0); + +static struct clk_regmap s4_tdm_mclk_pad_0 =3D + AUD_MCLK_PAD_GATE(mclk_pad0, AUDIO_S4_MCLK_PAD_CTRL0, 15); +static struct clk_regmap s4_tdm_mclk_pad_1 =3D + AUD_MCLK_PAD_GATE(mclk_pad1, AUDIO_S4_MCLK_PAD_CTRL0, 31); +static struct clk_regmap s4_tdm_mclk_pad_2 =3D + AUD_MCLK_PAD_GATE(mclk_pad2, AUDIO_S4_MCLK_PAD_CTRL1, 15); + +static struct clk_regmap s4_tdm_sclk_pad_0 =3D + AUD_TDM_PAD_CTRL(tdm_sclk_pad_0, AUDIO_S4_SCLK_PAD_CTRL0, 0, lrclk_pad_ct= rl_parent_data); +static struct clk_regmap s4_tdm_sclk_pad_1 =3D + AUD_TDM_PAD_CTRL(tdm_sclk_pad_1, AUDIO_S4_SCLK_PAD_CTRL0, 4, lrclk_pad_ct= rl_parent_data); +static struct clk_regmap s4_tdm_sclk_pad_2 =3D + AUD_TDM_PAD_CTRL(tdm_sclk_pad_2, AUDIO_S4_SCLK_PAD_CTRL0, 8, lrclk_pad_ct= rl_parent_data); +static struct clk_regmap s4_tdm_sclk_pad_3 =3D + AUD_TDM_PAD_CTRL(tdm_sclk_pad_3, AUDIO_S4_SCLK_PAD_CTRL0, 16, lrclk_pad_c= trl_parent_data); +static struct clk_regmap s4_tdm_sclk_pad_4 =3D + AUD_TDM_PAD_CTRL(tdm_sclk_pad_4, AUDIO_S4_SCLK_PAD_CTRL0, 20, lrclk_pad_c= trl_parent_data); + +static struct clk_regmap s4_tdm_lrclk_pad_0 =3D + AUD_TDM_PAD_CTRL(tdm_lrclk_pad_0, AUDIO_S4_SCLK_PAD_CTRL1, 0, lrclk_pad_c= trl_parent_data); +static struct clk_regmap s4_tdm_lrclk_pad_1 =3D + AUD_TDM_PAD_CTRL(tdm_lrclk_pad_1, AUDIO_S4_SCLK_PAD_CTRL1, 4, lrclk_pad_c= trl_parent_data); +static struct clk_regmap s4_tdm_lrclk_pad_2 =3D + AUD_TDM_PAD_CTRL(tdm_lrclk_pad_2, AUDIO_S4_SCLK_PAD_CTRL1, 8, lrclk_pad_c= trl_parent_data); +static struct clk_regmap s4_tdm_lrclk_pad_3 =3D + AUD_TDM_PAD_CTRL(tdm_lrclk_pad_3, AUDIO_S4_SCLK_PAD_CTRL1, 16, lrclk_pad_= ctrl_parent_data); +static struct clk_regmap s4_tdm_lrclk_pad_4 =3D + AUD_TDM_PAD_CTRL(tdm_lrclk_pad_4, AUDIO_S4_SCLK_PAD_CTRL1, 20, lrclk_pad_= ctrl_parent_data); + /* * Array of all clocks provided by this provider * The input clocks of the controller will be populated at runtime @@ -1257,6 +1310,182 @@ static struct clk_hw *sm1_audio_hw_clks[] =3D { [AUD_CLKID_EARCRX_DMAC] =3D &sm1_earcrx_dmac_clk.hw, }; =20 +/* + * Array of all S4 clocks provided by this provider + * The input clocks of the controller will be populated at runtime + */ +static struct clk_hw *s4_audio_hw_clks[] =3D { + [AUD_CLKID_DDR_ARB] =3D &ddr_arb.hw, + [AUD_CLKID_PDM] =3D &pdm.hw, + [AUD_CLKID_TDMIN_A] =3D &tdmin_a.hw, + [AUD_CLKID_TDMIN_B] =3D &tdmin_b.hw, + [AUD_CLKID_TDMIN_C] =3D &tdmin_c.hw, + [AUD_CLKID_TDMIN_LB] =3D &tdmin_lb.hw, + [AUD_CLKID_TDMOUT_A] =3D &tdmout_a.hw, + [AUD_CLKID_TDMOUT_B] =3D &tdmout_b.hw, + [AUD_CLKID_TDMOUT_C] =3D &tdmout_c.hw, + [AUD_CLKID_FRDDR_A] =3D &frddr_a.hw, + [AUD_CLKID_FRDDR_B] =3D &frddr_b.hw, + [AUD_CLKID_FRDDR_C] =3D &frddr_c.hw, + [AUD_CLKID_TODDR_A] =3D &toddr_a.hw, + [AUD_CLKID_TODDR_B] =3D &toddr_b.hw, + [AUD_CLKID_TODDR_C] =3D &toddr_c.hw, + [AUD_CLKID_LOOPBACK] =3D &loopback.hw, + [AUD_CLKID_SPDIFIN] =3D &spdifin.hw, + [AUD_CLKID_SPDIFOUT] =3D &spdifout.hw, + [AUD_CLKID_RESAMPLE] =3D &resample.hw, + [AUD_CLKID_SPDIFOUT_B] =3D &spdifout_b.hw, + [AUD_CLKID_MST_A_MCLK_SEL] =3D &sm1_mst_a_mclk_sel.hw, + [AUD_CLKID_MST_B_MCLK_SEL] =3D &sm1_mst_b_mclk_sel.hw, + [AUD_CLKID_MST_C_MCLK_SEL] =3D &sm1_mst_c_mclk_sel.hw, + [AUD_CLKID_MST_D_MCLK_SEL] =3D &sm1_mst_d_mclk_sel.hw, + [AUD_CLKID_MST_E_MCLK_SEL] =3D &sm1_mst_e_mclk_sel.hw, + [AUD_CLKID_MST_F_MCLK_SEL] =3D &sm1_mst_f_mclk_sel.hw, + [AUD_CLKID_MST_A_MCLK_DIV] =3D &sm1_mst_a_mclk_div.hw, + [AUD_CLKID_MST_B_MCLK_DIV] =3D &sm1_mst_b_mclk_div.hw, + [AUD_CLKID_MST_C_MCLK_DIV] =3D &sm1_mst_c_mclk_div.hw, + [AUD_CLKID_MST_D_MCLK_DIV] =3D &sm1_mst_d_mclk_div.hw, + [AUD_CLKID_MST_E_MCLK_DIV] =3D &sm1_mst_e_mclk_div.hw, + [AUD_CLKID_MST_F_MCLK_DIV] =3D &sm1_mst_f_mclk_div.hw, + [AUD_CLKID_MST_A_MCLK] =3D &sm1_mst_a_mclk.hw, + [AUD_CLKID_MST_B_MCLK] =3D &sm1_mst_b_mclk.hw, + [AUD_CLKID_MST_C_MCLK] =3D &sm1_mst_c_mclk.hw, + [AUD_CLKID_MST_D_MCLK] =3D &sm1_mst_d_mclk.hw, + [AUD_CLKID_MST_E_MCLK] =3D &sm1_mst_e_mclk.hw, + [AUD_CLKID_MST_F_MCLK] =3D &sm1_mst_f_mclk.hw, + [AUD_CLKID_SPDIFOUT_CLK_SEL] =3D &spdifout_clk_sel.hw, + [AUD_CLKID_SPDIFOUT_CLK_DIV] =3D &spdifout_clk_div.hw, + [AUD_CLKID_SPDIFOUT_CLK] =3D &spdifout_clk.hw, + [AUD_CLKID_SPDIFOUT_B_CLK_SEL] =3D &spdifout_b_clk_sel.hw, + [AUD_CLKID_SPDIFOUT_B_CLK_DIV] =3D &spdifout_b_clk_div.hw, + [AUD_CLKID_SPDIFOUT_B_CLK] =3D &spdifout_b_clk.hw, + [AUD_CLKID_SPDIFIN_CLK_SEL] =3D &spdifin_clk_sel.hw, + [AUD_CLKID_SPDIFIN_CLK_DIV] =3D &spdifin_clk_div.hw, + [AUD_CLKID_SPDIFIN_CLK] =3D &spdifin_clk.hw, + [AUD_CLKID_PDM_DCLK_SEL] =3D &pdm_dclk_sel.hw, + [AUD_CLKID_PDM_DCLK_DIV] =3D &pdm_dclk_div.hw, + [AUD_CLKID_PDM_DCLK] =3D &pdm_dclk.hw, + [AUD_CLKID_PDM_SYSCLK_SEL] =3D &pdm_sysclk_sel.hw, + [AUD_CLKID_PDM_SYSCLK_DIV] =3D &pdm_sysclk_div.hw, + [AUD_CLKID_PDM_SYSCLK] =3D &pdm_sysclk.hw, + [AUD_CLKID_MST_A_SCLK_PRE_EN] =3D &mst_a_sclk_pre_en.hw, + [AUD_CLKID_MST_B_SCLK_PRE_EN] =3D &mst_b_sclk_pre_en.hw, + [AUD_CLKID_MST_C_SCLK_PRE_EN] =3D &mst_c_sclk_pre_en.hw, + [AUD_CLKID_MST_D_SCLK_PRE_EN] =3D &mst_d_sclk_pre_en.hw, + [AUD_CLKID_MST_E_SCLK_PRE_EN] =3D &mst_e_sclk_pre_en.hw, + [AUD_CLKID_MST_F_SCLK_PRE_EN] =3D &mst_f_sclk_pre_en.hw, + [AUD_CLKID_MST_A_SCLK_DIV] =3D &mst_a_sclk_div.hw, + [AUD_CLKID_MST_B_SCLK_DIV] =3D &mst_b_sclk_div.hw, + [AUD_CLKID_MST_C_SCLK_DIV] =3D &mst_c_sclk_div.hw, + [AUD_CLKID_MST_D_SCLK_DIV] =3D &mst_d_sclk_div.hw, + [AUD_CLKID_MST_E_SCLK_DIV] =3D &mst_e_sclk_div.hw, + [AUD_CLKID_MST_F_SCLK_DIV] =3D &mst_f_sclk_div.hw, + [AUD_CLKID_MST_A_SCLK_POST_EN] =3D &mst_a_sclk_post_en.hw, + [AUD_CLKID_MST_B_SCLK_POST_EN] =3D &mst_b_sclk_post_en.hw, + [AUD_CLKID_MST_C_SCLK_POST_EN] =3D &mst_c_sclk_post_en.hw, + [AUD_CLKID_MST_D_SCLK_POST_EN] =3D &mst_d_sclk_post_en.hw, + [AUD_CLKID_MST_E_SCLK_POST_EN] =3D &mst_e_sclk_post_en.hw, + [AUD_CLKID_MST_F_SCLK_POST_EN] =3D &mst_f_sclk_post_en.hw, + [AUD_CLKID_MST_A_SCLK] =3D &mst_a_sclk.hw, + [AUD_CLKID_MST_B_SCLK] =3D &mst_b_sclk.hw, + [AUD_CLKID_MST_C_SCLK] =3D &mst_c_sclk.hw, + [AUD_CLKID_MST_D_SCLK] =3D &mst_d_sclk.hw, + [AUD_CLKID_MST_E_SCLK] =3D &mst_e_sclk.hw, + [AUD_CLKID_MST_F_SCLK] =3D &mst_f_sclk.hw, + [AUD_CLKID_MST_A_LRCLK_DIV] =3D &mst_a_lrclk_div.hw, + [AUD_CLKID_MST_B_LRCLK_DIV] =3D &mst_b_lrclk_div.hw, + [AUD_CLKID_MST_C_LRCLK_DIV] =3D &mst_c_lrclk_div.hw, + [AUD_CLKID_MST_D_LRCLK_DIV] =3D &mst_d_lrclk_div.hw, + [AUD_CLKID_MST_E_LRCLK_DIV] =3D &mst_e_lrclk_div.hw, + [AUD_CLKID_MST_F_LRCLK_DIV] =3D &mst_f_lrclk_div.hw, + [AUD_CLKID_MST_A_LRCLK] =3D &mst_a_lrclk.hw, + [AUD_CLKID_MST_B_LRCLK] =3D &mst_b_lrclk.hw, + [AUD_CLKID_MST_C_LRCLK] =3D &mst_c_lrclk.hw, + [AUD_CLKID_MST_D_LRCLK] =3D &mst_d_lrclk.hw, + [AUD_CLKID_MST_E_LRCLK] =3D &mst_e_lrclk.hw, + [AUD_CLKID_MST_F_LRCLK] =3D &mst_f_lrclk.hw, + [AUD_CLKID_TDMIN_A_SCLK_SEL] =3D &tdmin_a_sclk_sel.hw, + [AUD_CLKID_TDMIN_B_SCLK_SEL] =3D &tdmin_b_sclk_sel.hw, + [AUD_CLKID_TDMIN_C_SCLK_SEL] =3D &tdmin_c_sclk_sel.hw, + [AUD_CLKID_TDMIN_LB_SCLK_SEL] =3D &tdmin_lb_sclk_sel.hw, + [AUD_CLKID_TDMOUT_A_SCLK_SEL] =3D &tdmout_a_sclk_sel.hw, + [AUD_CLKID_TDMOUT_B_SCLK_SEL] =3D &tdmout_b_sclk_sel.hw, + [AUD_CLKID_TDMOUT_C_SCLK_SEL] =3D &tdmout_c_sclk_sel.hw, + [AUD_CLKID_TDMIN_A_SCLK_PRE_EN] =3D &tdmin_a_sclk_pre_en.hw, + [AUD_CLKID_TDMIN_B_SCLK_PRE_EN] =3D &tdmin_b_sclk_pre_en.hw, + [AUD_CLKID_TDMIN_C_SCLK_PRE_EN] =3D &tdmin_c_sclk_pre_en.hw, + [AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] =3D &tdmin_lb_sclk_pre_en.hw, + [AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] =3D &tdmout_a_sclk_pre_en.hw, + [AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] =3D &tdmout_b_sclk_pre_en.hw, + [AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] =3D &tdmout_c_sclk_pre_en.hw, + [AUD_CLKID_TDMIN_A_SCLK_POST_EN] =3D &tdmin_a_sclk_post_en.hw, + [AUD_CLKID_TDMIN_B_SCLK_POST_EN] =3D &tdmin_b_sclk_post_en.hw, + [AUD_CLKID_TDMIN_C_SCLK_POST_EN] =3D &tdmin_c_sclk_post_en.hw, + [AUD_CLKID_TDMIN_LB_SCLK_POST_EN] =3D &tdmin_lb_sclk_post_en.hw, + [AUD_CLKID_TDMOUT_A_SCLK_POST_EN] =3D &tdmout_a_sclk_post_en.hw, + [AUD_CLKID_TDMOUT_B_SCLK_POST_EN] =3D &tdmout_b_sclk_post_en.hw, + [AUD_CLKID_TDMOUT_C_SCLK_POST_EN] =3D &tdmout_c_sclk_post_en.hw, + [AUD_CLKID_TDMIN_A_SCLK] =3D &tdmin_a_sclk.hw, + [AUD_CLKID_TDMIN_B_SCLK] =3D &tdmin_b_sclk.hw, + [AUD_CLKID_TDMIN_C_SCLK] =3D &tdmin_c_sclk.hw, + [AUD_CLKID_TDMIN_LB_SCLK] =3D &tdmin_lb_sclk.hw, + [AUD_CLKID_TDMOUT_A_SCLK] =3D &g12a_tdmout_a_sclk.hw, + [AUD_CLKID_TDMOUT_B_SCLK] =3D &g12a_tdmout_b_sclk.hw, + [AUD_CLKID_TDMOUT_C_SCLK] =3D &g12a_tdmout_c_sclk.hw, + [AUD_CLKID_TDMIN_A_LRCLK] =3D &tdmin_a_lrclk.hw, + [AUD_CLKID_TDMIN_B_LRCLK] =3D &tdmin_b_lrclk.hw, + [AUD_CLKID_TDMIN_C_LRCLK] =3D &tdmin_c_lrclk.hw, + [AUD_CLKID_TDMIN_LB_LRCLK] =3D &tdmin_lb_lrclk.hw, + [AUD_CLKID_TDMOUT_A_LRCLK] =3D &tdmout_a_lrclk.hw, + [AUD_CLKID_TDMOUT_B_LRCLK] =3D &tdmout_b_lrclk.hw, + [AUD_CLKID_TDMOUT_C_LRCLK] =3D &tdmout_c_lrclk.hw, + [AUD_CLKID_TOP] =3D &sm1_aud_top.hw, + [AUD_CLKID_TORAM] =3D &toram.hw, + [AUD_CLKID_EQDRC] =3D &eqdrc.hw, + [AUD_CLKID_RESAMPLE_B] =3D &resample_b.hw, + [AUD_CLKID_TOVAD] =3D &tovad.hw, + [AUD_CLKID_LOCKER] =3D &locker.hw, + [AUD_CLKID_SPDIFIN_LB] =3D &spdifin_lb.hw, + [AUD_CLKID_FRDDR_D] =3D &frddr_d.hw, + [AUD_CLKID_TODDR_D] =3D &toddr_d.hw, + [AUD_CLKID_LOOPBACK_B] =3D &loopback_b.hw, + [AUD_CLKID_CLK81_EN] =3D &sm1_clk81_en.hw, + [AUD_CLKID_SYSCLK_A_DIV] =3D &sm1_sysclk_a_div.hw, + [AUD_CLKID_SYSCLK_A_EN] =3D &sm1_sysclk_a_en.hw, + [AUD_CLKID_SYSCLK_B_DIV] =3D &sm1_sysclk_b_div.hw, + [AUD_CLKID_SYSCLK_B_EN] =3D &sm1_sysclk_b_en.hw, + [AUD_CLKID_EARCRX] =3D &earcrx.hw, + [AUD_CLKID_EARCRX_CMDC_SEL] =3D &sm1_earcrx_cmdc_clk_sel.hw, + [AUD_CLKID_EARCRX_CMDC_DIV] =3D &sm1_earcrx_cmdc_clk_div.hw, + [AUD_CLKID_EARCRX_CMDC] =3D &sm1_earcrx_cmdc_clk.hw, + [AUD_CLKID_EARCRX_DMAC_SEL] =3D &sm1_earcrx_dmac_clk_sel.hw, + [AUD_CLKID_EARCRX_DMAC_DIV] =3D &sm1_earcrx_dmac_clk_div.hw, + [AUD_CLKID_EARCRX_DMAC] =3D &sm1_earcrx_dmac_clk.hw, + +}; + +static struct clk_hw *audio_clock_pads_hw_clks[] =3D { + [AUD_CLKID_TDM_MCLK_PAD0] =3D &s4_tdm_mclk_pad_0.hw, + [AUD_CLKID_TDM_MCLK_PAD1] =3D &s4_tdm_mclk_pad_1.hw, + [AUD_CLKID_TDM_LRCLK_PAD0] =3D &s4_tdm_lrclk_pad_0.hw, + [AUD_CLKID_TDM_LRCLK_PAD1] =3D &s4_tdm_lrclk_pad_1.hw, + [AUD_CLKID_TDM_LRCLK_PAD2] =3D &s4_tdm_lrclk_pad_2.hw, + [AUD_CLKID_TDM_SCLK_PAD0] =3D &s4_tdm_sclk_pad_0.hw, + [AUD_CLKID_TDM_SCLK_PAD1] =3D &s4_tdm_sclk_pad_1.hw, + [AUD_CLKID_TDM_SCLK_PAD2] =3D &s4_tdm_sclk_pad_2.hw, + [AUD_CLKID_TDM_MCLK_PAD0_SEL] =3D &s4_tdm_mclk_pad0_sel.hw, + [AUD_CLKID_TDM_MCLK_PAD1_SEL] =3D &s4_tdm_mclk_pad1_sel.hw, + [AUD_CLKID_TDM_MCLK_PAD0_DIV] =3D &s4_tdm_mclk_pad0_div.hw, + [AUD_CLKID_TDM_MCLK_PAD1_DIV] =3D &s4_tdm_mclk_pad1_div.hw, + [AUD_CLKID_TDM_MCLK_PAD2] =3D &s4_tdm_mclk_pad_2.hw, + [AUD_CLKID_TDM_MCLK_PAD2_SEL] =3D &s4_tdm_mclk_pad2_sel.hw, + [AUD_CLKID_TDM_MCLK_PAD2_DIV] =3D &s4_tdm_mclk_pad2_div.hw, + [AUD_CLKID_TDM_SCLK_PAD3] =3D &s4_tdm_sclk_pad_3.hw, + [AUD_CLKID_TDM_SCLK_PAD4] =3D &s4_tdm_sclk_pad_4.hw, + [AUD_CLKID_TDM_LRCLK_PAD3] =3D &s4_tdm_lrclk_pad_3.hw, + [AUD_CLKID_TDM_LRCLK_PAD4] =3D &s4_tdm_lrclk_pad_4.hw, + +}; =20 /* Convenience table to populate regmap in .probe(). */ static struct clk_regmap *const axg_clk_regmaps[] =3D { @@ -1678,6 +1907,177 @@ static struct clk_regmap *const sm1_clk_regmaps[] = =3D { &sm1_earcrx_dmac_clk, }; =20 +static struct clk_regmap *const s4_clk_regmaps[] =3D { + &ddr_arb, + &pdm, + &tdmin_a, + &tdmin_b, + &tdmin_c, + &tdmin_lb, + &tdmout_a, + &tdmout_b, + &tdmout_c, + &frddr_a, + &frddr_b, + &frddr_c, + &toddr_a, + &toddr_b, + &toddr_c, + &loopback, + &spdifin, + &spdifout, + &resample, + &spdifout_b, + &sm1_mst_a_mclk_sel, + &sm1_mst_b_mclk_sel, + &sm1_mst_c_mclk_sel, + &sm1_mst_d_mclk_sel, + &sm1_mst_e_mclk_sel, + &sm1_mst_f_mclk_sel, + &sm1_mst_a_mclk_div, + &sm1_mst_b_mclk_div, + &sm1_mst_c_mclk_div, + &sm1_mst_d_mclk_div, + &sm1_mst_e_mclk_div, + &sm1_mst_f_mclk_div, + &sm1_mst_a_mclk, + &sm1_mst_b_mclk, + &sm1_mst_c_mclk, + &sm1_mst_d_mclk, + &sm1_mst_e_mclk, + &sm1_mst_f_mclk, + &spdifout_clk_sel, + &spdifout_clk_div, + &spdifout_clk, + &spdifin_clk_sel, + &spdifin_clk_div, + &spdifin_clk, + &pdm_dclk_sel, + &pdm_dclk_div, + &pdm_dclk, + &pdm_sysclk_sel, + &pdm_sysclk_div, + &pdm_sysclk, + &mst_a_sclk_pre_en, + &mst_b_sclk_pre_en, + &mst_c_sclk_pre_en, + &mst_d_sclk_pre_en, + &mst_e_sclk_pre_en, + &mst_f_sclk_pre_en, + &mst_a_sclk_div, + &mst_b_sclk_div, + &mst_c_sclk_div, + &mst_d_sclk_div, + &mst_e_sclk_div, + &mst_f_sclk_div, + &mst_a_sclk_post_en, + &mst_b_sclk_post_en, + &mst_c_sclk_post_en, + &mst_d_sclk_post_en, + &mst_e_sclk_post_en, + &mst_f_sclk_post_en, + &mst_a_sclk, + &mst_b_sclk, + &mst_c_sclk, + &mst_d_sclk, + &mst_e_sclk, + &mst_f_sclk, + &mst_a_lrclk_div, + &mst_b_lrclk_div, + &mst_c_lrclk_div, + &mst_d_lrclk_div, + &mst_e_lrclk_div, + &mst_f_lrclk_div, + &mst_a_lrclk, + &mst_b_lrclk, + &mst_c_lrclk, + &mst_d_lrclk, + &mst_e_lrclk, + &mst_f_lrclk, + &tdmin_a_sclk_sel, + &tdmin_b_sclk_sel, + &tdmin_c_sclk_sel, + &tdmin_lb_sclk_sel, + &tdmout_a_sclk_sel, + &tdmout_b_sclk_sel, + &tdmout_c_sclk_sel, + &tdmin_a_sclk_pre_en, + &tdmin_b_sclk_pre_en, + &tdmin_c_sclk_pre_en, + &tdmin_lb_sclk_pre_en, + &tdmout_a_sclk_pre_en, + &tdmout_b_sclk_pre_en, + &tdmout_c_sclk_pre_en, + &tdmin_a_sclk_post_en, + &tdmin_b_sclk_post_en, + &tdmin_c_sclk_post_en, + &tdmin_lb_sclk_post_en, + &tdmout_a_sclk_post_en, + &tdmout_b_sclk_post_en, + &tdmout_c_sclk_post_en, + &tdmin_a_sclk, + &tdmin_b_sclk, + &tdmin_c_sclk, + &tdmin_lb_sclk, + &g12a_tdmout_a_sclk, + &g12a_tdmout_b_sclk, + &g12a_tdmout_c_sclk, + &tdmin_a_lrclk, + &tdmin_b_lrclk, + &tdmin_c_lrclk, + &tdmin_lb_lrclk, + &tdmout_a_lrclk, + &tdmout_b_lrclk, + &tdmout_c_lrclk, + &spdifout_b_clk_sel, + &spdifout_b_clk_div, + &spdifout_b_clk, + &sm1_aud_top, + &toram, + &eqdrc, + &resample_b, + &tovad, + &locker, + &spdifin_lb, + &frddr_d, + &toddr_d, + &loopback_b, + &sm1_clk81_en, + &sm1_sysclk_a_div, + &sm1_sysclk_a_en, + &sm1_sysclk_b_div, + &sm1_sysclk_b_en, + &earcrx, + &sm1_earcrx_cmdc_clk_sel, + &sm1_earcrx_cmdc_clk_div, + &sm1_earcrx_cmdc_clk, + &sm1_earcrx_dmac_clk_sel, + &sm1_earcrx_dmac_clk_div, + &sm1_earcrx_dmac_clk, +}; + +static struct clk_regmap *const clk_pads_regmaps[] =3D { + &s4_tdm_mclk_pad_0, + &s4_tdm_mclk_pad_1, + &s4_tdm_mclk_pad_2, + &s4_tdm_lrclk_pad_0, + &s4_tdm_lrclk_pad_1, + &s4_tdm_lrclk_pad_2, + &s4_tdm_lrclk_pad_3, + &s4_tdm_lrclk_pad_4, + &s4_tdm_sclk_pad_0, + &s4_tdm_sclk_pad_1, + &s4_tdm_sclk_pad_2, + &s4_tdm_sclk_pad_3, + &s4_tdm_sclk_pad_4, + &s4_tdm_mclk_pad0_sel, + &s4_tdm_mclk_pad1_sel, + &s4_tdm_mclk_pad0_div, + &s4_tdm_mclk_pad1_div, + &s4_tdm_mclk_pad2_sel, + &s4_tdm_mclk_pad2_div, +}; + struct axg_audio_reset_data { struct reset_controller_dev rstc; struct regmap *map; @@ -1802,7 +2202,8 @@ static int axg_audio_clkc_probe(struct platform_devic= e *pdev) if (IS_ERR(clk)) return PTR_ERR(clk); =20 - ret =3D device_reset(dev); + /*some clock control might be no reset*/ + ret =3D device_reset_optional(dev); if (ret) { dev_err_probe(dev, ret, "failed to reset device\n"); return ret; @@ -1886,6 +2287,30 @@ static const struct audioclk_data sm1_audioclk_data = =3D { .max_register =3D AUDIO_EARCRX_DMAC_CLK_CTRL, }; =20 +static const struct audioclk_data s4_audioclk_data =3D { + .regmap_clks =3D s4_clk_regmaps, + .regmap_clk_num =3D ARRAY_SIZE(s4_clk_regmaps), + .hw_clks =3D { + .hws =3D s4_audio_hw_clks, + .num =3D ARRAY_SIZE(s4_audio_hw_clks), + }, + .reset_offset =3D AUDIO_SM1_SW_RESET0, + .reset_num =3D 39, + .max_register =3D AUDIO_EARCRX_DMAC_CLK_CTRL, +}; + +static const struct audioclk_data audioclk_pads_data =3D { + .regmap_clks =3D clk_pads_regmaps, + .regmap_clk_num =3D ARRAY_SIZE(clk_pads_regmaps), + .hw_clks =3D { + .hws =3D audio_clock_pads_hw_clks, + .num =3D ARRAY_SIZE(audio_clock_pads_hw_clks), + }, + .reset_offset =3D AUDIO_SM1_SW_RESET0, + .reset_num =3D 0, + .max_register =3D AUDIO_S4_SCLK_PAD_CTRL1, +}; + static const struct of_device_id clkc_match_table[] =3D { { .compatible =3D "amlogic,axg-audio-clkc", @@ -1896,7 +2321,13 @@ static const struct of_device_id clkc_match_table[] = =3D { }, { .compatible =3D "amlogic,sm1-audio-clkc", .data =3D &sm1_audioclk_data - }, {} + }, { + .compatible =3D "amlogic,s4-audio-clkc", + .data =3D &s4_audioclk_data + }, { + .compatible =3D "amlogic,clock-pads-clkc", + .data =3D &audioclk_pads_data + }, { }, }; MODULE_DEVICE_TABLE(of, clkc_match_table); =20 diff --git a/drivers/clk/meson/axg-audio.h b/drivers/clk/meson/axg-audio.h index 9e7765b630c96a8029140539ffda789b7db5277a..24233c40171034eba86c699db02= 00f07555926af 100644 --- a/drivers/clk/meson/axg-audio.h +++ b/drivers/clk/meson/axg-audio.h @@ -67,4 +67,10 @@ #define AUDIO_EARCRX_CMDC_CLK_CTRL 0x0D0 #define AUDIO_EARCRX_DMAC_CLK_CTRL 0x0D4 =20 +/* s4 clock pads use new reg base */ +#define AUDIO_S4_MCLK_PAD_CTRL0 0x0 +#define AUDIO_S4_MCLK_PAD_CTRL1 0x4 +#define AUDIO_S4_SCLK_PAD_CTRL0 0x8 +#define AUDIO_S4_SCLK_PAD_CTRL1 0xC + #endif /*__AXG_AUDIO_CLKC_H */ --=20 2.43.0