From nobody Tue Dec 16 04:34:13 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4F600748F; Thu, 10 Jul 2025 03:36:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752118572; cv=none; b=B0Z4TDZkDJEAVbqwSCpm7U8PhX/BpAfqrsJXxMhruoPsyDcTgfwwoqPURDePchDub0DL9HSwU+NSt4X9JHPjq4R6Xksf7zp6bpRZxZMc4S2dMdBbqkl7h5RnPgDM/KXqW2fx/Ru0V2ShLGkIc5DuZwVizk5OkVgHFmxR5V+1CME= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752118572; c=relaxed/simple; bh=//XINryxTmCrNyFb/Ct61hIPybf0yNjBvdelFx7bQ14=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=uBJP+5Nnl6/d9Zs9kjrZO+4VvSVCkByxEp9WWw4msQHRO/YgGDUH5QF7eE30A2PWGXl3w2FNCZVyUyLf1nZmB7coio06FFHvpQHY5FXV/gzGq/fIIalI/2TX4+AQf5JQXFy3h2gQyZBh7VxkGg/O2H/K5B1HCwKEF+JXNohwNOM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=kkrnOAxX; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="kkrnOAxX" Received: by smtp.kernel.org (Postfix) with ESMTPS id DB9B4C4CEF5; Thu, 10 Jul 2025 03:36:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1752118571; bh=//XINryxTmCrNyFb/Ct61hIPybf0yNjBvdelFx7bQ14=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=kkrnOAxXTMSlLFNg6v0c+xTV5qRyIWAEA9MGwPRXxA7ryjseHdNkQ00odvaGGcJoV /oXAYn1FXDUTaLMa3rgqUokmYfVuWCYaoiu4k6jKMIcKLRRJRZge6Z/8Chi1ImrPqI Lw7XcWMHpDZ7W2BpPjXfqMLv/KbcoM488eMPzDF2syhj7A7kp4JK+1bIte+j8b8h8D rsswUExVHhJlAnhQelcqbzoWtq6WvuAjOXaPmydybBLJC8byFze0UKwtw0vlZ+MXd/ PpKUXOCYzLqMIM9XGo2n24fgxqHo0YXT491zH6/8z2Nlzk8s3/i3hB5hmYZclSpnPs d/o1aFdC5jxdw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id CA1D2C83030; Thu, 10 Jul 2025 03:36:11 +0000 (UTC) From: jiebing chen via B4 Relay Date: Thu, 10 Jul 2025 11:35:37 +0800 Subject: [PATCH v5 1/6] dt-bindings: clock: meson: Add audio power domain for s4 soc Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250710-audio_drvier-v5-1-d4155f1e7464@amlogic.com> References: <20250710-audio_drvier-v5-0-d4155f1e7464@amlogic.com> In-Reply-To: <20250710-audio_drvier-v5-0-d4155f1e7464@amlogic.com> To: Jerome Brunet , Liam Girdwood , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jaroslav Kysela , Takashi Iwai , Neil Armstrong , Kevin Hilman , Martin Blumenstingl , Michael Turquette , Stephen Boyd Cc: linux-sound@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, jian.xu@amlogic.com, shuai.li@amlogic.com, zhe.wang@amlogic.com, jiebing chen X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1752118569; l=3341; i=jiebing.chen@amlogic.com; s=20250110; h=from:subject:message-id; bh=yhsDXY7MMuP9ySNiIHj39Bbbf6ifv82AD9aG95a7FPY=; b=HRzZrpgSyMnpl/g7RHqIYGPk+EWvIzv1UFfvZEX3wevTxrCDzEyWmeD2hjyeoTXBQkF3x/u9Z HDXGEqCWaujBJZeKMnPNwhyn0alcJBgFA9a3avMZjC+jNYSXuybdFDI X-Developer-Key: i=jiebing.chen@amlogic.com; a=ed25519; pk=6rFvvF45A84pLNRy03hfUHeROxHCnZ+1KAGw/DoqKic= X-Endpoint-Received: by B4 Relay for jiebing.chen@amlogic.com/20250110 with auth_id=316 X-Original-From: jiebing chen Reply-To: jiebing.chen@amlogic.com From: jiebing chen The audio power domain has been detected on S4 device. It must be enabled prior to audio operations. Signed-off-by: jiebing chen --- .../bindings/clock/amlogic,axg-audio-clkc.yaml | 55 ++++++++++++++++++= +++- 1 file changed, 54 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc= .yaml b/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.yaml index fd7982dd4ceab82389167079c2258a9acff51a76..c3f0bb9b2ff050394828ba339a7= be0c9c48e9a76 100644 --- a/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.yaml +++ b/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.yaml @@ -21,6 +21,8 @@ properties: - amlogic,axg-audio-clkc - amlogic,g12a-audio-clkc - amlogic,sm1-audio-clkc + - amlogic,s4-audio-clkc + - amlogic,clock-pads-clkc =20 '#clock-cells': const: 1 @@ -100,13 +102,15 @@ properties: resets: description: internal reset line =20 + power-domains: + maxItems: 1 + required: - compatible - '#clock-cells' - reg - clocks - clock-names - - resets =20 allOf: - if: @@ -116,12 +120,37 @@ allOf: enum: - amlogic,g12a-audio-clkc - amlogic,sm1-audio-clkc + - amlogic,s4-audio-clkc then: required: - '#reset-cells' else: properties: '#reset-cells': false + - if: + properties: + compatible: + contains: + enum: + - amlogic,s4-audio-clkc + then: + required: + - power-domains + else: + properties: + power-domains: false + - if: + properties: + compatible: + contains: + enum: + - amlogic,clock-pads-clkc + then: + properties: + resets: false + else: + required: + - resets =20 additionalProperties: false =20 @@ -129,6 +158,7 @@ examples: - | #include #include + #include apb { #address-cells =3D <2>; #size-cells =3D <2>; @@ -198,4 +228,27 @@ examples: "slv_lrclk9"; resets =3D <&reset RESET_AUDIO>; }; + clk_pad: clock-controller@330e80 { + compatible =3D "amlogic,clock-pads-clkc"; + reg =3D <0x0 0x330e80 0x0 0x10>; + #clock-cells =3D <1>; + clocks =3D <&clkc_periphs CLKID_AUDIO>, + <&clkc_pll CLKID_MPLL0>, + <&clkc_pll CLKID_MPLL1>, + <&clkc_pll CLKID_MPLL2>, + <&clkc_pll CLKID_MPLL3>, + <&clkc_pll CLKID_HIFI_PLL>, + <&clkc_pll CLKID_FCLK_DIV3>, + <&clkc_pll CLKID_FCLK_DIV4>, + <&clkc_pll CLKID_FCLK_DIV5>; + clock-names =3D "pclk", + "mst_in0", + "mst_in1", + "mst_in2", + "mst_in3", + "mst_in4", + "mst_in5", + "mst_in6", + "mst_in7"; + }; }; --=20 2.43.0 From nobody Tue Dec 16 04:34:13 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4F692236A73; Thu, 10 Jul 2025 03:36:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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a=ed25519; pk=6rFvvF45A84pLNRy03hfUHeROxHCnZ+1KAGw/DoqKic= X-Endpoint-Received: by B4 Relay for jiebing.chen@amlogic.com/20250110 with auth_id=316 X-Original-From: jiebing chen Reply-To: jiebing.chen@amlogic.com From: jiebing chen Add clock ID definitions for the MCLK pads on S4 SoCs. Acked-by: Rob Herring (Arm) Signed-off-by: Jiebing Chen --- include/dt-bindings/clock/axg-audio-clkc.h | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/include/dt-bindings/clock/axg-audio-clkc.h b/include/dt-bindin= gs/clock/axg-audio-clkc.h index 607f23b83fa7287fe0403682ebf827e2df26a1ce..75dde05343d1fa74304ee21c9ec= 0541a8f51b15e 100644 --- a/include/dt-bindings/clock/axg-audio-clkc.h +++ b/include/dt-bindings/clock/axg-audio-clkc.h @@ -162,5 +162,16 @@ #define AUD_CLKID_EARCRX_DMAC_SEL 182 #define AUD_CLKID_EARCRX_DMAC_DIV 183 #define AUD_CLKID_EARCRX_DMAC 184 +#define AUD_CLKID_TDM_MCLK_PAD0_SEL 185 +#define AUD_CLKID_TDM_MCLK_PAD1_SEL 186 +#define AUD_CLKID_TDM_MCLK_PAD0_DIV 187 +#define AUD_CLKID_TDM_MCLK_PAD1_DIV 188 +#define AUD_CLKID_TDM_MCLK_PAD2 189 +#define AUD_CLKID_TDM_MCLK_PAD2_SEL 190 +#define AUD_CLKID_TDM_MCLK_PAD2_DIV 191 +#define AUD_CLKID_TDM_SCLK_PAD3 192 +#define AUD_CLKID_TDM_SCLK_PAD4 193 +#define AUD_CLKID_TDM_LRCLK_PAD3 194 +#define AUD_CLKID_TDM_LRCLK_PAD4 195 =20 #endif /* __AXG_AUDIO_CLKC_BINDINGS_H */ --=20 2.43.0 From nobody Tue Dec 16 04:34:13 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4F634F9D6; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250710-audio_drvier-v5-3-d4155f1e7464@amlogic.com> References: <20250710-audio_drvier-v5-0-d4155f1e7464@amlogic.com> In-Reply-To: <20250710-audio_drvier-v5-0-d4155f1e7464@amlogic.com> To: Jerome Brunet , Liam Girdwood , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jaroslav Kysela , Takashi Iwai , Neil Armstrong , Kevin Hilman , Martin Blumenstingl , Michael Turquette , Stephen Boyd Cc: linux-sound@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, jian.xu@amlogic.com, shuai.li@amlogic.com, zhe.wang@amlogic.com, jiebing chen X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1752118569; l=873; i=jiebing.chen@amlogic.com; s=20250110; h=from:subject:message-id; bh=x6WA+WpOIp5OPvSngtyt9yMnHRZE3lLhDSWKJO4Usbw=; b=8pDuK0vyXUAHxnZ7z6r+YQxBmz4b0lZ/mfWeKQkyV5k1GOC4ZXtfvhBnjtVB12AUjeTjzEuO9 AkCwFAr9iapCq1hjjNtYMbmLOyfFx1oEyxcMurQyj0Sy/tSiJe81BaI X-Developer-Key: i=jiebing.chen@amlogic.com; a=ed25519; pk=6rFvvF45A84pLNRy03hfUHeROxHCnZ+1KAGw/DoqKic= X-Endpoint-Received: by B4 Relay for jiebing.chen@amlogic.com/20250110 with auth_id=316 X-Original-From: jiebing chen Reply-To: jiebing.chen@amlogic.com From: jiebing chen Add S4 SoC tocodec compatibility support. Acked-by: Rob Herring (Arm) Signed-off-by: Jiebing Chen --- Documentation/devicetree/bindings/sound/amlogic,g12a-toacodec.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/sound/amlogic,g12a-toacodec.= yaml b/Documentation/devicetree/bindings/sound/amlogic,g12a-toacodec.yaml index 23f82bb89750898d20c866015bc2e1a4b0554846..ea669f4359bc81b0f45bc2105c8= 32fc2b11d8441 100644 --- a/Documentation/devicetree/bindings/sound/amlogic,g12a-toacodec.yaml +++ b/Documentation/devicetree/bindings/sound/amlogic,g12a-toacodec.yaml @@ -26,6 +26,7 @@ properties: - items: - enum: - amlogic,sm1-toacodec + - amlogic,s4-toacodec - const: amlogic,g12a-toacodec =20 reg: --=20 2.43.0 From nobody Tue Dec 16 04:34:13 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6125F27F759; Thu, 10 Jul 2025 03:36:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752118572; cv=none; b=J2R28xAZF+NRcVDKManOUX9m3FQPgBWu1hOkR59eF0CL5RN3JX22PlQQLv3sGpdSGl1nDZ7luClK/vJSRzNJthg8m9sZ5XJcwWZrXmF8oUz4X+vXEYrZxinMXmH9C+DDWgIzYVni7FSytvFWQ0t8ayChe9mQkgy1QsMzxPbPI98= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752118572; c=relaxed/simple; bh=8w2K7QZ6AF4MXhKAWZ0WsVMksPAeq09KxjKPNZT4T98=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=JjJQqr/HO9AsETetURE7ZggjTnp9PgA831fkJKskPOMWF5+i91NAfHFp92sy+Dtx1YWmn1u96NjD7PyaeMMsd79tKq+IABXaaJgsSewpJ9775KHZ4Qp/a4rlwTJxF42be/m4GfFp38teZ9lnNK99++Tqdbv49xbkjI00B0A6X9Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=TgG742dO; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="TgG742dO" Received: by smtp.kernel.org (Postfix) with ESMTPS id 108AAC4CEFD; Thu, 10 Jul 2025 03:36:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1752118572; bh=8w2K7QZ6AF4MXhKAWZ0WsVMksPAeq09KxjKPNZT4T98=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=TgG742dOsrxHtdgzj+eCd1PkLdIiMQIU1uZfFNXx3IdH3fRqUhqlUj1QDXBJBbTUo rDxAghZLlQ5xIH99QORiSp58A6XjXzFegxbYVknEs+sdzqaNJ34Kii3FJFouQQZszH rech3Yg9w95VGhs0SJu7my1twhE6Bwy/Fy8kA57pjhOSSNqsvn9XwKidorEKDQskpV IXPcKRSAsgvgi8dG4AGYMZJTkHKaHiYPgllP/d7g5qxLSLkJFmJrAYYQ5I40XOHaC7 yaXQMqq+nfTT2UtLZb9HU+ZDoXb/Y90waH1PL4/2EmzJt7NQXOOSGnnxYRa1crU7CN md7HDbD7+9/xg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 01561C83F1B; Thu, 10 Jul 2025 03:36:12 +0000 (UTC) From: jiebing chen via B4 Relay Date: Thu, 10 Jul 2025 11:35:40 +0800 Subject: [PATCH v5 4/6] ASoC: meson: g12a-toacodec: Add s4 tocodec driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250710-audio_drvier-v5-4-d4155f1e7464@amlogic.com> References: <20250710-audio_drvier-v5-0-d4155f1e7464@amlogic.com> In-Reply-To: <20250710-audio_drvier-v5-0-d4155f1e7464@amlogic.com> To: Jerome Brunet , Liam Girdwood , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jaroslav Kysela , Takashi Iwai , Neil Armstrong , Kevin Hilman , Martin Blumenstingl , Michael Turquette , Stephen Boyd Cc: linux-sound@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, jian.xu@amlogic.com, shuai.li@amlogic.com, zhe.wang@amlogic.com, jiebing chen X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1752118569; l=3554; i=jiebing.chen@amlogic.com; s=20250110; h=from:subject:message-id; bh=MLfvyxlbPsF5sk8NMUX7mF1hDMY2Iagf6LVWAbphU3w=; b=Rj3QS2sdPqUT+gPd/INbgcmQ3ZEZc5rhwuKhkgewA2BrN0DIsg/d7ZZONHJx9jHk+w2Lyo0ql baA0fExXo8QBTht5jGhDtGndlBQh31gZ7/2wADrwLL6RlLHpRuUsQf7 X-Developer-Key: i=jiebing.chen@amlogic.com; a=ed25519; pk=6rFvvF45A84pLNRy03hfUHeROxHCnZ+1KAGw/DoqKic= X-Endpoint-Received: by B4 Relay for jiebing.chen@amlogic.com/20250110 with auth_id=316 X-Original-From: jiebing chen Reply-To: jiebing.chen@amlogic.com From: jiebing chen The S4 tocodec supports 8-lane input configuration, requiring BCLK and MCLK control bits to be enabled during operation. Signed-off-by: jiebing chen --- sound/soc/meson/g12a-toacodec.c | 42 +++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 42 insertions(+) diff --git a/sound/soc/meson/g12a-toacodec.c b/sound/soc/meson/g12a-toacode= c.c index 531bb8707a3ec4c47814d6a0676d5c62c705da75..cb2169293f0e800bd9c0893087f= fc4813f3360e2 100644 --- a/sound/soc/meson/g12a-toacodec.c +++ b/sound/soc/meson/g12a-toacodec.c @@ -41,6 +41,9 @@ #define CTRL0_BCLK_SEL_LSB 4 #define CTRL0_MCLK_SEL GENMASK(2, 0) =20 +#define CTRL0_BCLK_ENABLE_SHIFT 30 +#define CTRL0_MCLK_ENABLE_SHIFT 29 + #define TOACODEC_OUT_CHMAX 2 =20 struct g12a_toacodec { @@ -143,6 +146,19 @@ static const struct snd_soc_dapm_widget sm1_toacodec_w= idgets[] =3D { &g12a_toacodec_out_enable), }; =20 +/* + * FIXME: + * On this soc, tocodec need enable mclk and bclk control + * just enable it when dapm power widget power on. + */ + +static const struct snd_soc_dapm_widget s4_toacodec_widgets[] =3D { + SND_SOC_DAPM_MUX("SRC", TOACODEC_CTRL0, CTRL0_BCLK_ENABLE_SHIFT, 0, + &sm1_toacodec_mux), + SND_SOC_DAPM_SWITCH("OUT EN", TOACODEC_CTRL0, CTRL0_MCLK_ENABLE_SHIFT, 0, + &g12a_toacodec_out_enable), +}; + static int g12a_toacodec_input_hw_params(struct snd_pcm_substream *substre= am, struct snd_pcm_hw_params *params, struct snd_soc_dai *dai) @@ -236,6 +252,10 @@ static const struct snd_kcontrol_new sm1_toacodec_cont= rols[] =3D { SOC_SINGLE("Lane Select", TOACODEC_CTRL0, CTRL0_LANE_SEL_SM1, 3, 0), }; =20 +static const struct snd_kcontrol_new s4_toacodec_controls[] =3D { + SOC_SINGLE("Lane Select", TOACODEC_CTRL0, CTRL0_LANE_SEL_SM1, 7, 0), +}; + static const struct snd_soc_component_driver g12a_toacodec_component_drv = =3D { .probe =3D g12a_toacodec_component_probe, .controls =3D g12a_toacodec_controls, @@ -258,6 +278,17 @@ static const struct snd_soc_component_driver sm1_toaco= dec_component_drv =3D { .endianness =3D 1, }; =20 +static const struct snd_soc_component_driver s4_toacodec_component_drv =3D= { + .probe =3D sm1_toacodec_component_probe, + .controls =3D s4_toacodec_controls, + .num_controls =3D ARRAY_SIZE(s4_toacodec_controls), + .dapm_widgets =3D s4_toacodec_widgets, + .num_dapm_widgets =3D ARRAY_SIZE(s4_toacodec_widgets), + .dapm_routes =3D g12a_toacodec_routes, + .num_dapm_routes =3D ARRAY_SIZE(g12a_toacodec_routes), + .endianness =3D 1, +}; + static const struct regmap_config g12a_toacodec_regmap_cfg =3D { .reg_bits =3D 32, .val_bits =3D 32, @@ -278,6 +309,13 @@ static const struct g12a_toacodec_match_data sm1_toaco= dec_match_data =3D { .field_bclk_sel =3D REG_FIELD(TOACODEC_CTRL0, 4, 6), }; =20 +static const struct g12a_toacodec_match_data s4_toacodec_match_data =3D { + .component_drv =3D &s4_toacodec_component_drv, + .field_dat_sel =3D REG_FIELD(TOACODEC_CTRL0, 19, 20), + .field_lrclk_sel =3D REG_FIELD(TOACODEC_CTRL0, 12, 14), + .field_bclk_sel =3D REG_FIELD(TOACODEC_CTRL0, 4, 6), +}; + static const struct of_device_id g12a_toacodec_of_match[] =3D { { .compatible =3D "amlogic,g12a-toacodec", @@ -287,6 +325,10 @@ static const struct of_device_id g12a_toacodec_of_matc= h[] =3D { .compatible =3D "amlogic,sm1-toacodec", .data =3D &sm1_toacodec_match_data, }, + { + .compatible =3D "amlogic,s4-toacodec", + .data =3D &s4_toacodec_match_data, + }, {} }; MODULE_DEVICE_TABLE(of, g12a_toacodec_of_match); --=20 2.43.0 From nobody Tue Dec 16 04:34:13 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9D7452836B1; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250710-audio_drvier-v5-5-d4155f1e7464@amlogic.com> References: <20250710-audio_drvier-v5-0-d4155f1e7464@amlogic.com> In-Reply-To: <20250710-audio_drvier-v5-0-d4155f1e7464@amlogic.com> To: Jerome Brunet , Liam Girdwood , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jaroslav Kysela , Takashi Iwai , Neil Armstrong , Kevin Hilman , Martin Blumenstingl , Michael Turquette , Stephen Boyd Cc: linux-sound@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, jian.xu@amlogic.com, shuai.li@amlogic.com, zhe.wang@amlogic.com, jiebing chen X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1752118569; l=19175; i=jiebing.chen@amlogic.com; s=20250110; h=from:subject:message-id; bh=5phRet6wDDYLB0TyFNKX7t/bGicx3Y4Z1oX45a4I99Q=; b=13qx1kzwBYQaSt/7T8J7xOnWTSdX0xfZlvPYq9p+x9YlaIWZXN2q/0DxXWo6/7HjS+a27oien EP7+PII6U+tDPcKEX96pzQQknWqgZs08ejCZKzd/prFeZaEyC6JdU1+ X-Developer-Key: i=jiebing.chen@amlogic.com; a=ed25519; pk=6rFvvF45A84pLNRy03hfUHeROxHCnZ+1KAGw/DoqKic= X-Endpoint-Received: by B4 Relay for jiebing.chen@amlogic.com/20250110 with auth_id=316 X-Original-From: jiebing chen Reply-To: jiebing.chen@amlogic.com From: jiebing chen Add MCLK pad divider support and expanded LRCLK/SCLK pad count to five. Signed-off-by: jiebing chen --- drivers/clk/meson/axg-audio.c | 435 ++++++++++++++++++++++++++++++++++++++= +++- drivers/clk/meson/axg-audio.h | 6 + 2 files changed, 439 insertions(+), 2 deletions(-) diff --git a/drivers/clk/meson/axg-audio.c b/drivers/clk/meson/axg-audio.c index 9df627b142f89788966ede0262aaaf39e13f0b49..7dc1f464bd55fa33ca3260002ed= 1b3929061f99b 100644 --- a/drivers/clk/meson/axg-audio.c +++ b/drivers/clk/meson/axg-audio.c @@ -323,6 +323,16 @@ static const struct clk_parent_data lrclk_pad_ctrl_par= ent_data[] =3D { AUD_MUX(_name, _reg, 0x7, _shift, 0, _parents, \ CLK_SET_RATE_NO_REPARENT) =20 +#define AUD_MCLK_PAD_MUX(_name, _reg, _shift) \ + AUD_MUX(_name##_sel, _reg, 0x7, _shift, CLK_MUX_ROUND_CLOSEST, \ + mclk_pad_ctrl_parent_data, 0) +#define AUD_MCLK_PAD_DIV(_name, _reg, _shift) \ + AUD_DIV(_name##_div, _reg, _shift, 8, CLK_DIVIDER_ROUND_CLOSEST, \ + aud_##_name##_sel, CLK_SET_RATE_PARENT) +#define AUD_MCLK_PAD_GATE(_name, _reg, _shift) \ + AUD_GATE(_name, _reg, _shift, aud_##_name##_div, \ + CLK_SET_RATE_PARENT) + /* Common Clocks */ static struct clk_regmap ddr_arb =3D AUD_PCLK_GATE(ddr_arb, AUDIO_CLK_GATE_EN, 0); @@ -826,6 +836,49 @@ static struct clk_regmap sm1_tdm_sclk_pad_1 =3D AUD_TD= M_PAD_CTRL( static struct clk_regmap sm1_tdm_sclk_pad_2 =3D AUD_TDM_PAD_CTRL( tdm_sclk_pad_2, AUDIO_SM1_MST_PAD_CTRL1, 8, sclk_pad_ctrl_parent_data); =20 +static struct clk_regmap s4_tdm_mclk_pad0_sel =3D + AUD_MCLK_PAD_MUX(mclk_pad0, AUDIO_S4_MCLK_PAD_CTRL0, 8); +static struct clk_regmap s4_tdm_mclk_pad1_sel =3D + AUD_MCLK_PAD_MUX(mclk_pad1, AUDIO_S4_MCLK_PAD_CTRL0, 24); +static struct clk_regmap s4_tdm_mclk_pad2_sel =3D + AUD_MCLK_PAD_MUX(mclk_pad2, AUDIO_S4_MCLK_PAD_CTRL1, 8); + +static struct clk_regmap s4_tdm_mclk_pad0_div =3D + AUD_MCLK_PAD_DIV(mclk_pad0, AUDIO_S4_MCLK_PAD_CTRL0, 0); +static struct clk_regmap s4_tdm_mclk_pad1_div =3D + AUD_MCLK_PAD_DIV(mclk_pad1, AUDIO_S4_MCLK_PAD_CTRL0, 16); +static struct clk_regmap s4_tdm_mclk_pad2_div =3D + AUD_MCLK_PAD_DIV(mclk_pad2, AUDIO_S4_MCLK_PAD_CTRL1, 0); + +static struct clk_regmap s4_tdm_mclk_pad_0 =3D + AUD_MCLK_PAD_GATE(mclk_pad0, AUDIO_S4_MCLK_PAD_CTRL0, 15); +static struct clk_regmap s4_tdm_mclk_pad_1 =3D + AUD_MCLK_PAD_GATE(mclk_pad1, AUDIO_S4_MCLK_PAD_CTRL0, 31); +static struct clk_regmap s4_tdm_mclk_pad_2 =3D + AUD_MCLK_PAD_GATE(mclk_pad2, AUDIO_S4_MCLK_PAD_CTRL1, 15); + +static struct clk_regmap s4_tdm_sclk_pad_0 =3D + AUD_TDM_PAD_CTRL(tdm_sclk_pad_0, AUDIO_S4_SCLK_PAD_CTRL0, 0, lrclk_pad_ct= rl_parent_data); +static struct clk_regmap s4_tdm_sclk_pad_1 =3D + AUD_TDM_PAD_CTRL(tdm_sclk_pad_1, AUDIO_S4_SCLK_PAD_CTRL0, 4, lrclk_pad_ct= rl_parent_data); +static struct clk_regmap s4_tdm_sclk_pad_2 =3D + AUD_TDM_PAD_CTRL(tdm_sclk_pad_2, AUDIO_S4_SCLK_PAD_CTRL0, 8, lrclk_pad_ct= rl_parent_data); +static struct clk_regmap s4_tdm_sclk_pad_3 =3D + AUD_TDM_PAD_CTRL(tdm_sclk_pad_3, AUDIO_S4_SCLK_PAD_CTRL0, 16, lrclk_pad_c= trl_parent_data); +static struct clk_regmap s4_tdm_sclk_pad_4 =3D + AUD_TDM_PAD_CTRL(tdm_sclk_pad_4, AUDIO_S4_SCLK_PAD_CTRL0, 20, lrclk_pad_c= trl_parent_data); + +static struct clk_regmap s4_tdm_lrclk_pad_0 =3D + AUD_TDM_PAD_CTRL(tdm_lrclk_pad_0, AUDIO_S4_SCLK_PAD_CTRL1, 0, lrclk_pad_c= trl_parent_data); +static struct clk_regmap s4_tdm_lrclk_pad_1 =3D + AUD_TDM_PAD_CTRL(tdm_lrclk_pad_1, AUDIO_S4_SCLK_PAD_CTRL1, 4, lrclk_pad_c= trl_parent_data); +static struct clk_regmap s4_tdm_lrclk_pad_2 =3D + AUD_TDM_PAD_CTRL(tdm_lrclk_pad_2, AUDIO_S4_SCLK_PAD_CTRL1, 8, lrclk_pad_c= trl_parent_data); +static struct clk_regmap s4_tdm_lrclk_pad_3 =3D + AUD_TDM_PAD_CTRL(tdm_lrclk_pad_3, AUDIO_S4_SCLK_PAD_CTRL1, 16, lrclk_pad_= ctrl_parent_data); +static struct clk_regmap s4_tdm_lrclk_pad_4 =3D + AUD_TDM_PAD_CTRL(tdm_lrclk_pad_4, AUDIO_S4_SCLK_PAD_CTRL1, 20, lrclk_pad_= ctrl_parent_data); + /* * Array of all clocks provided by this provider * The input clocks of the controller will be populated at runtime @@ -1257,6 +1310,182 @@ static struct clk_hw *sm1_audio_hw_clks[] =3D { [AUD_CLKID_EARCRX_DMAC] =3D &sm1_earcrx_dmac_clk.hw, }; =20 +/* + * Array of all S4 clocks provided by this provider + * The input clocks of the controller will be populated at runtime + */ +static struct clk_hw *s4_audio_hw_clks[] =3D { + [AUD_CLKID_DDR_ARB] =3D &ddr_arb.hw, + [AUD_CLKID_PDM] =3D &pdm.hw, + [AUD_CLKID_TDMIN_A] =3D &tdmin_a.hw, + [AUD_CLKID_TDMIN_B] =3D &tdmin_b.hw, + [AUD_CLKID_TDMIN_C] =3D &tdmin_c.hw, + [AUD_CLKID_TDMIN_LB] =3D &tdmin_lb.hw, + [AUD_CLKID_TDMOUT_A] =3D &tdmout_a.hw, + [AUD_CLKID_TDMOUT_B] =3D &tdmout_b.hw, + [AUD_CLKID_TDMOUT_C] =3D &tdmout_c.hw, + [AUD_CLKID_FRDDR_A] =3D &frddr_a.hw, + [AUD_CLKID_FRDDR_B] =3D &frddr_b.hw, + [AUD_CLKID_FRDDR_C] =3D &frddr_c.hw, + [AUD_CLKID_TODDR_A] =3D &toddr_a.hw, + [AUD_CLKID_TODDR_B] =3D &toddr_b.hw, + [AUD_CLKID_TODDR_C] =3D &toddr_c.hw, + [AUD_CLKID_LOOPBACK] =3D &loopback.hw, + [AUD_CLKID_SPDIFIN] =3D &spdifin.hw, + [AUD_CLKID_SPDIFOUT] =3D &spdifout.hw, + [AUD_CLKID_RESAMPLE] =3D &resample.hw, + [AUD_CLKID_SPDIFOUT_B] =3D &spdifout_b.hw, + [AUD_CLKID_MST_A_MCLK_SEL] =3D &sm1_mst_a_mclk_sel.hw, + [AUD_CLKID_MST_B_MCLK_SEL] =3D &sm1_mst_b_mclk_sel.hw, + [AUD_CLKID_MST_C_MCLK_SEL] =3D &sm1_mst_c_mclk_sel.hw, + [AUD_CLKID_MST_D_MCLK_SEL] =3D &sm1_mst_d_mclk_sel.hw, + [AUD_CLKID_MST_E_MCLK_SEL] =3D &sm1_mst_e_mclk_sel.hw, + [AUD_CLKID_MST_F_MCLK_SEL] =3D &sm1_mst_f_mclk_sel.hw, + [AUD_CLKID_MST_A_MCLK_DIV] =3D &sm1_mst_a_mclk_div.hw, + [AUD_CLKID_MST_B_MCLK_DIV] =3D &sm1_mst_b_mclk_div.hw, + [AUD_CLKID_MST_C_MCLK_DIV] =3D &sm1_mst_c_mclk_div.hw, + [AUD_CLKID_MST_D_MCLK_DIV] =3D &sm1_mst_d_mclk_div.hw, + [AUD_CLKID_MST_E_MCLK_DIV] =3D &sm1_mst_e_mclk_div.hw, + [AUD_CLKID_MST_F_MCLK_DIV] =3D &sm1_mst_f_mclk_div.hw, + [AUD_CLKID_MST_A_MCLK] =3D &sm1_mst_a_mclk.hw, + [AUD_CLKID_MST_B_MCLK] =3D &sm1_mst_b_mclk.hw, + [AUD_CLKID_MST_C_MCLK] =3D &sm1_mst_c_mclk.hw, + [AUD_CLKID_MST_D_MCLK] =3D &sm1_mst_d_mclk.hw, + [AUD_CLKID_MST_E_MCLK] =3D &sm1_mst_e_mclk.hw, + [AUD_CLKID_MST_F_MCLK] =3D &sm1_mst_f_mclk.hw, + [AUD_CLKID_SPDIFOUT_CLK_SEL] =3D &spdifout_clk_sel.hw, + [AUD_CLKID_SPDIFOUT_CLK_DIV] =3D &spdifout_clk_div.hw, + [AUD_CLKID_SPDIFOUT_CLK] =3D &spdifout_clk.hw, + [AUD_CLKID_SPDIFOUT_B_CLK_SEL] =3D &spdifout_b_clk_sel.hw, + [AUD_CLKID_SPDIFOUT_B_CLK_DIV] =3D &spdifout_b_clk_div.hw, + [AUD_CLKID_SPDIFOUT_B_CLK] =3D &spdifout_b_clk.hw, + [AUD_CLKID_SPDIFIN_CLK_SEL] =3D &spdifin_clk_sel.hw, + [AUD_CLKID_SPDIFIN_CLK_DIV] =3D &spdifin_clk_div.hw, + [AUD_CLKID_SPDIFIN_CLK] =3D &spdifin_clk.hw, + [AUD_CLKID_PDM_DCLK_SEL] =3D &pdm_dclk_sel.hw, + [AUD_CLKID_PDM_DCLK_DIV] =3D &pdm_dclk_div.hw, + [AUD_CLKID_PDM_DCLK] =3D &pdm_dclk.hw, + [AUD_CLKID_PDM_SYSCLK_SEL] =3D &pdm_sysclk_sel.hw, + [AUD_CLKID_PDM_SYSCLK_DIV] =3D &pdm_sysclk_div.hw, + [AUD_CLKID_PDM_SYSCLK] =3D &pdm_sysclk.hw, + [AUD_CLKID_MST_A_SCLK_PRE_EN] =3D &mst_a_sclk_pre_en.hw, + [AUD_CLKID_MST_B_SCLK_PRE_EN] =3D &mst_b_sclk_pre_en.hw, + [AUD_CLKID_MST_C_SCLK_PRE_EN] =3D &mst_c_sclk_pre_en.hw, + [AUD_CLKID_MST_D_SCLK_PRE_EN] =3D &mst_d_sclk_pre_en.hw, + [AUD_CLKID_MST_E_SCLK_PRE_EN] =3D &mst_e_sclk_pre_en.hw, + [AUD_CLKID_MST_F_SCLK_PRE_EN] =3D &mst_f_sclk_pre_en.hw, + [AUD_CLKID_MST_A_SCLK_DIV] =3D &mst_a_sclk_div.hw, + [AUD_CLKID_MST_B_SCLK_DIV] =3D &mst_b_sclk_div.hw, + [AUD_CLKID_MST_C_SCLK_DIV] =3D &mst_c_sclk_div.hw, + [AUD_CLKID_MST_D_SCLK_DIV] =3D &mst_d_sclk_div.hw, + [AUD_CLKID_MST_E_SCLK_DIV] =3D &mst_e_sclk_div.hw, + [AUD_CLKID_MST_F_SCLK_DIV] =3D &mst_f_sclk_div.hw, + [AUD_CLKID_MST_A_SCLK_POST_EN] =3D &mst_a_sclk_post_en.hw, + [AUD_CLKID_MST_B_SCLK_POST_EN] =3D &mst_b_sclk_post_en.hw, + [AUD_CLKID_MST_C_SCLK_POST_EN] =3D &mst_c_sclk_post_en.hw, + [AUD_CLKID_MST_D_SCLK_POST_EN] =3D &mst_d_sclk_post_en.hw, + [AUD_CLKID_MST_E_SCLK_POST_EN] =3D &mst_e_sclk_post_en.hw, + [AUD_CLKID_MST_F_SCLK_POST_EN] =3D &mst_f_sclk_post_en.hw, + [AUD_CLKID_MST_A_SCLK] =3D &mst_a_sclk.hw, + [AUD_CLKID_MST_B_SCLK] =3D &mst_b_sclk.hw, + [AUD_CLKID_MST_C_SCLK] =3D &mst_c_sclk.hw, + [AUD_CLKID_MST_D_SCLK] =3D &mst_d_sclk.hw, + [AUD_CLKID_MST_E_SCLK] =3D &mst_e_sclk.hw, + [AUD_CLKID_MST_F_SCLK] =3D &mst_f_sclk.hw, + [AUD_CLKID_MST_A_LRCLK_DIV] =3D &mst_a_lrclk_div.hw, + [AUD_CLKID_MST_B_LRCLK_DIV] =3D &mst_b_lrclk_div.hw, + [AUD_CLKID_MST_C_LRCLK_DIV] =3D &mst_c_lrclk_div.hw, + [AUD_CLKID_MST_D_LRCLK_DIV] =3D &mst_d_lrclk_div.hw, + [AUD_CLKID_MST_E_LRCLK_DIV] =3D &mst_e_lrclk_div.hw, + [AUD_CLKID_MST_F_LRCLK_DIV] =3D &mst_f_lrclk_div.hw, + [AUD_CLKID_MST_A_LRCLK] =3D &mst_a_lrclk.hw, + [AUD_CLKID_MST_B_LRCLK] =3D &mst_b_lrclk.hw, + [AUD_CLKID_MST_C_LRCLK] =3D &mst_c_lrclk.hw, + [AUD_CLKID_MST_D_LRCLK] =3D &mst_d_lrclk.hw, + [AUD_CLKID_MST_E_LRCLK] =3D &mst_e_lrclk.hw, + [AUD_CLKID_MST_F_LRCLK] =3D &mst_f_lrclk.hw, + [AUD_CLKID_TDMIN_A_SCLK_SEL] =3D &tdmin_a_sclk_sel.hw, + [AUD_CLKID_TDMIN_B_SCLK_SEL] =3D &tdmin_b_sclk_sel.hw, + [AUD_CLKID_TDMIN_C_SCLK_SEL] =3D &tdmin_c_sclk_sel.hw, + [AUD_CLKID_TDMIN_LB_SCLK_SEL] =3D &tdmin_lb_sclk_sel.hw, + [AUD_CLKID_TDMOUT_A_SCLK_SEL] =3D &tdmout_a_sclk_sel.hw, + [AUD_CLKID_TDMOUT_B_SCLK_SEL] =3D &tdmout_b_sclk_sel.hw, + [AUD_CLKID_TDMOUT_C_SCLK_SEL] =3D &tdmout_c_sclk_sel.hw, + [AUD_CLKID_TDMIN_A_SCLK_PRE_EN] =3D &tdmin_a_sclk_pre_en.hw, + [AUD_CLKID_TDMIN_B_SCLK_PRE_EN] =3D &tdmin_b_sclk_pre_en.hw, + [AUD_CLKID_TDMIN_C_SCLK_PRE_EN] =3D &tdmin_c_sclk_pre_en.hw, + [AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] =3D &tdmin_lb_sclk_pre_en.hw, + [AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] =3D &tdmout_a_sclk_pre_en.hw, + [AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] =3D &tdmout_b_sclk_pre_en.hw, + [AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] =3D &tdmout_c_sclk_pre_en.hw, + [AUD_CLKID_TDMIN_A_SCLK_POST_EN] =3D &tdmin_a_sclk_post_en.hw, + [AUD_CLKID_TDMIN_B_SCLK_POST_EN] =3D &tdmin_b_sclk_post_en.hw, + [AUD_CLKID_TDMIN_C_SCLK_POST_EN] =3D &tdmin_c_sclk_post_en.hw, + [AUD_CLKID_TDMIN_LB_SCLK_POST_EN] =3D &tdmin_lb_sclk_post_en.hw, + [AUD_CLKID_TDMOUT_A_SCLK_POST_EN] =3D &tdmout_a_sclk_post_en.hw, + [AUD_CLKID_TDMOUT_B_SCLK_POST_EN] =3D &tdmout_b_sclk_post_en.hw, + [AUD_CLKID_TDMOUT_C_SCLK_POST_EN] =3D &tdmout_c_sclk_post_en.hw, + [AUD_CLKID_TDMIN_A_SCLK] =3D &tdmin_a_sclk.hw, + [AUD_CLKID_TDMIN_B_SCLK] =3D &tdmin_b_sclk.hw, + [AUD_CLKID_TDMIN_C_SCLK] =3D &tdmin_c_sclk.hw, + [AUD_CLKID_TDMIN_LB_SCLK] =3D &tdmin_lb_sclk.hw, + [AUD_CLKID_TDMOUT_A_SCLK] =3D &g12a_tdmout_a_sclk.hw, + [AUD_CLKID_TDMOUT_B_SCLK] =3D &g12a_tdmout_b_sclk.hw, + [AUD_CLKID_TDMOUT_C_SCLK] =3D &g12a_tdmout_c_sclk.hw, + [AUD_CLKID_TDMIN_A_LRCLK] =3D &tdmin_a_lrclk.hw, + [AUD_CLKID_TDMIN_B_LRCLK] =3D &tdmin_b_lrclk.hw, + [AUD_CLKID_TDMIN_C_LRCLK] =3D &tdmin_c_lrclk.hw, + [AUD_CLKID_TDMIN_LB_LRCLK] =3D &tdmin_lb_lrclk.hw, + [AUD_CLKID_TDMOUT_A_LRCLK] =3D &tdmout_a_lrclk.hw, + [AUD_CLKID_TDMOUT_B_LRCLK] =3D &tdmout_b_lrclk.hw, + [AUD_CLKID_TDMOUT_C_LRCLK] =3D &tdmout_c_lrclk.hw, + [AUD_CLKID_TOP] =3D &sm1_aud_top.hw, + [AUD_CLKID_TORAM] =3D &toram.hw, + [AUD_CLKID_EQDRC] =3D &eqdrc.hw, + [AUD_CLKID_RESAMPLE_B] =3D &resample_b.hw, + [AUD_CLKID_TOVAD] =3D &tovad.hw, + [AUD_CLKID_LOCKER] =3D &locker.hw, + [AUD_CLKID_SPDIFIN_LB] =3D &spdifin_lb.hw, + [AUD_CLKID_FRDDR_D] =3D &frddr_d.hw, + [AUD_CLKID_TODDR_D] =3D &toddr_d.hw, + [AUD_CLKID_LOOPBACK_B] =3D &loopback_b.hw, + [AUD_CLKID_CLK81_EN] =3D &sm1_clk81_en.hw, + [AUD_CLKID_SYSCLK_A_DIV] =3D &sm1_sysclk_a_div.hw, + [AUD_CLKID_SYSCLK_A_EN] =3D &sm1_sysclk_a_en.hw, + [AUD_CLKID_SYSCLK_B_DIV] =3D &sm1_sysclk_b_div.hw, + [AUD_CLKID_SYSCLK_B_EN] =3D &sm1_sysclk_b_en.hw, + [AUD_CLKID_EARCRX] =3D &earcrx.hw, + [AUD_CLKID_EARCRX_CMDC_SEL] =3D &sm1_earcrx_cmdc_clk_sel.hw, + [AUD_CLKID_EARCRX_CMDC_DIV] =3D &sm1_earcrx_cmdc_clk_div.hw, + [AUD_CLKID_EARCRX_CMDC] =3D &sm1_earcrx_cmdc_clk.hw, + [AUD_CLKID_EARCRX_DMAC_SEL] =3D &sm1_earcrx_dmac_clk_sel.hw, + [AUD_CLKID_EARCRX_DMAC_DIV] =3D &sm1_earcrx_dmac_clk_div.hw, + [AUD_CLKID_EARCRX_DMAC] =3D &sm1_earcrx_dmac_clk.hw, + +}; + +static struct clk_hw *audio_clock_pads_hw_clks[] =3D { + [AUD_CLKID_TDM_MCLK_PAD0] =3D &s4_tdm_mclk_pad_0.hw, + [AUD_CLKID_TDM_MCLK_PAD1] =3D &s4_tdm_mclk_pad_1.hw, + [AUD_CLKID_TDM_LRCLK_PAD0] =3D &s4_tdm_lrclk_pad_0.hw, + [AUD_CLKID_TDM_LRCLK_PAD1] =3D &s4_tdm_lrclk_pad_1.hw, + [AUD_CLKID_TDM_LRCLK_PAD2] =3D &s4_tdm_lrclk_pad_2.hw, + [AUD_CLKID_TDM_SCLK_PAD0] =3D &s4_tdm_sclk_pad_0.hw, + [AUD_CLKID_TDM_SCLK_PAD1] =3D &s4_tdm_sclk_pad_1.hw, + [AUD_CLKID_TDM_SCLK_PAD2] =3D &s4_tdm_sclk_pad_2.hw, + [AUD_CLKID_TDM_MCLK_PAD0_SEL] =3D &s4_tdm_mclk_pad0_sel.hw, + [AUD_CLKID_TDM_MCLK_PAD1_SEL] =3D &s4_tdm_mclk_pad1_sel.hw, + [AUD_CLKID_TDM_MCLK_PAD0_DIV] =3D &s4_tdm_mclk_pad0_div.hw, + [AUD_CLKID_TDM_MCLK_PAD1_DIV] =3D &s4_tdm_mclk_pad1_div.hw, + [AUD_CLKID_TDM_MCLK_PAD2] =3D &s4_tdm_mclk_pad_2.hw, + [AUD_CLKID_TDM_MCLK_PAD2_SEL] =3D &s4_tdm_mclk_pad2_sel.hw, + [AUD_CLKID_TDM_MCLK_PAD2_DIV] =3D &s4_tdm_mclk_pad2_div.hw, + [AUD_CLKID_TDM_SCLK_PAD3] =3D &s4_tdm_sclk_pad_3.hw, + [AUD_CLKID_TDM_SCLK_PAD4] =3D &s4_tdm_sclk_pad_4.hw, + [AUD_CLKID_TDM_LRCLK_PAD3] =3D &s4_tdm_lrclk_pad_3.hw, + [AUD_CLKID_TDM_LRCLK_PAD4] =3D &s4_tdm_lrclk_pad_4.hw, + +}; =20 /* Convenience table to populate regmap in .probe(). */ static struct clk_regmap *const axg_clk_regmaps[] =3D { @@ -1678,6 +1907,177 @@ static struct clk_regmap *const sm1_clk_regmaps[] = =3D { &sm1_earcrx_dmac_clk, }; =20 +static struct clk_regmap *const s4_clk_regmaps[] =3D { + &ddr_arb, + &pdm, + &tdmin_a, + &tdmin_b, + &tdmin_c, + &tdmin_lb, + &tdmout_a, + &tdmout_b, + &tdmout_c, + &frddr_a, + &frddr_b, + &frddr_c, + &toddr_a, + &toddr_b, + &toddr_c, + &loopback, + &spdifin, + &spdifout, + &resample, + &spdifout_b, + &sm1_mst_a_mclk_sel, + &sm1_mst_b_mclk_sel, + &sm1_mst_c_mclk_sel, + &sm1_mst_d_mclk_sel, + &sm1_mst_e_mclk_sel, + &sm1_mst_f_mclk_sel, + &sm1_mst_a_mclk_div, + &sm1_mst_b_mclk_div, + &sm1_mst_c_mclk_div, + &sm1_mst_d_mclk_div, + &sm1_mst_e_mclk_div, + &sm1_mst_f_mclk_div, + &sm1_mst_a_mclk, + &sm1_mst_b_mclk, + &sm1_mst_c_mclk, + &sm1_mst_d_mclk, + &sm1_mst_e_mclk, + &sm1_mst_f_mclk, + &spdifout_clk_sel, + &spdifout_clk_div, + &spdifout_clk, + &spdifin_clk_sel, + &spdifin_clk_div, + &spdifin_clk, + &pdm_dclk_sel, + &pdm_dclk_div, + &pdm_dclk, + &pdm_sysclk_sel, + &pdm_sysclk_div, + &pdm_sysclk, + &mst_a_sclk_pre_en, + &mst_b_sclk_pre_en, + &mst_c_sclk_pre_en, + &mst_d_sclk_pre_en, + &mst_e_sclk_pre_en, + &mst_f_sclk_pre_en, + &mst_a_sclk_div, + &mst_b_sclk_div, + &mst_c_sclk_div, + &mst_d_sclk_div, + &mst_e_sclk_div, + &mst_f_sclk_div, + &mst_a_sclk_post_en, + &mst_b_sclk_post_en, + &mst_c_sclk_post_en, + &mst_d_sclk_post_en, + &mst_e_sclk_post_en, + &mst_f_sclk_post_en, + &mst_a_sclk, + &mst_b_sclk, + &mst_c_sclk, + &mst_d_sclk, + &mst_e_sclk, + &mst_f_sclk, + &mst_a_lrclk_div, + &mst_b_lrclk_div, + &mst_c_lrclk_div, + &mst_d_lrclk_div, + &mst_e_lrclk_div, + &mst_f_lrclk_div, + &mst_a_lrclk, + &mst_b_lrclk, + &mst_c_lrclk, + &mst_d_lrclk, + &mst_e_lrclk, + &mst_f_lrclk, + &tdmin_a_sclk_sel, + &tdmin_b_sclk_sel, + &tdmin_c_sclk_sel, + &tdmin_lb_sclk_sel, + &tdmout_a_sclk_sel, + &tdmout_b_sclk_sel, + &tdmout_c_sclk_sel, + &tdmin_a_sclk_pre_en, + &tdmin_b_sclk_pre_en, + &tdmin_c_sclk_pre_en, + &tdmin_lb_sclk_pre_en, + &tdmout_a_sclk_pre_en, + &tdmout_b_sclk_pre_en, + &tdmout_c_sclk_pre_en, + &tdmin_a_sclk_post_en, + &tdmin_b_sclk_post_en, + &tdmin_c_sclk_post_en, + &tdmin_lb_sclk_post_en, + &tdmout_a_sclk_post_en, + &tdmout_b_sclk_post_en, + &tdmout_c_sclk_post_en, + &tdmin_a_sclk, + &tdmin_b_sclk, + &tdmin_c_sclk, + &tdmin_lb_sclk, + &g12a_tdmout_a_sclk, + &g12a_tdmout_b_sclk, + &g12a_tdmout_c_sclk, + &tdmin_a_lrclk, + &tdmin_b_lrclk, + &tdmin_c_lrclk, + &tdmin_lb_lrclk, + &tdmout_a_lrclk, + &tdmout_b_lrclk, + &tdmout_c_lrclk, + &spdifout_b_clk_sel, + &spdifout_b_clk_div, + &spdifout_b_clk, + &sm1_aud_top, + &toram, + &eqdrc, + &resample_b, + &tovad, + &locker, + &spdifin_lb, + &frddr_d, + &toddr_d, + &loopback_b, + &sm1_clk81_en, + &sm1_sysclk_a_div, + &sm1_sysclk_a_en, + &sm1_sysclk_b_div, + &sm1_sysclk_b_en, + &earcrx, + &sm1_earcrx_cmdc_clk_sel, + &sm1_earcrx_cmdc_clk_div, + &sm1_earcrx_cmdc_clk, + &sm1_earcrx_dmac_clk_sel, + &sm1_earcrx_dmac_clk_div, + &sm1_earcrx_dmac_clk, +}; + +static struct clk_regmap *const clk_pads_regmaps[] =3D { + &s4_tdm_mclk_pad_0, + &s4_tdm_mclk_pad_1, + &s4_tdm_mclk_pad_2, + &s4_tdm_lrclk_pad_0, + &s4_tdm_lrclk_pad_1, + &s4_tdm_lrclk_pad_2, + &s4_tdm_lrclk_pad_3, + &s4_tdm_lrclk_pad_4, + &s4_tdm_sclk_pad_0, + &s4_tdm_sclk_pad_1, + &s4_tdm_sclk_pad_2, + &s4_tdm_sclk_pad_3, + &s4_tdm_sclk_pad_4, + &s4_tdm_mclk_pad0_sel, + &s4_tdm_mclk_pad1_sel, + &s4_tdm_mclk_pad0_div, + &s4_tdm_mclk_pad1_div, + &s4_tdm_mclk_pad2_sel, + &s4_tdm_mclk_pad2_div, +}; + struct axg_audio_reset_data { struct reset_controller_dev rstc; struct regmap *map; @@ -1802,7 +2202,8 @@ static int axg_audio_clkc_probe(struct platform_devic= e *pdev) if (IS_ERR(clk)) return PTR_ERR(clk); =20 - ret =3D device_reset(dev); + /*some clock control might be no reset*/ + ret =3D device_reset_optional(dev); if (ret) { dev_err_probe(dev, ret, "failed to reset device\n"); return ret; @@ -1886,6 +2287,30 @@ static const struct audioclk_data sm1_audioclk_data = =3D { .max_register =3D AUDIO_EARCRX_DMAC_CLK_CTRL, }; =20 +static const struct audioclk_data s4_audioclk_data =3D { + .regmap_clks =3D s4_clk_regmaps, + .regmap_clk_num =3D ARRAY_SIZE(s4_clk_regmaps), + .hw_clks =3D { + .hws =3D s4_audio_hw_clks, + .num =3D ARRAY_SIZE(s4_audio_hw_clks), + }, + .reset_offset =3D AUDIO_SM1_SW_RESET0, + .reset_num =3D 39, + .max_register =3D AUDIO_EARCRX_DMAC_CLK_CTRL, +}; + +static const struct audioclk_data audioclk_pads_data =3D { + .regmap_clks =3D clk_pads_regmaps, + .regmap_clk_num =3D ARRAY_SIZE(clk_pads_regmaps), + .hw_clks =3D { + .hws =3D audio_clock_pads_hw_clks, + .num =3D ARRAY_SIZE(audio_clock_pads_hw_clks), + }, + .reset_offset =3D AUDIO_SM1_SW_RESET0, + .reset_num =3D 0, + .max_register =3D AUDIO_S4_SCLK_PAD_CTRL1, +}; + static const struct of_device_id clkc_match_table[] =3D { { .compatible =3D "amlogic,axg-audio-clkc", @@ -1896,7 +2321,13 @@ static const struct of_device_id clkc_match_table[] = =3D { }, { .compatible =3D "amlogic,sm1-audio-clkc", .data =3D &sm1_audioclk_data - }, {} + }, { + .compatible =3D "amlogic,s4-audio-clkc", + .data =3D &s4_audioclk_data + }, { + .compatible =3D "amlogic,clock-pads-clkc", + .data =3D &audioclk_pads_data + }, { }, }; MODULE_DEVICE_TABLE(of, clkc_match_table); =20 diff --git a/drivers/clk/meson/axg-audio.h b/drivers/clk/meson/axg-audio.h index 9e7765b630c96a8029140539ffda789b7db5277a..24233c40171034eba86c699db02= 00f07555926af 100644 --- a/drivers/clk/meson/axg-audio.h +++ b/drivers/clk/meson/axg-audio.h @@ -67,4 +67,10 @@ #define AUDIO_EARCRX_CMDC_CLK_CTRL 0x0D0 #define AUDIO_EARCRX_DMAC_CLK_CTRL 0x0D4 =20 +/* s4 clock pads use new reg base */ +#define AUDIO_S4_MCLK_PAD_CTRL0 0x0 +#define AUDIO_S4_MCLK_PAD_CTRL1 0x4 +#define AUDIO_S4_SCLK_PAD_CTRL0 0x8 +#define AUDIO_S4_SCLK_PAD_CTRL1 0xC + #endif /*__AXG_AUDIO_CLKC_H */ --=20 2.43.0 From nobody Tue Dec 16 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hKjxKrVE6JOlxndgFYSNSqKbN4GVgZimd2+fFsCBTO+k5Q4bpsJGEwBx9/HZ3nEWTq HP9meYyr8RQy+KJE8254lp4/jyJ+qewZyLBlHff2xYNcwkCwrNQ0VBMi9OViVH2a89 awvaNyGkBouhwRXYoubO9fNRUf42W8NisoA2s8gQSnY+UhiwvM250qxHu2YqtRdhMh GBRNuk/LkPI9g== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 24328C83F0F; Thu, 10 Jul 2025 03:36:12 +0000 (UTC) From: jiebing chen via B4 Relay Date: Thu, 10 Jul 2025 11:35:42 +0800 Subject: [PATCH v5 6/6] arm64: dts: amlogic: Add Amlogic S4 Audio Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250710-audio_drvier-v5-6-d4155f1e7464@amlogic.com> References: <20250710-audio_drvier-v5-0-d4155f1e7464@amlogic.com> In-Reply-To: <20250710-audio_drvier-v5-0-d4155f1e7464@amlogic.com> To: Jerome Brunet , Liam Girdwood , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jaroslav Kysela , Takashi Iwai , Neil Armstrong , Kevin Hilman , Martin Blumenstingl , Michael Turquette , Stephen Boyd Cc: linux-sound@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, jian.xu@amlogic.com, shuai.li@amlogic.com, zhe.wang@amlogic.com, jiebing chen X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1752118569; l=19932; i=jiebing.chen@amlogic.com; s=20250110; h=from:subject:message-id; bh=cKEhK8ynFZrEBOKpJs4H/3QM4I944r6iZdyIB4LEbXk=; b=C0HPqyGWnGrcwApD3DDRWbX1BYVQyCF+eeaKugdAGp6scCDzc7IbQM0H+XL2DSiyLTI6HH+WQ Ev8Cygq0PWyDnOyFqE7JCFiLzvEiRdnSDwnrK6Tz8RegD225xPOqfoT X-Developer-Key: i=jiebing.chen@amlogic.com; a=ed25519; pk=6rFvvF45A84pLNRy03hfUHeROxHCnZ+1KAGw/DoqKic= X-Endpoint-Received: by B4 Relay for jiebing.chen@amlogic.com/20250110 with auth_id=316 X-Original-From: jiebing chen Reply-To: jiebing.chen@amlogic.com From: jiebing chen Add basic audio driver support for the Amlogic S4 based Amlogic AQ222 board. Signed-off-by: jiebing chen --- .../boot/dts/amlogic/meson-s4-s805x2-aq222.dts | 218 ++++++++++++ arch/arm64/boot/dts/amlogic/meson-s4.dtsi | 387 +++++++++++++++++= ++++ 2 files changed, 605 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-s4-s805x2-aq222.dts b/arch/a= rm64/boot/dts/amlogic/meson-s4-s805x2-aq222.dts index 6730c44642d2910d42ec0c4adf49fefc3514dbec..47c6b8d63fdfca01281f0935f3d= c419af6d86a25 100644 --- a/arch/arm64/boot/dts/amlogic/meson-s4-s805x2-aq222.dts +++ b/arch/arm64/boot/dts/amlogic/meson-s4-s805x2-aq222.dts @@ -75,6 +75,19 @@ vddio_ao1v8: regulator-vddio-ao1v8 { regulator-always-on; }; =20 + vcc5v_reg: regulator-vcc-5v { + compatible =3D "regulator-fixed"; + vin-supply =3D <&main_12v>; + regulator-name =3D "VCC5V"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + gpio =3D <&gpio GPIOH_7 GPIO_ACTIVE_HIGH>; + startup-delay-us =3D <7000>; + enable-active-high; + regulator-boot-on; + regulator-always-on; + }; + /* SY8120B1ABC DC/DC Regulator. */ vddcpu: regulator-vddcpu { compatible =3D "pwm-regulator"; @@ -129,6 +142,211 @@ vddcpu: regulator-vddcpu { <699000 98>, <689000 100>; }; + dmics: audio-codec-1 { + compatible =3D "dmic-codec"; + #sound-dai-cells =3D <0>; + num-channels =3D <2>; + wakeup-delay-ms =3D <50>; + sound-name-prefix =3D "MIC"; + }; + + dioo2133: audio-amplifier-0 { + compatible =3D "simple-audio-amplifier"; + enable-gpios =3D <&gpio GPIOH_8 GPIO_ACTIVE_HIGH>; + VCC-supply =3D <&vcc5v_reg>; + sound-name-prefix =3D "10U2"; + }; + + spdif_dir: audio-spdif-in { + compatible =3D "linux,spdif-dir"; + #sound-dai-cells =3D <0>; + sound-name-prefix =3D "DIR"; + }; + + spdif_dit: audio-spdif-out { + compatible =3D "linux,spdif-dit"; + #sound-dai-cells =3D <0>; + sound-name-prefix =3D "DIT"; + }; + + sound { + compatible =3D "amlogic,axg-sound-card"; + model =3D "aq222"; + audio-widgets =3D "Line", "Lineout"; + audio-aux-devs =3D <&tdmout_a>, <&tdmout_b>, <&tdmout_c>, + <&tdmin_a>, <&tdmin_b>, <&tdmin_c>, + <&tdmin_lb>, <&dioo2133>; + audio-routing =3D "TDMOUT_A IN 0", "FRDDR_A OUT 0", + "TDMOUT_A IN 1", "FRDDR_B OUT 0", + "TDMOUT_A IN 2", "FRDDR_C OUT 0", + "TDM_A Playback", "TDMOUT_A OUT", + "TDMOUT_B IN 0", "FRDDR_A OUT 1", + "TDMOUT_B IN 1", "FRDDR_B OUT 1", + "TDMOUT_B IN 2", "FRDDR_C OUT 1", + "TDM_B Playback", "TDMOUT_B OUT", + "TDMOUT_C IN 0", "FRDDR_A OUT 2", + "TDMOUT_C IN 1", "FRDDR_B OUT 2", + "TDMOUT_C IN 2", "FRDDR_C OUT 2", + "TDM_C Playback", "TDMOUT_C OUT", + "SPDIFOUT_A IN 0", "FRDDR_A OUT 3", + "SPDIFOUT_A IN 1", "FRDDR_B OUT 3", + "SPDIFOUT_A IN 2", "FRDDR_C OUT 3", + "SPDIFOUT_B IN 0", "FRDDR_A OUT 4", + "SPDIFOUT_B IN 1", "FRDDR_B OUT 4", + "SPDIFOUT_B IN 2", "FRDDR_C OUT 4", + "TDMIN_A IN 0", "TDM_A Capture", + "TDMIN_A IN 1", "TDM_B Capture", + "TDMIN_A IN 2", "TDM_C Capture", + "TDMIN_A IN 3", "TDM_A Loopback", + "TDMIN_A IN 4", "TDM_B Loopback", + "TDMIN_A IN 5", "TDM_C Loopback", + "TDMIN_B IN 0", "TDM_A Capture", + "TDMIN_B IN 1", "TDM_B Capture", + "TDMIN_B IN 2", "TDM_C Capture", + "TDMIN_B IN 3", "TDM_A Loopback", + "TDMIN_B IN 4", "TDM_B Loopback", + "TDMIN_B IN 5", "TDM_C Loopback", + "TDMIN_C IN 0", "TDM_A Capture", + "TDMIN_C IN 1", "TDM_B Capture", + "TDMIN_C IN 2", "TDM_C Capture", + "TDMIN_C IN 3", "TDM_A Loopback", + "TDMIN_C IN 4", "TDM_B Loopback", + "TDMIN_C IN 5", "TDM_C Loopback", + "TDMIN_LB IN 3", "TDM_A Capture", + "TDMIN_LB IN 4", "TDM_B Capture", + "TDMIN_LB IN 5", "TDM_C Capture", + "TDMIN_LB IN 0", "TDM_A Loopback", + "TDMIN_LB IN 1", "TDM_B Loopback", + "TDMIN_LB IN 2", "TDM_C Loopback", + "TODDR_A IN 0", "TDMIN_A OUT", + "TODDR_B IN 0", "TDMIN_A OUT", + "TODDR_C IN 0", "TDMIN_A OUT", + "TODDR_A IN 1", "TDMIN_B OUT", + "TODDR_B IN 1", "TDMIN_B OUT", + "TODDR_C IN 1", "TDMIN_B OUT", + "TODDR_A IN 2", "TDMIN_C OUT", + "TODDR_B IN 2", "TDMIN_C OUT", + "TODDR_C IN 2", "TDMIN_C OUT", + "TODDR_A IN 3", "SPDIFIN Capture", + "TODDR_B IN 3", "SPDIFIN Capture", + "TODDR_C IN 3", "SPDIFIN Capture", + "TODDR_A IN 6", "TDMIN_LB OUT", + "TODDR_B IN 6", "TDMIN_LB OUT", + "TODDR_C IN 6", "TDMIN_LB OUT", + "10U2 INL", "ACODEC LOLP", + "10U2 INR", "ACODEC LORP", + "Lineout", "10U2 OUTL", + "Lineout", "10U2 OUTR"; + assigned-clocks =3D <&clkc_pll CLKID_HIFI_PLL>, + <&clkc_pll CLKID_MPLL0>, + <&clkc_pll CLKID_MPLL1>; + assigned-clock-rates =3D <1179648000>, + <270950400>, + <338688000>; + + dai-link-0 { + sound-dai =3D <&frddr_a>; + }; + + dai-link-1 { + sound-dai =3D <&frddr_b>; + }; + + dai-link-2 { + sound-dai =3D <&frddr_c>; + }; + + dai-link-3 { + sound-dai =3D <&toddr_a>; + }; + + dai-link-4 { + sound-dai =3D <&toddr_b>; + }; + + dai-link-5 { + sound-dai =3D <&toddr_c>; + }; + + dai-link-6 { + sound-dai =3D <&tdmif_a>; + dai-format =3D "i2s"; + dai-tdm-slot-tx-mask-0 =3D <1 1>; + mclk-fs =3D <256>; + codec-0 { + sound-dai =3D <&tohdmitx TOHDMITX_I2S_IN_A>; + }; + codec-1 { + sound-dai =3D <&toacodec TOACODEC_IN_A>; + }; + }; + + dai-link-7 { + sound-dai =3D <&tdmif_b>; + dai-format =3D "i2s"; + dai-tdm-slot-tx-mask-0 =3D <1 1>; + mclk-fs =3D <256>; + codec-0 { + sound-dai =3D <&toacodec TOACODEC_IN_B>; + }; + codec-1 { + sound-dai =3D <&tohdmitx TOHDMITX_I2S_IN_B>; + }; + }; + + /* 8ch HDMI interface */ + dai-link-8 { + sound-dai =3D <&tdmif_c>; + dai-format =3D "i2s"; + dai-tdm-slot-tx-mask-0 =3D <1 1>; + dai-tdm-slot-tx-mask-1 =3D <1 1>; + dai-tdm-slot-tx-mask-2 =3D <1 1>; + dai-tdm-slot-tx-mask-3 =3D <1 1>; + mclk-fs =3D <256>; + codec-0 { + sound-dai =3D <&tohdmitx TOHDMITX_I2S_IN_C>; + }; + }; + + /* spdif hdmi and coax output */ + dai-link-9 { + sound-dai =3D <&spdifout_a>; + + codec-0 { + sound-dai =3D <&spdif_dit>; + }; + + codec-1 { + sound-dai =3D <&tohdmitx TOHDMITX_SPDIF_IN_A>; + }; + }; + + /* spdif hdmi interface */ + dai-link-10 { + sound-dai =3D <&spdifout_b>; + + codec { + sound-dai =3D <&tohdmitx TOHDMITX_SPDIF_IN_B>; + }; + }; + + /* spdif coax input */ + dai-link-11 { + sound-dai =3D <&spdifin>; + + codec { + sound-dai =3D <&spdif_dir>; + }; + }; + + dai-link-12 { + sound-dai =3D <&toacodec TOACODEC_OUT>; + + codec { + sound-dai =3D <&acodec>; + }; + }; + }; }; =20 &pwm_ef { diff --git a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi b/arch/arm64/boot/dt= s/amlogic/meson-s4.dtsi index 957577d986c0675a503115e1ccbc4387c2051620..3af2fb333cf7b1ca35f1ff7ad84= 79bcd859e608a 100644 --- a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi @@ -11,6 +11,11 @@ #include #include #include +#include +#include +#include +#include +#include =20 / { cpus { @@ -849,4 +854,386 @@ emmc: mmc@fe08c000 { status =3D "disabled"; }; }; + + tdmif_a: audio-controller-0 { + compatible =3D "amlogic,axg-tdm-iface"; + #sound-dai-cells =3D <0>; + sound-name-prefix =3D "TDM_A"; + clocks =3D <&clkc_audio AUD_CLKID_MST_A_SCLK>, + <&clkc_audio AUD_CLKID_MST_A_LRCLK>, + <&clkc_audio AUD_CLKID_MST_A_MCLK>; + clock-names =3D "sclk", "lrclk","mclk"; + }; + + tdmif_b: audio-controller-1 { + compatible =3D "amlogic,axg-tdm-iface"; + #sound-dai-cells =3D <0>; + sound-name-prefix =3D "TDM_B"; + clocks =3D <&clkc_audio AUD_CLKID_MST_A_SCLK>, + <&clkc_audio AUD_CLKID_MST_B_LRCLK>, + <&clkc_audio AUD_CLKID_MST_B_MCLK>; + clock-names =3D "sclk", "lrclk","mclk"; + }; + + tdmif_c: audio-controller-2 { + compatible =3D "amlogic,axg-tdm-iface"; + #sound-dai-cells =3D <0>; + sound-name-prefix =3D "TDM_C"; + clocks =3D <&clkc_audio AUD_CLKID_MST_C_SCLK>, + <&clkc_audio AUD_CLKID_MST_C_LRCLK>, + <&clkc_audio AUD_CLKID_MST_C_MCLK>; + clock-names =3D "sclk", "lrclk","mclk"; + }; +}; + +&apb4 { + acodec: audio-controller@1a000 { + compatible =3D "amlogic,t9015"; + reg =3D <0x0 0x1A000 0x0 0x14>; + #sound-dai-cells =3D <0>; + sound-name-prefix =3D "ACODEC"; + clocks =3D <&clkc_periphs CLKID_ACODEC>; + clock-names =3D "pclk"; + resets =3D <&reset RESET_ACODEC>; + AVDD-supply =3D <&vddio_ao1v8>; + }; + + clkc_audio: clock-controller@330000 { + compatible =3D "amlogic,s4-audio-clkc"; + reg =3D <0x0 0x330000 0x0 0xd8>, + <0x0 0x330e80 0x0 0x10>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + power-domains =3D <&pwrc PWRC_S4_AUDIO_ID>; + clocks =3D <&clkc_periphs CLKID_AUDIO>, + <&clkc_pll CLKID_MPLL0>, + <&clkc_pll CLKID_MPLL1>, + <&clkc_pll CLKID_MPLL2>, + <&clkc_pll CLKID_MPLL3>, + <&clkc_pll CLKID_HIFI_PLL>, + <&clkc_pll CLKID_FCLK_DIV3>, + <&clkc_pll CLKID_FCLK_DIV4>, + <&clkc_pll CLKID_FCLK_DIV5>; + clock-names =3D "pclk", + "mst_in0", + "mst_in1", + "mst_in2", + "mst_in3", + "mst_in4", + "mst_in5", + "mst_in6", + "mst_in7"; + + resets =3D <&reset RESET_AUDIO>; + }; + + clock-controller@330e80 { + compatible =3D "amlogic,clock-pads-clkc"; + reg =3D <0x0 0x330e80 0x0 0x10>; + #clock-cells =3D <1>; + power-domains =3D <&pwrc PWRC_S4_AUDIO_ID>; + clocks =3D <&clkc_periphs CLKID_AUDIO>, + <&clkc_pll CLKID_MPLL0>, + <&clkc_pll CLKID_MPLL1>, + <&clkc_pll CLKID_MPLL2>, + <&clkc_pll CLKID_MPLL3>, + <&clkc_pll CLKID_HIFI_PLL>, + <&clkc_pll CLKID_FCLK_DIV3>, + <&clkc_pll CLKID_FCLK_DIV4>, + <&clkc_pll CLKID_FCLK_DIV5>; + clock-names =3D "pclk", + "mst_in0", + "mst_in1", + "mst_in2", + "mst_in3", + "mst_in4", + "mst_in5", + "mst_in6", + "mst_in7"; + }; + + toddr_a: audio-controller@330100 { + compatible =3D "amlogic,sm1-toddr", + "amlogic,axg-toddr"; + reg =3D <0x0 0x330100 0x0 0x2c>; + #sound-dai-cells =3D <0>; + sound-name-prefix =3D "TODDR_A"; + interrupts =3D ; + clocks =3D <&clkc_audio AUD_CLKID_TODDR_A>; + resets =3D <&arb AXG_ARB_TODDR_A>, + <&clkc_audio AUD_RESET_TODDR_A>; + reset-names =3D "arb", "rst"; + amlogic,fifo-depth =3D <8192>; + }; + + toddr_b: audio-controller@330140 { + compatible =3D "amlogic,sm1-toddr", + "amlogic,axg-toddr"; + reg =3D <0x0 0x330140 0x0 0x2c>; + #sound-dai-cells =3D <0>; + sound-name-prefix =3D "TODDR_B"; + interrupts =3D ; + clocks =3D <&clkc_audio AUD_CLKID_TODDR_B>; + resets =3D <&arb AXG_ARB_TODDR_B>, + <&clkc_audio AUD_RESET_TODDR_B>; + reset-names =3D "arb", "rst"; + amlogic,fifo-depth =3D <256>; + }; + + toddr_c: audio-controller@330180 { + compatible =3D "amlogic,sm1-toddr", + "amlogic,axg-toddr"; + reg =3D <0x0 0x330180 0x0 0x2c>; + #sound-dai-cells =3D <0>; + sound-name-prefix =3D "TODDR_C"; + interrupts =3D ; + clocks =3D <&clkc_audio AUD_CLKID_TODDR_C>; + resets =3D <&arb AXG_ARB_TODDR_C>, + <&clkc_audio AUD_RESET_TODDR_C>; + reset-names =3D "arb", "rst"; + amlogic,fifo-depth =3D <256>; + }; + + frddr_a: audio-controller@3301c0 { + compatible =3D "amlogic,sm1-frddr", + "amlogic,axg-frddr"; + reg =3D <0x0 0x3301c0 0x0 0x2c>; + #sound-dai-cells =3D <0>; + sound-name-prefix =3D "FRDDR_A"; + interrupts =3D ; + clocks =3D <&clkc_audio AUD_CLKID_FRDDR_A>; + resets =3D <&arb AXG_ARB_FRDDR_A>, + <&clkc_audio AUD_RESET_FRDDR_A>; + reset-names =3D "arb", "rst"; + amlogic,fifo-depth =3D <512>; + }; + + frddr_b: audio-controller@330200 { + compatible =3D "amlogic,sm1-frddr", + "amlogic,axg-frddr"; + reg =3D <0x0 0x330200 0x0 0x2c>; + #sound-dai-cells =3D <0>; + sound-name-prefix =3D "FRDDR_B"; + interrupts =3D ; + clocks =3D <&clkc_audio AUD_CLKID_FRDDR_B>; + resets =3D <&arb AXG_ARB_FRDDR_B>, + <&clkc_audio AUD_RESET_FRDDR_B>; + reset-names =3D "arb", "rst"; + amlogic,fifo-depth =3D <256>; + }; + + frddr_c: audio-controller@330240 { + compatible =3D "amlogic,sm1-frddr", + "amlogic,axg-frddr"; + reg =3D <0x0 0x330240 0x0 0x2c>; + #sound-dai-cells =3D <0>; + sound-name-prefix =3D "FRDDR_C"; + interrupts =3D ; + clocks =3D <&clkc_audio AUD_CLKID_FRDDR_C>; + resets =3D <&arb AXG_ARB_FRDDR_C>, + <&clkc_audio AUD_RESET_FRDDR_C>; + reset-names =3D "arb", "rst"; + amlogic,fifo-depth =3D <256>; + }; + + arb: reset-controller@330280 { + compatible =3D "amlogic,meson-sm1-audio-arb"; + reg =3D <0x0 0x330280 0x0 0x4>; + #reset-cells =3D <1>; + clocks =3D <&clkc_audio AUD_CLKID_DDR_ARB>; + }; + + tdmin_a: audio-controller@330300 { + compatible =3D "amlogic,sm1-tdmin"; + reg =3D <0x0 0x330300 0x0 0x40>; + sound-name-prefix =3D "TDMIN_A"; + resets =3D <&clkc_audio AUD_RESET_TDMIN_A>; + clocks =3D <&clkc_audio AUD_CLKID_TDMIN_A>, + <&clkc_audio AUD_CLKID_TDMIN_A_SCLK>, + <&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>, + <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>, + <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>; + clock-names =3D "pclk", "sclk", "sclk_sel", + "lrclk", "lrclk_sel"; + }; + + tdmin_b: audio-controller@330340 { + compatible =3D "amlogic,sm1-tdmin"; + reg =3D <0x0 0x330340 0x0 0x40>; + sound-name-prefix =3D "TDMIN_B"; + resets =3D <&clkc_audio AUD_RESET_TDMIN_B>; + clocks =3D <&clkc_audio AUD_CLKID_TDMIN_B>, + <&clkc_audio AUD_CLKID_TDMIN_B_SCLK>, + <&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>, + <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>, + <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>; + clock-names =3D "pclk", "sclk", "sclk_sel", + "lrclk", "lrclk_sel"; + }; + + tdmin_c: audio-controller@330380 { + compatible =3D "amlogic,sm1-tdmin"; + reg =3D <0x0 0x330380 0x0 0x40>; + sound-name-prefix =3D "TDMIN_C"; + resets =3D <&clkc_audio AUD_RESET_TDMIN_C>; + clocks =3D <&clkc_audio AUD_CLKID_TDMIN_C>, + <&clkc_audio AUD_CLKID_TDMIN_C_SCLK>, + <&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>, + <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>, + <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>; + clock-names =3D "pclk", "sclk", "sclk_sel", + "lrclk", "lrclk_sel"; + }; + + tdmin_lb: audio-controller@3303c0 { + compatible =3D "amlogic,sm1-tdmin"; + reg =3D <0x0 0x3303c0 0x0 0x40>; + sound-name-prefix =3D "TDMIN_LB"; + resets =3D <&clkc_audio AUD_RESET_TDMIN_LB>; + clocks =3D <&clkc_audio AUD_CLKID_TDMIN_LB>, + <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>, + <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>, + <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>, + <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>; + clock-names =3D "pclk", "sclk", "sclk_sel", + "lrclk", "lrclk_sel"; + }; + + spdifin: audio-controller@330400 { + compatible =3D "amlogic,g12a-spdifin", + "amlogic,axg-spdifin"; + reg =3D <0x0 0x330400 0x0 0x30>; + #sound-dai-cells =3D <0>; + sound-name-prefix =3D "SPDIFIN"; + interrupts =3D ; + clocks =3D <&clkc_audio AUD_CLKID_SPDIFIN>, + <&clkc_audio AUD_CLKID_SPDIFIN_CLK>; + clock-names =3D "pclk", "refclk"; + resets =3D <&clkc_audio AUD_RESET_SPDIFIN>; + }; + + spdifout_a: audio-controller@330480 { + compatible =3D "amlogic,g12a-spdifout", + "amlogic,axg-spdifout"; + reg =3D <0x0 0x330480 0x0 0x50>; + #sound-dai-cells =3D <0>; + sound-name-prefix =3D "SPDIFOUT_A"; + clocks =3D <&clkc_audio AUD_CLKID_SPDIFOUT>, + <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>; + clock-names =3D "pclk", "mclk"; + resets =3D <&clkc_audio AUD_RESET_SPDIFOUT>; + }; + + tdmout_a: audio-controller@330500 { + compatible =3D "amlogic,sm1-tdmout"; + reg =3D <0x0 0x330500 0x0 0x40>; + sound-name-prefix =3D "TDMOUT_A"; + resets =3D <&clkc_audio AUD_RESET_TDMOUT_A>; + clocks =3D <&clkc_audio AUD_CLKID_TDMOUT_A>, + <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>, + <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>, + <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>, + <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>; + clock-names =3D "pclk", "sclk", "sclk_sel", + "lrclk", "lrclk_sel"; + }; + + tdmout_b: audio-controller@330540 { + compatible =3D "amlogic,sm1-tdmout"; + reg =3D <0x0 0x330540 0x0 0x40>; + sound-name-prefix =3D "TDMOUT_B"; + resets =3D <&clkc_audio AUD_RESET_TDMOUT_B>; + clocks =3D <&clkc_audio AUD_CLKID_TDMOUT_B>, + <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>, + <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>, + <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>, + <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>; + clock-names =3D "pclk", "sclk", "sclk_sel", + "lrclk", "lrclk_sel"; + }; + + tdmout_c: audio-controller@330580 { + compatible =3D "amlogic,sm1-tdmout"; + reg =3D <0x0 0x330580 0x0 0x40>; + sound-name-prefix =3D "TDMOUT_C"; + resets =3D <&clkc_audio AUD_RESET_TDMOUT_C>; + clocks =3D <&clkc_audio AUD_CLKID_TDMOUT_C>, + <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>, + <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>, + <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>, + <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>; + clock-names =3D "pclk", "sclk", "sclk_sel", + "lrclk", "lrclk_sel"; + }; + + spdifout_b: audio-controller@330680 { + compatible =3D "amlogic,g12a-spdifout", + "amlogic,axg-spdifout"; + reg =3D <0x0 0x330680 0x0 0x50>; + #sound-dai-cells =3D <0>; + sound-name-prefix =3D "SPDIFOUT_B"; + clocks =3D <&clkc_audio AUD_CLKID_SPDIFOUT_B>, + <&clkc_audio AUD_CLKID_SPDIFOUT_B_CLK>; + clock-names =3D "pclk", "mclk"; + resets =3D <&clkc_audio AUD_RESET_SPDIFOUT_B>; + }; + + toacodec: audio-controller@330740 { + compatible =3D "amlogic,s4-toacodec", + "amlogic,g12a-toacodec"; + reg =3D <0x0 0x330740 0x0 0x4>; + sound-name-prefix =3D "TOACODEC"; + #sound-dai-cells =3D <1>; + resets =3D <&clkc_audio AUD_RESET_TOACODEC>; + }; + + tohdmitx: audio-controller@330744 { + compatible =3D "amlogic,sm1-tohdmitx", + "amlogic,g12a-tohdmitx"; + reg =3D <0x0 0x330744 0x0 0x4>; + #sound-dai-cells =3D <1>; + sound-name-prefix =3D "TOHDMITX"; + resets =3D <&clkc_audio AUD_RESET_TOHDMITX>; + }; + + toddr_d: audio-controller@330840 { + compatible =3D "amlogic,sm1-toddr", + "amlogic,axg-toddr"; + reg =3D <0x0 0x330840 0x0 0x2c>; + #sound-dai-cells =3D <0>; + sound-name-prefix =3D "TODDR_D"; + interrupts =3D ; + clocks =3D <&clkc_audio AUD_CLKID_TODDR_D>; + resets =3D <&arb AXG_ARB_TODDR_D>, + <&clkc_audio AUD_RESET_TODDR_D>; + reset-names =3D "arb", "rst"; + amlogic,fifo-depth =3D <256>; + }; + + frddr_d: audio-controller@330880 { + compatible =3D "amlogic,sm1-frddr", + "amlogic,axg-frddr"; + reg =3D <0x0 0x330880 0x0 0x2c>; + #sound-dai-cells =3D <0>; + sound-name-prefix =3D "FRDDR_D"; + interrupts =3D ; + clocks =3D <&clkc_audio AUD_CLKID_FRDDR_D>; + resets =3D <&arb AXG_ARB_FRDDR_D>, + <&clkc_audio AUD_RESET_FRDDR_D>; + reset-names =3D "arb", "rst"; + amlogic,fifo-depth =3D <256>; + }; + + pdm: audio-controller@331000 { + compatible =3D "amlogic,sm1-pdm", + "amlogic,axg-pdm"; + reg =3D <0x0 0x331000 0x0 0x34>; + #sound-dai-cells =3D <0>; + sound-name-prefix =3D "PDM"; + clocks =3D <&clkc_audio AUD_CLKID_PDM>, + <&clkc_audio AUD_CLKID_PDM_DCLK>, + <&clkc_audio AUD_CLKID_PDM_SYSCLK>; + clock-names =3D "pclk", "dclk", "sysclk"; + resets =3D <&clkc_audio AUD_RESET_PDM>; + }; }; --=20 2.43.0