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Thu, 10 Jul 2025 07:03:15 -0500 Received: from DLEE103.ent.ti.com (157.170.170.33) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Thu, 10 Jul 2025 07:03:15 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Thu, 10 Jul 2025 07:03:15 -0500 Received: from localhost (bb.dhcp.ti.com [128.247.81.12]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 56AC3FrR1600545; Thu, 10 Jul 2025 07:03:15 -0500 From: Bryan Brattlof Date: Thu, 10 Jul 2025 07:03:10 -0500 Subject: [PATCH v2] arm64: dts: ti: k3-am62a7-sk: add boot phase tags Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250710-62a-uboot-cleanup-v2-1-9e04a7db1f54@ti.com> X-B4-Tracking: v=1; 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a=openpgp; fpr=D3D177E40A38DF4D1853FEEF41B90D5D71D56CE0 X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea The 'bootph-all' tag was added to the dt-schema to describe the various nodes used during the different phases of bootup with DT. Add the bootph-all tag to all nodes that are used during the early stages of bootup by the bootloaders. This includes the console UART along with the SD and eMMC nodes and its required regulators for the 3v3 to 1v8 transition and the various nodes for Ethernet booting. Signed-off-by: Bryan Brattlof --- Changes in v2: - removed tag from ethernet-ports{} as it was redundant - Link to v1: https://lore.kernel.org/r/20250709-62a-uboot-cleanup-v1-1-70f= 8e6cde719@ti.com --- arch/arm64/boot/dts/ti/k3-am62a7-sk.dts | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts b/arch/arm64/boot/dts/= ti/k3-am62a7-sk.dts index f11284b3fe8e23b4c48d8d2f3a7202e80dc57370..bceead5e288e6d78c671baf0afa= bd1a9aa23fbee 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts @@ -36,6 +36,7 @@ memory@80000000 { /* 4G RAM */ reg =3D <0x00000000 0x80000000 0x00000000 0x80000000>, <0x00000008 0x80000000 0x00000000 0x80000000>; + bootph-all; }; =20 reserved-memory { @@ -151,6 +152,7 @@ vdd_mmc1: regulator-3 { regulator-boot-on; enable-active-high; gpio =3D <&exp1 3 GPIO_ACTIVE_HIGH>; + bootph-all; }; =20 vcc_3v3_sys: regulator-4 { @@ -297,6 +299,7 @@ main_uart0_pins_default: main-uart0-default-pins { AM62AX_IOPAD(0x1c8, PIN_INPUT, 0) /* (E14) UART0_RXD */ AM62AX_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (D15) UART0_TXD */ >; + bootph-all; }; =20 main_uart1_pins_default: main-uart1-default-pins { @@ -320,6 +323,7 @@ main_i2c1_pins_default: main-i2c1-default-pins { AM62AX_IOPAD(0x1e8, PIN_INPUT_PULLUP, 0) /* (B17) I2C1_SCL */ AM62AX_IOPAD(0x1ec, PIN_INPUT_PULLUP, 0) /* (A17) I2C1_SDA */ >; + bootph-all; }; =20 main_i2c2_pins_default: main-i2c2-default-pins { @@ -356,6 +360,7 @@ AM62AX_IOPAD(0x228, PIN_INPUT, 0) /* (C21) MMC1_DAT2 */ AM62AX_IOPAD(0x224, PIN_INPUT, 0) /* (D22) MMC1_DAT3 */ AM62AX_IOPAD(0x240, PIN_INPUT, 0) /* (D17) MMC1_SDCD */ >; + bootph-all; }; =20 usr_led_pins_default: usr-led-default-pins { @@ -375,6 +380,7 @@ main_mdio1_pins_default: main-mdio1-default-pins { AM62AX_IOPAD(0x160, PIN_OUTPUT, 0) /* (V12) MDIO0_MDC */ AM62AX_IOPAD(0x15c, PIN_INPUT, 0) /* (V13) MDIO0_MDIO */ >; + bootph-all; }; =20 main_rgmii1_pins_default: main-rgmii1-default-pins { @@ -392,6 +398,7 @@ AM62AX_IOPAD(0x140, PIN_INPUT, 0) /* (AA17) RGMII1_TD3 = */ AM62AX_IOPAD(0x130, PIN_INPUT, 0) /* (AB17) RGMII1_TXC */ AM62AX_IOPAD(0x12c, PIN_INPUT, 0) /* (W16) RGMII1_TX_CTL */ >; + bootph-all; }; =20 main_mcasp1_pins_default: main-mcasp1-default-pins { @@ -572,6 +579,7 @@ exp1: gpio@22 { #interrupt-cells =3D <2>; pinctrl-names =3D "default"; pinctrl-0 =3D <&main_gpio1_ioexp_intr_pins_default>; + bootph-all; =20 gpio-line-names =3D "GPIO_CPSW2_RST", "GPIO_CPSW1_RST", "BT_EN_SOC", "MMC1_SD_EN", @@ -675,10 +683,12 @@ &sdhci1 { pinctrl-names =3D "default"; pinctrl-0 =3D <&main_mmc1_pins_default>; disable-wp; + bootph-all; }; =20 &main_gpio0 { status =3D "okay"; + bootph-all; }; =20 &main_gpio1 { @@ -693,6 +703,7 @@ &main_uart0 { status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&main_uart0_pins_default>; + bootph-all; }; =20 /* Main UART1 is used for TIFS firmware logs */ @@ -739,10 +750,15 @@ &cpsw3g { pinctrl-0 =3D <&main_rgmii1_pins_default>; }; =20 +&phy_gmii_sel { + bootph-all; +}; + &cpsw_port1 { status =3D "okay"; phy-mode =3D "rgmii-rxid"; phy-handle =3D <&cpsw3g_phy0>; + bootph-all; }; =20 &cpsw_port2 { @@ -759,6 +775,7 @@ cpsw3g_phy0: ethernet-phy@0 { ti,rx-internal-delay =3D ; ti,fifo-depth =3D ; ti,min-output-impedance; + bootph-all; }; }; =20 --- base-commit: 3b08f8a34a2061d89a2411d04a675b3860d4f9cc change-id: 20250623-62a-uboot-cleanup-b80e6952f91d Best regards, --=20 Bryan Brattlof