From nobody Tue Oct 7 14:05:32 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5658124500A for ; Wed, 9 Jul 2025 20:27:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752092842; cv=none; b=tpKM1L+ciNg6o1FLDAQ39Dx8yAxs642RJuKEUMPH2yJpUTQzfk5SIY3RCSaAx6MO9tsdNkxy497hXwWdsyLWcPJdCIzfGQdr9kZ5DBgLWK+XbxTAfLrL8rts5gc+/upgLQFKyxoVbnyBykfoeOM0N/5AkKqwlgXs5gGnuzok7GY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752092842; c=relaxed/simple; bh=FZ9H4/MGT0XYBHeY+H65v0m9KWcRSW93roPsQeAFDLA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=AqK7TyXbU8et+MAzzcXYRt8IqJfZruVcHTHD5fEkF+h/+DLg44oBjPxAbchhSsSTS75X5McHRwfiHOutqD8rY827Q+ZVsuTruh2xfzJLGqcANaWO7qTN2kvlRr9Ncd8m5K4e7v7THff5X4FYDlZuovzTq7jwmCYceM/IjHiZTNw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=pGHL+WZp; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=CB4vgEXX; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="pGHL+WZp"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="CB4vgEXX" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1752092839; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=av1RJLmDJc38MxsK1DauTEQVAq72KkzKxqMBwAWtSvk=; b=pGHL+WZpvfBJ7CNjZ0sYzhYvLcV2KDR43hFM9OBkFYvPgcT3jO5Qy1v987rMI/huga4ecJ pXtlAeRZxlz/0Ts1Qvafb2XSUObg7SOqkMuYD1PRGkm0c1Vh4RgbOKAqDi40735Vql1lbM UF8VEtJpcCa2yhXpArpoXSrN66XQV9fQABil+uKsRcL2URMkEdLZmRD9KJyofPGvhyfUCh NKpHihgQlA9Z/s/ZNjQiAzIL0hfSIAx+IYNhUqTRvYMm7O6VpDjkw410ARvoJ4DiynbUXz T//FWxfzxvJtzkqREbI2n1NhzD0KtDTHrX7OUJ3JmkC6DJDolh+xXUzWkmCarw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1752092839; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=av1RJLmDJc38MxsK1DauTEQVAq72KkzKxqMBwAWtSvk=; b=CB4vgEXX4BKrRqPnSa1Kicay2XyTJ2X38kbNkv4g779OUz0VNTl5ubvQLecekP/kPImIJw NTbPy6DdGznPIaDg== To: Borislav Petkov , Ingo Molnar , Dave Hansen Cc: Thomas Gleixner , Andrew Cooper , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v2 2/6] ASoC: Intel: avs: Include CPUID header at file scope Date: Wed, 9 Jul 2025 22:26:29 +0200 Message-ID: <20250709202635.89791-3-darwi@linutronix.de> In-Reply-To: <20250709202635.89791-1-darwi@linutronix.de> References: <20250612234010.572636-1-darwi@linutronix.de> <20250709202635.89791-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Commit cbe37a4d2b3c ("ASoC: Intel: avs: Configure basefw on TGL-based platform= s") includes the main CPUID header from within a C function. This works by luck and forbids valid refactorings inside the CPUID header. Include the CPUID header at file scope instead. Note, for the CPUID(0x15) leaf number, use CPUID_LEAF_TSC instead of defining a custom local macro for it. Signed-off-by: Ahmed S. Darwish Acked-by: Cezary Rojewski --- sound/soc/intel/avs/tgl.c | 25 ++++++++++++++++--------- 1 file changed, 16 insertions(+), 9 deletions(-) diff --git a/sound/soc/intel/avs/tgl.c b/sound/soc/intel/avs/tgl.c index 9dbb3ad0954a..cf19d3a7ced2 100644 --- a/sound/soc/intel/avs/tgl.c +++ b/sound/soc/intel/avs/tgl.c @@ -10,8 +10,6 @@ #include "avs.h" #include "messages.h" =20 -#define CPUID_TSC_LEAF 0x15 - static int avs_tgl_dsp_core_power(struct avs_dev *adev, u32 core_mask, boo= l power) { core_mask &=3D AVS_MAIN_CORE_MASK; @@ -39,22 +37,31 @@ static int avs_tgl_dsp_core_stall(struct avs_dev *adev,= u32 core_mask, bool stal return avs_dsp_core_stall(adev, core_mask, stall); } =20 +#ifdef CONFIG_X86 +#include +static unsigned int intel_crystal_freq_hz(void) +{ + return cpuid_ecx(CPUID_LEAF_TSC); +} +#else +static unsigned int intel_crystal_freq_hz(void) +{ + return 0; +} +#endif /* !CONFIG_X86 */ + static int avs_tgl_config_basefw(struct avs_dev *adev) { + unsigned int freq =3D intel_crystal_freq_hz(); struct pci_dev *pci =3D adev->base.pci; struct avs_bus_hwid hwid; int ret; -#ifdef CONFIG_X86 - unsigned int ecx; =20 -#include - ecx =3D cpuid_ecx(CPUID_TSC_LEAF); - if (ecx) { - ret =3D avs_ipc_set_fw_config(adev, 1, AVS_FW_CFG_XTAL_FREQ_HZ, sizeof(e= cx), &ecx); + if (freq) { + ret =3D avs_ipc_set_fw_config(adev, 1, AVS_FW_CFG_XTAL_FREQ_HZ, sizeof(f= req), &freq); if (ret) return AVS_IPC_RET(ret); } -#endif =20 hwid.device =3D pci->device; hwid.subsystem =3D pci->subsystem_vendor | (pci->subsystem_device << 16); --=20 2.49.0