From nobody Tue Oct 7 13:28:35 2025 Received: from mail-wr1-f43.google.com (mail-wr1-f43.google.com [209.85.221.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4A582227EAA; Wed, 9 Jul 2025 16:08:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.43 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752077316; cv=none; b=XLJusQDhz2xAt5S4An45x6gT815dJCQZWrRtD07+Yz5Q/SxnM5oPGMZiDEkcB09+RHdKchcPdPXc5ZwuMalOsTW2rwDlmZ0IYgQjXlcmutru9xua+y2A/3KWuEU9VpSrRrGNMrMUdsd4WiBcMnvo84VeRE/gVGBK4+x45OETVeM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752077316; c=relaxed/simple; bh=Ehs/IxozPcMhYr1TDm8jNGouEFl9DWXgjxz/LIgengk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=X/kwNtXodklmY8qaPhQ9OHzLL3tlzbEZdX5r4V4vYC4h+aFdylBUvz+xyHUc4ohuoWtt7qxoxCij/Ux5xeIQ/ZFAdZivuJjdbGwv+6K88qPHaE5qbs7V1685pR6ZVLptmh9rl7ozaKHSPJF2rFAXVntVQyeXh/htvC+zD8lp2ZU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=QyEHCYZ7; arc=none smtp.client-ip=209.85.221.43 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="QyEHCYZ7" Received: by mail-wr1-f43.google.com with SMTP id ffacd0b85a97d-3a522224582so64319f8f.3; Wed, 09 Jul 2025 09:08:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1752077313; x=1752682113; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ey7WdkVLv0tBLLtK0Co00XDASEfL95KiYEFMTV+z8Ug=; b=QyEHCYZ7X+TQP+k21Vmby3ilz20mY8bPkQQeqrgD0Kwgg7d1ZZRIuUFZ2hvJhXOYbY xzYdr4kCeE6p3f16D3TWX+jywM5R3z1twANCgWRmvgOAQHEFCCfsAutMv1CsPDJifQJd 2+n3YB9E3w+RGjew2OsWzhDz7Z2AUH+NY2PjYg6aHc9GMbTvwyYVQyi0ML2tz7GVPK8i 5wuJLQW0+fDIMmvEkJ4FLxm8dWQ5wpzredBi8hjBbD+ty1wF42hx+g/wZr4ygLv+uGJf K9qgg5xuLmPQ7lgPO6+ESXKlR1eyJ/bstsZz1EQ/Tl+IYpF3NXwPArYQ4qg33h7B2S5W DkBA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1752077313; x=1752682113; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ey7WdkVLv0tBLLtK0Co00XDASEfL95KiYEFMTV+z8Ug=; b=jbxfPCdu8a+ncybzE39o1mv+4ipIMTtiOe89nHzTLPM0CLtJHx4navTBCYqMJYTdR6 ksP0D3kDM6ZIyVV3Jy05HQIzsaZ3CysF0e+DEtzRbwKAI7SfZPkfkBvmuNDk7ZVeM2mB 5g3n7y2rVPXeJqQ3oQ/Q83lPcVqMvckXy4KNEOSwy3pjtH1RGohtbbN7zQ3neUE4FJeO hgHxuO9w7DL8tAyab8ftk7W6/BTRfSMWAQ/zh4MsbYbN/a6FvYBTZZYfaVQisAvWsEWS HEXpKvc+PIbz35tKuTInvUZtjThf8NHxVYEUVaWozoKadg1l8RJ9KtZDCTGTrEDGIoic VBpw== X-Forwarded-Encrypted: i=1; AJvYcCVO+mMHQa0Wo0dRPjxtqMKUX1a1zoXKb0Di+z8WjCuHSAullFCw9g4LGTPA26TtRfeHyTRLxpoYz2eYcbyD@vger.kernel.org, AJvYcCWJr6+vVVTu2g9pfZJE7mmP/JkRqoQOgvCzbC2VaEMi1oX2gm86KKmCcRA6Ybey9nwBf6BsLyQQGX49@vger.kernel.org X-Gm-Message-State: AOJu0YwUqy6lnND/NUxVGOj9jNYSw4Ota9z1vNNIQwIVSxwASBSWIQH0 zmhRaOKLWu6CPx6DM2iVO4PiCT+YRQtCcIGChiD/1xWXI+WexY6NLONr X-Gm-Gg: ASbGncs2bkNSUpDt3JVY+W6+OGailM9RsKqMWAn2/17yti2zqGSn4+3cvnK+KhVuGMU Z9bzmZ/unbyrHNKbQQnRNjUUePkYcEVuHrE5msfwnUH0uyEooDujV46h5PXtsUjPNj5cIZv92fy D5e4OFI2c2j1VvNdFdS6UPizmzHtsuy+tiecQ5AvXsACR0C2EgAm20r6uQNM+iv7TzXTCavyv1m hNDIBzJL5XqLmcBJmZ1kQ9S1Btp6mfgBhJASQ8vsSmXVD3TYOSkZrpQoPoLXWrEiIx90uid3bJR q4bQze4/hJR7W226Fx8+LIS3/JdB3bceA7jNepjqcnK/sCBpdUA6aUjyx+l9jezkeekv4wk5b4J FK48S8AJxj8A= X-Google-Smtp-Source: AGHT+IFyhTKnTrcnRIYB6EpfCGhWfyHCSHFHwr02yaTHMXSzLsNU4t0ih3bdjbzCXrVig39NY454vw== X-Received: by 2002:a05:6000:26d0:b0:3a4:cfbf:51a0 with SMTP id ffacd0b85a97d-3b5e44e9f8emr2910253f8f.21.1752077313198; Wed, 09 Jul 2025 09:08:33 -0700 (PDT) Received: from iku.Home ([2a06:5906:61b:2d00:c930:b02d:bf60:750b]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3b471b9671asm16639686f8f.53.2025.07.09.09.08.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Jul 2025 09:08:32 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Linus Walleij Cc: linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , John Madieu , Lad Prabhakar Subject: [PATCH v2 1/7] pinctrl: renesas: rzg2l: Fix invalid unsigned return in rzg3s_oen_read() Date: Wed, 9 Jul 2025 17:08:13 +0100 Message-ID: <20250709160819.306875-2-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250709160819.306875-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250709160819.306875-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar rzg3s_oen_read() returns a u32 value, but previously propagated a negative error code from rzg3s_pin_to_oen_bit(), resulting in an unintended large positive value due to unsigned conversion. This caused incorrect output-enable reporting for certain pins. Without this patch, pins P1_0-P1_4 and P7_0-P7_4 are incorrectly reported as "output enabled" in the pinconf-pins debugfs file. With this fix, only P1_0-P1_1 and P7_0-P7_1 are shown as "output enabled", which matches the hardware manual. Fix this by returning 0 when the OEN bit lookup fails, treating the pin as output-disabled by default. Fixes: a9024a323af2 ("pinctrl: renesas: rzg2l: Clean up and refactor OEN re= ad/write functions") Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/rene= sas/pinctrl-rzg2l.c index 2a10ae0bf5bd..af4a40ca0a98 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -1124,7 +1124,7 @@ static u32 rzg3s_oen_read(struct rzg2l_pinctrl *pctrl= , unsigned int _pin) =20 bit =3D rzg3s_pin_to_oen_bit(pctrl, _pin); if (bit < 0) - return bit; + return 0; =20 return !(readb(pctrl->base + ETH_MODE) & BIT(bit)); } --=20 2.49.0 From nobody Tue Oct 7 13:28:35 2025 Received: from mail-wr1-f51.google.com (mail-wr1-f51.google.com [209.85.221.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4513F2E9722; Wed, 9 Jul 2025 16:08:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752077319; cv=none; b=EDSiKn8z/ajbLYkpBkXo5LvgYXLBncca22DjrPsLE6x6a6jkrjIbB+5xlARqRd9V/z8QnxgVxm2/P7gYiRONmeBuNnXC45iZLsi8sAPTA7jVwfnzF+Ppz3miEvbj8zW27fIOroIc8Bjj4DahEOe97d4hsQmuBqCKeU1gBEy7nfM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752077319; c=relaxed/simple; bh=FEefdo7gGWDr8pupO9oyHxETp/w8tXE1asAKs8xFNf4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=hUV73Op7XpsJdJPZY4yrVkev0TksrW3eShGwjF4lhvkjKB+G2sJiBaMsOKxfgKPdN28qAruJWh9ZY0MgvWilB7g/HjMaWidkcZoZiM5ETi2RXR4Mg+5mXoZBpbAhwwHOfhEouQX98A4/xOo72VEFtEEa33zvFs6SMM0o/7r4phk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=bQpXxVWa; arc=none smtp.client-ip=209.85.221.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="bQpXxVWa" Received: by mail-wr1-f51.google.com with SMTP id ffacd0b85a97d-3a6d1369d4eso76398f8f.2; Wed, 09 Jul 2025 09:08:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1752077315; x=1752682115; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=76nVrXKIo/jAoyMI3XJ2QxZEzzS9N+bzV0hB2Ue/F9s=; b=bQpXxVWa/DTj/z2n4K6r+/f2ruX/hBNbuIvgULKLIoIzAuF6xXmRNzfpHhbMQ4F0me 8f3Mm1VKB9Nfae2EhUGVy7624IP7eZm6/iIJONQOGOS5+J+UlGBHoMJmFSNkMh6Z8jV8 CTUjfWJti7y+gDZ8rQlgvaLoIVC/957ld74ouwHwRUh1rsqjYOLeEG+zVsBDJqjtVaby gtp8EJ10uzRFcyCDT4JOyS60NQ1J+OReMX4QBwKJJ8YxZgWcQiow4WaN7PrMTI+QWCfg 0thyjYcbReAn5wGyBlUgeq1kpF4cmDG9zkgVW0SOFr2gK71HJF66ethWhqFgHHJvdVwh ANhw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1752077315; x=1752682115; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=76nVrXKIo/jAoyMI3XJ2QxZEzzS9N+bzV0hB2Ue/F9s=; b=V2ApXnDMHu0LfvP7QBN+DpSYR7VADBmadukkb4gpI3EoD78aNcBILN9Di0AM1rsEFA F0/XfcYzBjX1Dd28deP4gK8DBPMSg/jlEosPvottg6lauHfxnV0oj8j3cwLs3g6ZyuLD LvPP+Fl1IREysXqIuYAPpsaJKmiDsg8u1qdp6QurSarReONlE4lXMM/yLYIRL4H5kP8o UbSSgoWnhDdgoCbbg1yB2Tw8SEEDlBhtdeJkrhsP1j0SVTBVmAWSxceTOy//hE3+CoXi 88+EaoMPlwCJSXeIsw6amMoMJHKTxdxJLM+Bof6YHtf7xN4nkxUKXDX/jMnahFqScPmF KRCA== X-Forwarded-Encrypted: i=1; AJvYcCXAo6z2TlMPSFXeXMrg2noYPmVGgchwgjPv4l9Ab9UzE5aCiJ3jGu5Z1ZNQLTVLNtQjLqdt9wlQjJZQ@vger.kernel.org, AJvYcCXMrgtUclHKkj6Qw7UgXOvH7/HnssaddbG2a8idGCNq6Y/oef0Kx8UN+Si/XvxUb7S+538UEzaddm38N3kN@vger.kernel.org X-Gm-Message-State: AOJu0YyJJrZp7Xbg0s6gjn9nGGC1/cfUWdSK4pRpIfN66KlO76YasL/c tM4x0H37U7Vn1oZwymwnmulJdzxeIJDdArf1AMAmjV7Ql7tYFX6a5H4D X-Gm-Gg: ASbGncs3H6iqvEHRKFgXhhBaMRAg6jXZxQZq6X5WX3fwl41yCweIqSAbDS83ZgyffTs WDt+7QDfcmFf6vYIjLwKAL4U8QVozrWM57OiiKNyMC5FdYLVF7IBH0U8YCCIgRYVWBp6kWX3P9K sd/HgpmnZ2kKVdHOV0XFAOyg2x/UX5rjVLF2CSR9HMGJv1IIfsqvtCWDH98PeUQthafy2u7DG7m z23vuOB0oxH6tlLzsrcU4u7lyUbDimScZUBaJd6+l+0BZlh7YrGsTeeu6gL2HOB6Hv3Drx9NDho NVok3+n9dTe14ISnT31DhWNmocCs/u2O8tIcmyFgNw7RlWgT8dwHSrzemBglOz+zaBZUmadQd9S hdsnwGpcurXg= X-Google-Smtp-Source: AGHT+IFuCxtYJhXND6eyKWWcAAqQN0A94wPLMPZtK2WkaLNK7Rw8E5vO4D2G3lHFasSYQ96k2Cs5KQ== X-Received: by 2002:a05:6000:220d:b0:3a4:ed10:c14 with SMTP id ffacd0b85a97d-3b5e44e94damr2641451f8f.14.1752077314326; Wed, 09 Jul 2025 09:08:34 -0700 (PDT) Received: from iku.Home ([2a06:5906:61b:2d00:c930:b02d:bf60:750b]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3b471b9671asm16639686f8f.53.2025.07.09.09.08.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Jul 2025 09:08:33 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Linus Walleij Cc: linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , John Madieu , Lad Prabhakar Subject: [PATCH v2 2/7] pinctrl: renesas: rzg2l: parameterize OEN register offset Date: Wed, 9 Jul 2025 17:08:14 +0100 Message-ID: <20250709160819.306875-3-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250709160819.306875-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250709160819.306875-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Prepare for supporting SoCs with varying OEN register locations by parameterizing the OEN offset in the rzg2l driver. Introduce an `oen` field in the rzg2l_register_offsets structure and update rzg2l_read_oen(), rzg2l_write_oen(), suspend/resume caching, and SoC hwcfg entries to use this offset instead of the hard-coded ETH_MODE value. Signed-off-by: Lad Prabhakar --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 23 ++++++++++++++--------- 1 file changed, 14 insertions(+), 9 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/rene= sas/pinctrl-rzg2l.c index af4a40ca0a98..75b5bd032659 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -146,7 +146,6 @@ #define SD_CH(off, ch) ((off) + (ch) * 4) #define ETH_POC(off, ch) ((off) + (ch) * 4) #define QSPI (0x3008) -#define ETH_MODE (0x3018) #define PFC_OEN (0x3C40) /* known on RZ/V2H(P) only */ =20 #define PVDD_2500 2 /* I/O domain voltage 2.5V */ @@ -221,11 +220,13 @@ static const struct pin_config_item renesas_rzv2h_con= f_items[] =3D { * @pwpr: PWPR register offset * @sd_ch: SD_CH register offset * @eth_poc: ETH_POC register offset + * @oen: OEN register offset */ struct rzg2l_register_offsets { u16 pwpr; u16 sd_ch; u16 eth_poc; + u16 oen; }; =20 /** @@ -1073,11 +1074,12 @@ static u32 rzg2l_read_oen(struct rzg2l_pinctrl *pct= rl, unsigned int _pin) if (bit < 0) return 0; =20 - return !(readb(pctrl->base + ETH_MODE) & BIT(bit)); + return !(readb(pctrl->base + pctrl->data->hwcfg->regs.oen) & BIT(bit)); } =20 static int rzg2l_write_oen(struct rzg2l_pinctrl *pctrl, unsigned int _pin,= u8 oen) { + u16 oen_offset =3D pctrl->data->hwcfg->regs.oen; unsigned long flags; int bit; u8 val; @@ -1087,12 +1089,12 @@ static int rzg2l_write_oen(struct rzg2l_pinctrl *pc= trl, unsigned int _pin, u8 oe return bit; =20 spin_lock_irqsave(&pctrl->lock, flags); - val =3D readb(pctrl->base + ETH_MODE); + val =3D readb(pctrl->base + oen_offset); if (oen) val &=3D ~BIT(bit); else val |=3D BIT(bit); - writeb(val, pctrl->base + ETH_MODE); + writeb(val, pctrl->base + oen_offset); spin_unlock_irqrestore(&pctrl->lock, flags); =20 return 0; @@ -1126,11 +1128,12 @@ static u32 rzg3s_oen_read(struct rzg2l_pinctrl *pct= rl, unsigned int _pin) if (bit < 0) return 0; =20 - return !(readb(pctrl->base + ETH_MODE) & BIT(bit)); + return !(readb(pctrl->base + pctrl->data->hwcfg->regs.oen) & BIT(bit)); } =20 static int rzg3s_oen_write(struct rzg2l_pinctrl *pctrl, unsigned int _pin,= u8 oen) { + u16 oen_offset =3D pctrl->data->hwcfg->regs.oen; unsigned long flags; int bit; u8 val; @@ -1140,12 +1143,12 @@ static int rzg3s_oen_write(struct rzg2l_pinctrl *pc= trl, unsigned int _pin, u8 oe return bit; =20 spin_lock_irqsave(&pctrl->lock, flags); - val =3D readb(pctrl->base + ETH_MODE); + val =3D readb(pctrl->base + oen_offset); if (oen) val &=3D ~BIT(bit); else val |=3D BIT(bit); - writeb(val, pctrl->base + ETH_MODE); + writeb(val, pctrl->base + oen_offset); spin_unlock_irqrestore(&pctrl->lock, flags); =20 return 0; @@ -3164,7 +3167,7 @@ static int rzg2l_pinctrl_suspend_noirq(struct device = *dev) } =20 cache->qspi =3D readb(pctrl->base + QSPI); - cache->eth_mode =3D readb(pctrl->base + ETH_MODE); + cache->eth_mode =3D readb(pctrl->base + pctrl->data->hwcfg->regs.oen); =20 if (!atomic_read(&pctrl->wakeup_path)) clk_disable_unprepare(pctrl->clk); @@ -3189,7 +3192,7 @@ static int rzg2l_pinctrl_resume_noirq(struct device *= dev) } =20 writeb(cache->qspi, pctrl->base + QSPI); - writeb(cache->eth_mode, pctrl->base + ETH_MODE); + writeb(cache->eth_mode, pctrl->base + pctrl->data->hwcfg->regs.oen); for (u8 i =3D 0; i < 2; i++) { if (regs->sd_ch) writeb(cache->sd_ch[i], pctrl->base + SD_CH(regs->sd_ch, i)); @@ -3241,6 +3244,7 @@ static const struct rzg2l_hwcfg rzg2l_hwcfg =3D { .pwpr =3D 0x3014, .sd_ch =3D 0x3000, .eth_poc =3D 0x300c, + .oen =3D 0x3018, }, .iolh_groupa_ua =3D { /* 3v3 power source */ @@ -3256,6 +3260,7 @@ static const struct rzg2l_hwcfg rzg3s_hwcfg =3D { .pwpr =3D 0x3000, .sd_ch =3D 0x3004, .eth_poc =3D 0x3010, + .oen =3D 0x3018, }, .iolh_groupa_ua =3D { /* 1v8 power source */ --=20 2.49.0 From nobody Tue Oct 7 13:28:35 2025 Received: from mail-wr1-f49.google.com (mail-wr1-f49.google.com [209.85.221.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 023A82E5B0E; Wed, 9 Jul 2025 16:08:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.49 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752077318; cv=none; b=SAytKvrZOeP1wO7f+eZHd//cXj4ytkBLv93EnWTTahyWcWMM3/199ct/vEHmgABdGyTiZVA66ciBbVnIIJ48sJ/cMPbgElOseifZoh6vVgHU+UIsUZQozpQBwY3CLkqLCDTzazZuZBOJr/J8vbpz6pP3Mo7a7NhmycWK6sYpkSk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752077318; c=relaxed/simple; bh=eyzMrV4oXkoY0Xog7pWNxsaUDeTlHVhYnqbpICNTXzw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=rpSHlXHEIH+ch/zGeWLE8DmJUutV6eofg1d8CjoaClYov9GWoLauMhDiIvrgSEWiec0UG0oDR5pzR4AGXxF5hKOqlZwz0Ddsxq4Z/Yjn2bo3I05bfg3Vi1vu/fb9kd+lCzcC3Ls7sX6lgQvEJHW3FyRit2X53gJBSqLj+fWdTPc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=ZsoYIvWG; arc=none smtp.client-ip=209.85.221.49 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="ZsoYIvWG" Received: by mail-wr1-f49.google.com with SMTP id ffacd0b85a97d-3b45edf2303so109563f8f.2; Wed, 09 Jul 2025 09:08:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1752077315; x=1752682115; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=WbEQbP0gHmoeU8ky70blwCNCDEnSUfgldHxfZOgWw5I=; b=ZsoYIvWG1MjTGfsqarWX3GUVeqRnIrCwhBuWnVFe+cmPr0ufTdH32IMGcn8bHa0Efe U5Eq0jpCsTIbyXqaZLGNg01vbk9JSQqDBPiwwDqw9j48Mz9Y5DJGpbRzjwqk23/9q7qM 0/OxrizS9qwgMhqnNEHF/YA/iQFGd8Kgv+rwTiSIRlo7TXOYpnVDf49qEXNaLYSmz1nt 6fAjH7j4vIpTlxve/M7122PHnYeUKvVrGEGRWQn8CuRDBdT9yrtWvAVx+Fc2UxccR2XD m3Sgxdpa/LivEJpv6XL3VnYuTLe9Mt4+78RKZUxUdV1xIYON0tkZ2K11higN5HoQuTpd kxyA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1752077315; x=1752682115; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WbEQbP0gHmoeU8ky70blwCNCDEnSUfgldHxfZOgWw5I=; b=A3HBxapCs0L6yEXt7+8+Qu2ZOoPjnqnoZzkRorOl5IrY7VTLxP0lgRgcAAyECKshI3 5FbSTeZNdC9vK8RE47OcvaBSZw700nKBCx0fph3/exGSFnVaStye1BfTG3fcxa79Xoia WId9K/WB6N2rA98fk8GiDRKLp/X7nZovIrgZchcLtHZzXA2f9+twVaPuguAaqD3EwUuH 2ttZPNJqvbt0TXsXClmhxL2TrpYZeIo2zi8vrPttuE5PXCCT90CmVXGU77V5evGOm+dF Yo01HPB3NsslPaVGzXgu9KiQhba7B8O5KFo4qoRW6KlrLIcjR+mpSJzjR5q6F16fyz9b UlFg== X-Forwarded-Encrypted: i=1; AJvYcCU6UCiNV6XQTnf04Ko1ce/aDlzvsPzie0XRo7yLV5Kb9N+v/rcBauLK37r55VKBGYdcG+bcov91ICZuGL2+@vger.kernel.org, AJvYcCUZfBHEnkOzZpqXyeTrY7wQ+JvZh6l4vfVdlUseDtz5+003km0l97VTABfggxjv16OzjCneo5UNKXAl@vger.kernel.org X-Gm-Message-State: AOJu0YxyPAZCvLhn7dtWZxEFlrB4O5Sj1pNWpqLbAVAP4/8/xQ+Akg31 oodWeHpGkzW2IK9D1KiOvfX1QhR4G7cXeCI13mt/AVnA2oiFzE4PFhv7 X-Gm-Gg: ASbGnctL1Y3YAyKzBp8jHAv9sOPH4MtLjXAJ7enIu5oajk/dj4nVu/19uWfBMnisSoa RBJ3fnPC4lzBfVq1Z0FwV8LEaQYutAzrlwB9NyYaotD50Y5whPjHJdP6HeWajXANldUZtm8X0Bm F+FeOI4U9+Lt3cKSRQVT3wkpY5kU5DFly8A7sjqmE6LS8cmNuNCpyWBrJmJvKaxrQho1JEF6lti JXaCUDmKUsJjB+7HMpFcCrLE7PJPx3UyjJLinB+AvKk6mXIVbqdpAmaVwYyX1uFoJusIcpnLo6E tRfUdHXZVHdDOa0o7DlmOvfnuaKDWRZuvU2963gQOumMW8t3xoswY5uVNqIPakgzVOnvyuUqIan yeVfhyHAAUK8a1vsIP2vHkg== X-Google-Smtp-Source: AGHT+IEZcEEvfIU/FjGFchPJNxOYfIPPGBA1O+qz1PV9gOHFHWQo3MX10WhWH6m/oCxo/TXjelyY+w== X-Received: by 2002:a05:6000:4608:b0:3a5:2ef8:34f9 with SMTP id ffacd0b85a97d-3b5e45245e9mr2722850f8f.27.1752077315108; Wed, 09 Jul 2025 09:08:35 -0700 (PDT) Received: from iku.Home ([2a06:5906:61b:2d00:c930:b02d:bf60:750b]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3b471b9671asm16639686f8f.53.2025.07.09.09.08.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Jul 2025 09:08:34 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Linus Walleij Cc: linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , John Madieu , Lad Prabhakar Subject: [PATCH v2 3/7] pinctrl: renesas: rzg2l: Unify OEN access by making pin-to-bit mapping configurable Date: Wed, 9 Jul 2025 17:08:15 +0100 Message-ID: <20250709160819.306875-4-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250709160819.306875-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250709160819.306875-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Refactor the RZG2L pinctrl driver to support reuse of the common rzg2l_read_oen() and rzg2l_write_oen() helpers across SoCs with different output-enable (OEN) bit mappings. Introduce a new `pin_to_oen_bit` callback in `struct rzg2l_pinctrl_data` to allow SoCs to provide custom logic for mapping a pin to its OEN bit. Update the generic OEN read/write paths to use this callback when present. With this change, SoCs like RZ/G3S can reuse the common OEN handling code by simply supplying their own `pin_to_oen_bit` implementation. The previously duplicated `rzg3s_oen_read()` and `rzg3s_oen_write()` functions are now removed. This improves maintainability and prepares the driver for supporting future SoCs with minimal duplication. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 52 +++++++------------------ 1 file changed, 13 insertions(+), 39 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/rene= sas/pinctrl-rzg2l.c index 75b5bd032659..345ee709363b 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -296,6 +296,7 @@ struct rzg2l_pinctrl_data { #endif void (*pwpr_pfc_lock_unlock)(struct rzg2l_pinctrl *pctrl, bool lock); void (*pmc_writeb)(struct rzg2l_pinctrl *pctrl, u8 val, u16 offset); + int (*pin_to_oen_bit)(struct rzg2l_pinctrl *pctrl, unsigned int _pin); u32 (*oen_read)(struct rzg2l_pinctrl *pctrl, unsigned int _pin); int (*oen_write)(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen); int (*hw_to_bias_param)(unsigned int val); @@ -1070,7 +1071,9 @@ static u32 rzg2l_read_oen(struct rzg2l_pinctrl *pctrl= , unsigned int _pin) { int bit; =20 - bit =3D rzg2l_pin_to_oen_bit(pctrl, _pin); + if (!pctrl->data->pin_to_oen_bit) + return 0; + bit =3D pctrl->data->pin_to_oen_bit(pctrl, _pin); if (bit < 0) return 0; =20 @@ -1084,9 +1087,11 @@ static int rzg2l_write_oen(struct rzg2l_pinctrl *pct= rl, unsigned int _pin, u8 oe int bit; u8 val; =20 - bit =3D rzg2l_pin_to_oen_bit(pctrl, _pin); + if (!pctrl->data->pin_to_oen_bit) + return -EINVAL; + bit =3D pctrl->data->pin_to_oen_bit(pctrl, _pin); if (bit < 0) - return bit; + return -EINVAL; =20 spin_lock_irqsave(&pctrl->lock, flags); val =3D readb(pctrl->base + oen_offset); @@ -1120,40 +1125,6 @@ static int rzg3s_pin_to_oen_bit(struct rzg2l_pinctrl= *pctrl, unsigned int _pin) return bit; } =20 -static u32 rzg3s_oen_read(struct rzg2l_pinctrl *pctrl, unsigned int _pin) -{ - int bit; - - bit =3D rzg3s_pin_to_oen_bit(pctrl, _pin); - if (bit < 0) - return 0; - - return !(readb(pctrl->base + pctrl->data->hwcfg->regs.oen) & BIT(bit)); -} - -static int rzg3s_oen_write(struct rzg2l_pinctrl *pctrl, unsigned int _pin,= u8 oen) -{ - u16 oen_offset =3D pctrl->data->hwcfg->regs.oen; - unsigned long flags; - int bit; - u8 val; - - bit =3D rzg3s_pin_to_oen_bit(pctrl, _pin); - if (bit < 0) - return bit; - - spin_lock_irqsave(&pctrl->lock, flags); - val =3D readb(pctrl->base + oen_offset); - if (oen) - val &=3D ~BIT(bit); - else - val |=3D BIT(bit); - writeb(val, pctrl->base + oen_offset); - spin_unlock_irqrestore(&pctrl->lock, flags); - - return 0; -} - static int rzg2l_hw_to_bias_param(unsigned int bias) { switch (bias) { @@ -3310,6 +3281,7 @@ static struct rzg2l_pinctrl_data r9a07g043_data =3D { #endif .pwpr_pfc_lock_unlock =3D &rzg2l_pwpr_pfc_lock_unlock, .pmc_writeb =3D &rzg2l_pmc_writeb, + .pin_to_oen_bit =3D &rzg2l_pin_to_oen_bit, .oen_read =3D &rzg2l_read_oen, .oen_write =3D &rzg2l_write_oen, .hw_to_bias_param =3D &rzg2l_hw_to_bias_param, @@ -3327,6 +3299,7 @@ static struct rzg2l_pinctrl_data r9a07g044_data =3D { .hwcfg =3D &rzg2l_hwcfg, .pwpr_pfc_lock_unlock =3D &rzg2l_pwpr_pfc_lock_unlock, .pmc_writeb =3D &rzg2l_pmc_writeb, + .pin_to_oen_bit =3D &rzg2l_pin_to_oen_bit, .oen_read =3D &rzg2l_read_oen, .oen_write =3D &rzg2l_write_oen, .hw_to_bias_param =3D &rzg2l_hw_to_bias_param, @@ -3343,8 +3316,9 @@ static struct rzg2l_pinctrl_data r9a08g045_data =3D { .hwcfg =3D &rzg3s_hwcfg, .pwpr_pfc_lock_unlock =3D &rzg2l_pwpr_pfc_lock_unlock, .pmc_writeb =3D &rzg2l_pmc_writeb, - .oen_read =3D &rzg3s_oen_read, - .oen_write =3D &rzg3s_oen_write, + .pin_to_oen_bit =3D &rzg3s_pin_to_oen_bit, + .oen_read =3D &rzg2l_read_oen, + .oen_write =3D &rzg2l_write_oen, .hw_to_bias_param =3D &rzg2l_hw_to_bias_param, .bias_param_to_hw =3D &rzg2l_bias_param_to_hw, }; --=20 2.49.0 From nobody Tue Oct 7 13:28:35 2025 Received: from mail-wr1-f53.google.com (mail-wr1-f53.google.com [209.85.221.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 20C672E9EB1; Wed, 9 Jul 2025 16:08:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752077319; cv=none; b=UC3Xp+y7iB7/HgV0cA0uU9OwlNbx63OBgKooTKgy43MVSbWt3Sn9xePNb4Ka3QgCFK0mM5uqmZS+wkTf5+QI8fVB1SApYH+RyR3ii2TU1jfdAiIKaj79swCQuHKEsK4ESDtEc6Kj/Qol29Ce4sHbwnDOXpxB4bSWshJr99PCdfc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752077319; c=relaxed/simple; bh=kQg2I+XJl4ihRUBL6W+xK4p3ztFjK9G4FA8VGAo5ChQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=PgT5+sbbvA6tZKwB/mx++bCqFeGrWWlH1LvnSU/EGPQImOPm+Sop9ZUJWYbt5ZZb7wRDT7hY0Z5ip9nrvn1m+uOidwVu791zoR22s49nIbWFk1QDcTm+Rz02IQMh6hon97itY1bt8NCkJb2spQnJiL2PgcFm7ecYAUIuvcZiLtU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=lfapYCVI; arc=none smtp.client-ip=209.85.221.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="lfapYCVI" Received: by mail-wr1-f53.google.com with SMTP id ffacd0b85a97d-3a4ef2c2ef3so80333f8f.2; Wed, 09 Jul 2025 09:08:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1752077316; x=1752682116; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=nn1ViZV2LOQQXzFk4XjikcfNiQCWJRxcn9ezMpVHTg0=; b=lfapYCVICnB4Ardf5Bgfqa1m/qQR6HBRt92zBh4YbtVDyjY35I4P5PTkBJCloRA4W5 6QzAWDk9m+xIe5UsWQjkL/fSutSKNUglMfK5F/MRQQlqL9c8FN+sWfJmkCaHQ+6AZJQH bzGqqF1x01x5Q0kRcOhkXuAxj6zL9pjuG6r0FBTPP1Oa2t/lr3MkiR7I90YO6Bl+h1xu licqXJ6EZ7N22zYx5H3K8OXWtuYcZp+dwmiefKDyW0imaNJoQRNfahwtjvyfETqOEI4H X3aW4E0TAXxmaWOV+4rw5SxdYMyXOVDUSI0zYNJwycXcoHWRSScnh1DMUp/D7LNcTT4k CWKw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1752077316; x=1752682116; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=nn1ViZV2LOQQXzFk4XjikcfNiQCWJRxcn9ezMpVHTg0=; b=uXfF/Bx0lg7wbs7kE7REV/0chGOeHJQOXjK57SxISvU+cPPTv4p8Z1r88OJZpzu/lp qzmKvkQ/OvC4J41Pq8CopyHBcPHdJEaf5Y45DA62n1oTTyNvMXJdVAzz+XQrdS7n1MVi GFdioLfk/R5b4gixMW/1UwuVd1PwPBqn0CHq45dyyrzKN5MDc0Iff7k2+I5apjadENH5 uX8764cyF6UJ/TKucT1m1xsBYhA8+76DQRYk6jl8bEG/edqaDGGY1KQlyJSTlb44mRWd EBEbMymkpcK99M5BLP60lfJ+hfW4ANKBYYkrZGvqNJnuUItOC/AGQVa7Bn0baPIojLpf 4WCg== X-Forwarded-Encrypted: i=1; AJvYcCVS2RluKcgxwjLy7uKgwXvrbQGyBVWkip7BPEkWEYVt99qdIxlr+CeVNt98jFENoyjc9rAl3UwbHXYB6pGM@vger.kernel.org, AJvYcCXI2kMEm/kZIhnK/4oR1Q8dCkpe9xZqumTWB8tJYYg+eVm6/E14bYlIngnhUbk6VJvG2pH13Usu2V33@vger.kernel.org X-Gm-Message-State: AOJu0YwAZJUT9NO77ueXU/6H5aIUepFSE07Z0qP+AR054UfT9XRafQpL uHdowj/dUhb8O+0v3LmYC21dfQhCG1SX4fzSEBvFJ7QYFlA1a7gN2WUA X-Gm-Gg: ASbGncv9EYJ62qcePHAbVzA9RUlYI7gzNxa3KD9GG58jhC3WiFaL0yjIcPLsWRCq1lA kGPX+6OvEEFIbcy2npNnmB3N/ZRg3sl6bVHSSd28TkNDqYinmxS4OMdfmsEpovGh3K1G2KRMCfR /oc5PSf442w6jjBlzZkFILh/cwQUpDc+xPgOAyjZH85uokMcMVmeflO0cd7hFj/X99Tq3yYhHJH F+Of17nwPyqqGpb1/kVG0ekbmNhxAROVvRtI220My3AaXGv8r0pQHgB57hBdFvxecddqLd6DJmE OBes6mht9wWj6s2uIxdWn/kBtLCHlpUFHXtAd09IXJ2UGbA/DHZm/C21g6rYDG6w+aplDoIz7fK 8seQcS6/xDOQ= X-Google-Smtp-Source: AGHT+IFSqNDJA1edYUq91XlKZRAF2b1pbWNd8O3+ULQPCxFxTICdsLeKRJ9w4sIIN/31FtET8hIfqg== X-Received: by 2002:a05:6000:2911:b0:3a6:d95c:5db with SMTP id ffacd0b85a97d-3b5e44eda66mr2878945f8f.26.1752077316137; Wed, 09 Jul 2025 09:08:36 -0700 (PDT) Received: from iku.Home ([2a06:5906:61b:2d00:c930:b02d:bf60:750b]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3b471b9671asm16639686f8f.53.2025.07.09.09.08.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Jul 2025 09:08:35 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Linus Walleij Cc: linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , John Madieu , Lad Prabhakar Subject: [PATCH v2 4/7] pinctrl: renesas: rzg2l: Remove OEN ops for RZ/G3E Date: Wed, 9 Jul 2025 17:08:16 +0100 Message-ID: <20250709160819.306875-5-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250709160819.306875-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250709160819.306875-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar The RZ/G3E pin controller does not advertise PIN_CFG_OEN capability, so there is no valid mapping for output-enable bits on this SoC. Remove the oen_read and oen_write callbacks from the RZ/G3E driver data to defer OEN support until PIN_CFG_OEN support is added. This is a preparatory change for future unification of OEN handling across the driver. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/rene= sas/pinctrl-rzg2l.c index 345ee709363b..cf0b92c661d9 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -3340,8 +3340,6 @@ static struct rzg2l_pinctrl_data r9a09g047_data =3D { #endif .pwpr_pfc_lock_unlock =3D &rzv2h_pwpr_pfc_lock_unlock, .pmc_writeb =3D &rzv2h_pmc_writeb, - .oen_read =3D &rzv2h_oen_read, - .oen_write =3D &rzv2h_oen_write, .hw_to_bias_param =3D &rzv2h_hw_to_bias_param, .bias_param_to_hw =3D &rzv2h_bias_param_to_hw, }; --=20 2.49.0 From nobody Tue Oct 7 13:28:35 2025 Received: from mail-wm1-f44.google.com (mail-wm1-f44.google.com [209.85.128.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C88612E9ECC; Wed, 9 Jul 2025 16:08:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.44 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752077320; cv=none; b=o1U5zA2XGO1JiD4SSu7qq8himg+u0rAyPN11mEpoKPi4pDnsed973DwL0imWABl+TCdHWJpSomWnrPlk9uxMaFlByXnKExucn9fQLOa/gKRm3ujddgNKjP0kZkB3NGUzmJIAVfWs0k4Jb2/zidmOzG2Wa4wui3ITwsLSCpaQlPk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752077320; c=relaxed/simple; bh=kZsMF9PH/uKNlzfxv3oC+i484V5rR03nkK+9vzngpu8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=NlgpqqmInD1X2Cr3I/yOFva96VmYP5qYsZpOqS+fulm/1GtLD0MxIIDVPHLLNLyhOP7LEDpuFOAmlFp1afXjYEADdLJMIejLFjX8Vo2Fh0nD2lkqtYhzw9sZdVXWgKXMELjmPlPQQ5hJOUOJ66t6gmHyzvZz69gt2uc1CaHSdhU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=kvATbaWH; arc=none smtp.client-ip=209.85.128.44 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="kvATbaWH" Received: by mail-wm1-f44.google.com with SMTP id 5b1f17b1804b1-4538a2fc7ffso8913265e9.0; Wed, 09 Jul 2025 09:08:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1752077317; x=1752682117; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=TQchwjWBmsVPFG1/hlspb5mC7Dl4wCOCwe3Vgy3tmEM=; b=kvATbaWHie67OsWuq73tM8S39dXkugloAVXuLHumeqj1oLjft36Zlo8OuySaxKJFuK rMAYCZWUnE83XKLF3behX9lBIuIfBHWQDFcOSgQIL+hXqXwhAz2TeXIDKZwabIYvunTF vPQZSWPDPoBkycnrGPIQLunrd/X6dHXy/W7iRw69V6IiY3z2H/CC+G/hstVqMuqrBY5T fyn+R+wBPGiOjlOa0uYsBv5LGkYAWVj0FuYke0sB589Affz6k1v2W/FmGo5Mghk8sEck HLkCf3la9ogbFvhymG0S+pfQGx4oziqMvNhPwVyRnAHRMdCqOZH/SpSpN/iOb8tHCgmC Kp9A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1752077317; x=1752682117; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TQchwjWBmsVPFG1/hlspb5mC7Dl4wCOCwe3Vgy3tmEM=; b=YO9uQhTuPtux1pEXBB0nnLwioliqGpT6ncsVYpc6xu2Dt6a2F6LgVWTA369Pue76kn kVzXkyt5Zc3ZKXk7AmZPlt5bdo1HfIlmo9f3mbNvATljc4k34toX7hwgKi+dvmEsWXH4 iDaqz4M9/4zUTo8JNcGnMIRXNC5WAMYYxdJnrKh0dgDhnax9gqW3RJewd73apBSIY9l2 plNcnCnydYW4OnBdgAcPrBo0eAxdEnreiH+seukOE66ulsprMHIm2DJbxx1oSYTUMavt rQxJwqt7/jHd7Lpwjjj9Bk9kmlzvnlPzPp4RyHyCdpZnFoFhq/CPuYU+i0VqPzfEZcoG n8Xg== X-Forwarded-Encrypted: i=1; AJvYcCWYWdTKXnke389P3WwUm0A2AWrkIF2Z5Sjxpkhe/ynwGTn34V5VQbIj0RDhbnaNYS1DaZJUEmTNgxE1@vger.kernel.org, AJvYcCWk4XlWvNq5YCWgrOA22VqQVy/QRoewZ5bG8miaIFe0DmVc2N2uY0WvSjVk0vlF+qPQieMME+NC9kpCU1Rl@vger.kernel.org X-Gm-Message-State: AOJu0YwMEyYkJms1J6TbW9ycFHClgHpuVdY/eARXmG5uHZDuEvfn+YV4 6o5ejzPAu+JZhPLlvuyXwSLqDn5v1dZltaSLycADMpFZKc3Wz58dkB1TzFx2Zw== X-Gm-Gg: ASbGncvF6+78ZCoGDojsmjxQi5uolQDXEBb7r6RM18o2tCaHc/mGWW6tuKmJ1UhfNmU IWhEo0AnoWKyBF/TgbnuLfsgINmm54zj7QxqkgZoc7aNFQul1P7aSJqiFYCijaIb8uisEzbPbZ8 0r/yRd2XTvBIDFQ+HSHINBllZjgdoRlOnvUfFwjlcA5bJttqAxFT5RSQg7OxTkhzmdfrvLjpqr3 ihqsZONg9rpQgDDBfJMck90IWAr/90J464uwOSOjzoIrXUxImzZPY4HeW+3HhUvtY2sWUmHGRTA q3QiazI+zeoSfbdO4mI6zBUl4zCbN3c/blfYyzwyojoRcI6+r4Pr4lAcL5zuE5vn6nIq0kysSd8 UeHBSObNL6Zo= X-Google-Smtp-Source: AGHT+IGSdDcm1ZajKQqWIe0FklxMr8IEmeu3LElppNvF1PKsdPHVfCstLjJeCRI6xfIuy2U9WFlcEA== X-Received: by 2002:a05:600c:3b93:b0:453:835a:db with SMTP id 5b1f17b1804b1-454db88f64bmr706375e9.4.1752077316934; Wed, 09 Jul 2025 09:08:36 -0700 (PDT) Received: from iku.Home ([2a06:5906:61b:2d00:c930:b02d:bf60:750b]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3b471b9671asm16639686f8f.53.2025.07.09.09.08.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Jul 2025 09:08:36 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Linus Walleij Cc: linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , John Madieu , Lad Prabhakar Subject: [PATCH v2 5/7] pinctrl: renesas: rzg2l: Unify OEN handling across RZ/{G2L,V2H,V2N} Date: Wed, 9 Jul 2025 17:08:17 +0100 Message-ID: <20250709160819.306875-6-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250709160819.306875-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250709160819.306875-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Unify the OEN handling on RZ/V2H(P) and RZ/V2N SoCs by reusing the existing rzg2l_read_oen and rzg2l_write_oen functions from RZ/G2L. Add a pin_to_oen_bit callback in rzg2l_pinctrl_data to look up per-pin OEN bit positions, and introduce an oen_pwpr_lock flag in the hwcfg to manage PWPR locking on SoCs that require it (RZ/V2H(P) family). Remove the hardcoded PFC_OEN define and obsolete per-SoC OEN helpers. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 62 ++++++++----------------- 1 file changed, 20 insertions(+), 42 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/rene= sas/pinctrl-rzg2l.c index cf0b92c661d9..64101423e1f3 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -146,7 +146,6 @@ #define SD_CH(off, ch) ((off) + (ch) * 4) #define ETH_POC(off, ch) ((off) + (ch) * 4) #define QSPI (0x3008) -#define PFC_OEN (0x3C40) /* known on RZ/V2H(P) only */ =20 #define PVDD_2500 2 /* I/O domain voltage 2.5V */ #define PVDD_1800 1 /* I/O domain voltage <=3D 1.8V */ @@ -258,6 +257,7 @@ enum rzg2l_iolh_index { * @func_base: base number for port function (see register PFC) * @oen_max_pin: the maximum pin number supporting output enable * @oen_max_port: the maximum port number supporting output enable + * @oen_pwpr_lock: flag indicating if the OEN register is locked by PWPR */ struct rzg2l_hwcfg { const struct rzg2l_register_offsets regs; @@ -270,6 +270,7 @@ struct rzg2l_hwcfg { u8 func_base; u8 oen_max_pin; u8 oen_max_port; + bool oen_pwpr_lock; }; =20 struct rzg2l_dedicated_configs { @@ -1082,10 +1083,11 @@ static u32 rzg2l_read_oen(struct rzg2l_pinctrl *pct= rl, unsigned int _pin) =20 static int rzg2l_write_oen(struct rzg2l_pinctrl *pctrl, unsigned int _pin,= u8 oen) { + const struct rzg2l_register_offsets *regs =3D &pctrl->data->hwcfg->regs; u16 oen_offset =3D pctrl->data->hwcfg->regs.oen; unsigned long flags; + u8 val, pwpr; int bit; - u8 val; =20 if (!pctrl->data->pin_to_oen_bit) return -EINVAL; @@ -1099,7 +1101,13 @@ static int rzg2l_write_oen(struct rzg2l_pinctrl *pct= rl, unsigned int _pin, u8 oe val &=3D ~BIT(bit); else val |=3D BIT(bit); + if (pctrl->data->hwcfg->oen_pwpr_lock) { + pwpr =3D readb(pctrl->base + regs->pwpr); + writeb(pwpr | PWPR_REGWE_B, pctrl->base + regs->pwpr); + } writeb(val, pctrl->base + oen_offset); + if (pctrl->data->hwcfg->oen_pwpr_lock) + writeb(pwpr & ~PWPR_REGWE_B, pctrl->base + regs->pwpr); spin_unlock_irqrestore(&pctrl->lock, flags); =20 return 0; @@ -1190,7 +1198,7 @@ static int rzv2h_bias_param_to_hw(enum pin_config_par= am param) return -EINVAL; } =20 -static u8 rzv2h_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int _= pin) +static int rzv2h_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int = _pin) { static const char * const pin_names[] =3D { "ET0_TXC_TXCLK", "ET1_TXC_TXC= LK", "XSPI0_RESET0N", "XSPI0_CS0N", @@ -1204,41 +1212,7 @@ static u8 rzv2h_pin_to_oen_bit(struct rzg2l_pinctrl = *pctrl, unsigned int _pin) } =20 /* Should not happen. */ - return 0; -} - -static u32 rzv2h_oen_read(struct rzg2l_pinctrl *pctrl, unsigned int _pin) -{ - u8 bit; - - bit =3D rzv2h_pin_to_oen_bit(pctrl, _pin); - - return !(readb(pctrl->base + PFC_OEN) & BIT(bit)); -} - -static int rzv2h_oen_write(struct rzg2l_pinctrl *pctrl, unsigned int _pin,= u8 oen) -{ - const struct rzg2l_hwcfg *hwcfg =3D pctrl->data->hwcfg; - const struct rzg2l_register_offsets *regs =3D &hwcfg->regs; - unsigned long flags; - u8 val, bit; - u8 pwpr; - - bit =3D rzv2h_pin_to_oen_bit(pctrl, _pin); - spin_lock_irqsave(&pctrl->lock, flags); - val =3D readb(pctrl->base + PFC_OEN); - if (oen) - val &=3D ~BIT(bit); - else - val |=3D BIT(bit); - - pwpr =3D readb(pctrl->base + regs->pwpr); - writeb(pwpr | PWPR_REGWE_B, pctrl->base + regs->pwpr); - writeb(val, pctrl->base + PFC_OEN); - writeb(pwpr & ~PWPR_REGWE_B, pctrl->base + regs->pwpr); - spin_unlock_irqrestore(&pctrl->lock, flags); - - return 0; + return -EINVAL; } =20 static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, @@ -3263,8 +3237,10 @@ static const struct rzg2l_hwcfg rzg3s_hwcfg =3D { static const struct rzg2l_hwcfg rzv2h_hwcfg =3D { .regs =3D { .pwpr =3D 0x3c04, + .oen =3D 0x3c40, }, .tint_start_index =3D 17, + .oen_pwpr_lock =3D true, }; =20 static struct rzg2l_pinctrl_data r9a07g043_data =3D { @@ -3361,8 +3337,9 @@ static struct rzg2l_pinctrl_data r9a09g056_data =3D { #endif .pwpr_pfc_lock_unlock =3D &rzv2h_pwpr_pfc_lock_unlock, .pmc_writeb =3D &rzv2h_pmc_writeb, - .oen_read =3D &rzv2h_oen_read, - .oen_write =3D &rzv2h_oen_write, + .pin_to_oen_bit =3D &rzv2h_pin_to_oen_bit, + .oen_read =3D &rzg2l_read_oen, + .oen_write =3D &rzg2l_write_oen, .hw_to_bias_param =3D &rzv2h_hw_to_bias_param, .bias_param_to_hw =3D &rzv2h_bias_param_to_hw, }; @@ -3385,8 +3362,9 @@ static struct rzg2l_pinctrl_data r9a09g057_data =3D { #endif .pwpr_pfc_lock_unlock =3D &rzv2h_pwpr_pfc_lock_unlock, .pmc_writeb =3D &rzv2h_pmc_writeb, - .oen_read =3D &rzv2h_oen_read, - .oen_write =3D &rzv2h_oen_write, + .pin_to_oen_bit =3D &rzv2h_pin_to_oen_bit, + .oen_read =3D &rzg2l_read_oen, + .oen_write =3D &rzg2l_write_oen, .hw_to_bias_param =3D &rzv2h_hw_to_bias_param, .bias_param_to_hw =3D &rzv2h_bias_param_to_hw, }; --=20 2.49.0 From nobody Tue Oct 7 13:28:35 2025 Received: from mail-wr1-f43.google.com (mail-wr1-f43.google.com [209.85.221.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BFE142EA161; Wed, 9 Jul 2025 16:08:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.43 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752077321; cv=none; b=IleiwGgupLcwq52mQXntfwrvQFcEMkHEfzVmTCrF9B1dWA4/7VS4gvP6l03o3qDdleLZk7FjbrL6gepwKPXpOT6wsfGMfFn8cBbp7AGkJy4ldEXV9oVxwvlG5IAlhGS+ZKTmcF5dUSd1PkYsiteLko3KkyBFwr25zWjTXNzzbYI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752077321; c=relaxed/simple; bh=cmS8OaxXs07rdRkZmeuQ8U2/HjwTz+q7p3ytpa5Nz10=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Jrr2p76r/fyNz6h1F1P3IRdrdJaM0Hc+MZCjxu2OV99bQFAD1Bq/4NcJdbFwdWkr+cxnm8wwx0ficwA0cPG7JwrzOtUzvlktHPGaj1YLvP0a4UJLV9DIeOvjaI7EOPRLw1auII7X0xzKHIDooEVHN8tZ2D6DFCfaK1zU/OBr+ZY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=PX2Wc2Ud; arc=none smtp.client-ip=209.85.221.43 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="PX2Wc2Ud" Received: by mail-wr1-f43.google.com with SMTP id ffacd0b85a97d-3a536ecbf6fso81566f8f.2; Wed, 09 Jul 2025 09:08:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1752077318; x=1752682118; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=225/uGLq7GzKmveCG3TTIRsj6STqcgVffZebkZov6Dg=; b=PX2Wc2Udo4d2rmrp+svbHAsdvsMX8wmENbbh5R9LSwcjbbsGevPg7Ii/222aJsm1ui tlY2bjJZE2WXYaKn4giqmldoZEOE1MkD0fYQwCRhc4N6rTpnrPcjkKVT1wH4ED0do9Aq TXzNK2aA/qNjZ97W0mMxLKjp5gid8s2bF/xrxOR/RMojay3fmzI1+yzflZ947NZo2Jpw Q0eRdgrTxTlGVKVoW8pgpj+8TJiaJ+5ljxqIefM4p8dzCYXzmeZ7BzL0YRjS9t1rHcqw 9C3LtVxLMoqabY4cKlYjo4nVwY6PtiDPScREsHMNDDW01bT3Jy/BuRHtsvufsE8vN6RB SJxQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1752077318; x=1752682118; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=225/uGLq7GzKmveCG3TTIRsj6STqcgVffZebkZov6Dg=; b=ndPVfpapitZYBFYxw+HBBBEUrOucUqS8rkAe5E/1PFhpSPuOWqnQn14rOsM8vssqF9 r0BJ7dEa8HKmnzD9CQV4qQhNTkmO8BYvFv2bliEVDtU5y096bFWWp4202bDXQhHdvASG KBnUulbWghJrQLKvk+fKCV6SWaadbHxtAiK7/WIrx9je2Qe3tQ8TI+YxOV8ybijbKFht Lj2aGAW7lvkvbGm5R6ospDRm/lAkckCGghw8N0Yzv7Cg18vDuTLTdCrNUJnxQgbD9gIU ekYMAqqhKu+p3gUoVAkFdcRD5uzMWQBjM2cOEqIkJaxf22lbPpHzaEs9oNdNp6xos+HY 1V4Q== X-Forwarded-Encrypted: i=1; AJvYcCWFA3H4DRsDkSFArVDTC+SvIfjyRVTJKPCDnyws5XmvtyEGc7jnUpuMfzhKW6bWC7Wyx80neK0QwVLI@vger.kernel.org, AJvYcCXK/2EDBBPXC8ksPNNUxnb2T9uU85/mUjwb/O6aSYh150gWGdUzRBLpO8G01OF4DaXp88zv4S5K11US9ou0@vger.kernel.org X-Gm-Message-State: AOJu0Yy0KVvfS6STCN3xsga5MPr1OnThP4GFhmIR8B6ox94e/DoOBYtT jyC4fEjSVVQirkLO9oqDLJbZ57kGjmOBk5ruKpZifKrNKnPjNNAr8uzbsMCVSA== X-Gm-Gg: ASbGncsBIqQW3vgEa18x4YT9JH7jbk8yAXUHgS109FZVqX7JpoOOiYqixqumcsqYHfK RyaL5j8cd33azT7wNWRN/sUN6FPspQNnE7ngwBz3mbkNG1k0gk3WJOJF8iPN8Iv7MZYdo7HD3QG 9z4Ojnv83FWqr+z/rlyTB+9w/6pEdxiXLcn8ykoaFoF5yLLjH/JiLACS4gwjOli9BmwL6Si03m2 rcz+8dWJ73J98QmiDGma64ATJbg+zxX4ykYUXgsupg/tR10CljswmJOvFCSf4/cqTX7tUpNj37T 6oRAnUQp/fX7IQ29B95oCjwgjas0ZATafqCw0pvhEo8BfZMEAd6b8sflaIX85E5sTT1SvDc96P4 cdyWli1OdrKY= X-Google-Smtp-Source: AGHT+IFKLcwT+CBGTaJ3oDmL5xoPc1mmbppX8EoIu052AkLuXIjcYIHQdmOYgMMscSAVWz4AlnsThw== X-Received: by 2002:a05:6000:144e:b0:3b3:9cc4:6830 with SMTP id ffacd0b85a97d-3b5e453e217mr2843727f8f.48.1752077317689; Wed, 09 Jul 2025 09:08:37 -0700 (PDT) Received: from iku.Home ([2a06:5906:61b:2d00:c930:b02d:bf60:750b]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3b471b9671asm16639686f8f.53.2025.07.09.09.08.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Jul 2025 09:08:37 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Linus Walleij Cc: linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , John Madieu , Lad Prabhakar Subject: [PATCH v2 6/7] pinctrl: renesas: rzg2l: Add PFC_OEN support for RZ/G3E SoC Date: Wed, 9 Jul 2025 17:08:18 +0100 Message-ID: <20250709160819.306875-7-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250709160819.306875-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250709160819.306875-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Add support for configuring the PFC_OEN register on the RZ/G3E SoC to enable output-enable control for specific pins. On this SoC, certain pins such as TXC_TXCLK need to support switching between input and output modes depending on the PHY interface mode (e.g., MII vs RGMII). This functionality maps to the 'output-enable' property in the device tree and requires explicit control via the PFC_OEN register. This change updates the r9a09g047_variable_pin_cfg array to mark PB1, PE1, PL0, PL1, PL2, and PL4 with the PIN_CFG_OEN flag to indicate output-enable support. A new helper, rzg3e_pin_to_oen_bit(), is introduced to map these pin names to their respective OEN bit positions, and the corresponding callbacks are wired into the RZ/G3E SoC configuration using the generic rzg2l_read_oen() and rzg2l_write_oen() accessors. Additionally, the GPIO configuration for the PB, PE, and PL ports is updated to use the variable port pack macro, enabling per-pin configuration necessary for OEN handling. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 61 +++++++++++++++++++++---- 1 file changed, 52 insertions(+), 9 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/rene= sas/pinctrl-rzg2l.c index 64101423e1f3..a6580d06db13 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -397,6 +397,14 @@ static const u64 r9a09g047_variable_pin_cfg[] =3D { RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 5, RZV2H_MPXED_PIN_FUNCS), RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 6, RZV2H_MPXED_PIN_FUNCS), RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 7, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PB, 0, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PB, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_= OEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PB, 2, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PB, 3, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PB, 4, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PB, 5, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PB, 6, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PB, 7, RZV2H_MPXED_PIN_FUNCS), RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 0, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_= IEN), RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 1, RZV2H_MPXED_PIN_FUNCS), RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 2, RZV2H_MPXED_PIN_FUNCS), @@ -405,6 +413,14 @@ static const u64 r9a09g047_variable_pin_cfg[] =3D { RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 5, RZV2H_MPXED_PIN_FUNCS), RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 6, RZV2H_MPXED_PIN_FUNCS), RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PD, 7, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PE, 0, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PE, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_= OEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PE, 2, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PE, 3, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PE, 4, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PE, 5, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PE, 6, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PE, 7, RZV2H_MPXED_PIN_FUNCS), RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 0, RZV2H_MPXED_PIN_FUNCS), RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_= IEN), RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PG, 2, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_= IEN), @@ -424,6 +440,14 @@ static const u64 r9a09g047_variable_pin_cfg[] =3D { RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PJ, 2, RZV2H_MPXED_PIN_FUNCS), RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PJ, 3, RZV2H_MPXED_PIN_FUNCS), RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PJ, 4, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PL, 0, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_= OEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PL, 1, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_= OEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PL, 2, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_= OEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PL, 3, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PL, 4, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_= OEN), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PL, 5, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PL, 6, RZV2H_MPXED_PIN_FUNCS), + RZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PL, 7, RZV2H_MPXED_PIN_FUNCS), }; =20 static const u64 r9a09g057_variable_pin_cfg[] =3D { @@ -1198,23 +1222,39 @@ static int rzv2h_bias_param_to_hw(enum pin_config_p= aram param) return -EINVAL; } =20 -static int rzv2h_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int = _pin) +static int rzg2l_pin_names_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigne= d int _pin, + const char * const pin_names[], unsigned int count) { - static const char * const pin_names[] =3D { "ET0_TXC_TXCLK", "ET1_TXC_TXC= LK", - "XSPI0_RESET0N", "XSPI0_CS0N", - "XSPI0_CKN", "XSPI0_CKP" }; const struct pinctrl_pin_desc *pin_desc =3D &pctrl->desc.pins[_pin]; unsigned int i; =20 - for (i =3D 0; i < ARRAY_SIZE(pin_names); i++) { + for (i =3D 0; i < count; i++) { if (!strcmp(pin_desc->name, pin_names[i])) return i; } =20 - /* Should not happen. */ return -EINVAL; } =20 +static int rzv2h_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int = _pin) +{ + static const char * const pin_names[] =3D { + "ET0_TXC_TXCLK", "ET1_TXC_TXCLK", "XSPI0_RESET0N", + "XSPI0_CS0N", "XSPI0_CKN", "XSPI0_CKP" + }; + + return rzg2l_pin_names_to_oen_bit(pctrl, _pin, pin_names, ARRAY_SIZE(pin_= names)); +} + +static int rzg3e_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, unsigned int = _pin) +{ + static const char * const pin_names[] =3D { + "PB1", "PE1", "PL4", "PL1", "PL2", "PL0" + }; + + return rzg2l_pin_names_to_oen_bit(pctrl, _pin, pin_names, ARRAY_SIZE(pin_= names)); +} + static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, unsigned int _pin, unsigned long *config) @@ -2006,17 +2046,17 @@ static const u64 r9a09g047_gpio_configs[] =3D { RZG2L_GPIO_PORT_PACK(6, 0x28, RZV2H_MPXED_PIN_FUNCS), /* P8 */ 0x0, RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x2a), /* PA */ - RZG2L_GPIO_PORT_PACK(8, 0x2b, RZV2H_MPXED_PIN_FUNCS), /* PB */ + RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x2b), /* PB */ RZG2L_GPIO_PORT_PACK(3, 0x2c, RZV2H_MPXED_PIN_FUNCS), /* PC */ RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x2d), /* PD */ - RZG2L_GPIO_PORT_PACK(8, 0x2e, RZV2H_MPXED_PIN_FUNCS), /* PE */ + RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x2e), /* PE */ RZG2L_GPIO_PORT_PACK(3, 0x2f, RZV2H_MPXED_PIN_FUNCS), /* PF */ RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x30), /* PG */ RZG2L_GPIO_PORT_PACK_VARIABLE(6, 0x31), /* PH */ 0x0, RZG2L_GPIO_PORT_PACK_VARIABLE(5, 0x33), /* PJ */ RZG2L_GPIO_PORT_PACK(4, 0x34, RZV2H_MPXED_PIN_FUNCS), /* PK */ - RZG2L_GPIO_PORT_PACK(8, 0x35, RZV2H_MPXED_PIN_FUNCS), /* PL */ + RZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x35), /* PL */ RZG2L_GPIO_PORT_PACK(8, 0x36, RZV2H_MPXED_PIN_FUNCS), /* PM */ 0x0, 0x0, @@ -3316,6 +3356,9 @@ static struct rzg2l_pinctrl_data r9a09g047_data =3D { #endif .pwpr_pfc_lock_unlock =3D &rzv2h_pwpr_pfc_lock_unlock, .pmc_writeb =3D &rzv2h_pmc_writeb, + .pin_to_oen_bit =3D &rzg3e_pin_to_oen_bit, + .oen_read =3D &rzg2l_read_oen, + .oen_write =3D &rzg2l_write_oen, .hw_to_bias_param =3D &rzv2h_hw_to_bias_param, .bias_param_to_hw =3D &rzv2h_bias_param_to_hw, }; --=20 2.49.0 From nobody Tue Oct 7 13:28:35 2025 Received: from mail-wm1-f48.google.com (mail-wm1-f48.google.com [209.85.128.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8625D2EA469; Wed, 9 Jul 2025 16:08:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752077322; cv=none; b=dVOliYOy6HfjgvOYgI0H0tmtsYMLK2lHm+tl8j5BLWLA1Do8KxoreevvdIdQuqmRMJPTsTXErrt4WqHNl3HuWFdeZnDScIf6OOSPTEL1FdLjmDJ3mNp01L+Ha/I3WpGLWOWIYyQpQZ7qQCyMagxInVN5WKhYohPhxdcNWI2Ft7A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752077322; c=relaxed/simple; bh=3KtpilEy3/o3/1qg2G5TextcJcows1HYN0ngbhiNMHI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=P+Gum9ecHhM+N3evjHsLFPpCtTR4C6e+md1pdzsuvdMVdu4BWzkhzm8gmF0yZfBy6zUS7wDTd3tF/eUfKh0x0CkILpadRRXrT6WT5xUo/ZtDdb3i6Bui0qXPsUk/j09QffFMG/uddW7XgOiLFB2gaFvHzqtZsunJbLGW7zGmo6Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=EI/epiSF; arc=none smtp.client-ip=209.85.128.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="EI/epiSF" Received: by mail-wm1-f48.google.com with SMTP id 5b1f17b1804b1-450cb2ddd46so121015e9.2; Wed, 09 Jul 2025 09:08:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1752077319; x=1752682119; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=JyfdpRD0W+iXSmWBFAIa4vA9j53BOrWnzXp955ltOb0=; b=EI/epiSFtcAS2inH3pSyyyZN7u4oJ0WxUs7cY5O/v38BuC43qZhTwanOFCS/7yh5vZ zBSA5bT2GnfQ/BP6q34f0zwgOaPjBsJMVknD486rnu7pi3V2a1lllcmEIgc8ID05i5jn xirH/tFOxxCyv+QEiqpNnH5WIk5RA2SM2Vmxad/ZVvj/drUdiIAt2B3S9Kdt4VDVxndC 5d+ThXGPNBQTHMUBY5C/EVNOTjgx6a7i2JOFT71VtC/KVY9AR5sm4YQNbhq4MW9TYRnj 3OiQ6nqUUlEKuxbUN0tzmqtdqdJPp8xm9yGd9Jzq2LV0rHnYubguIk864iYDkyJNqEPK ubyg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1752077319; x=1752682119; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JyfdpRD0W+iXSmWBFAIa4vA9j53BOrWnzXp955ltOb0=; b=UuD/oYh0aQgEvfBO9kj0M8wDTotmP4UD9P3EiOodzIetmWhCwdaGKnoKonYPcDRHKn UnZ8veFVXbf+IIlzjuYbo295O89wMx/hVvn9/TQ2KX8rMzlRXHx4qrs4FhrFBwE1EXe1 qvYAAIKtQjOfCmgNDf6GyU6bMxhpKbLuq+lWIh41+ccThrfd6tXj6DUAN4ohuBzAC6HA zzwlc2rHlVecAIVci2usOF8dI4Qsp6ya3AnghZaobsyu4PvogkKGbOCBgbEzL61ELl2u SzzpgTUnv9HvIwhKEjeTBabZ58prx7CE0ZTwSUdzmCrFGLTJinTBK+VAzWRHs6ZETV8S yn0Q== X-Forwarded-Encrypted: i=1; AJvYcCV2Z4CuBzMAbP2oxoXCVHfJRf8DX+xwsOqB2gXmHgJ1rqe6OGOxWwaYb4SPE+NnJNv/2e+xpixjEi90@vger.kernel.org, AJvYcCV5R9ivjJkXYLTkcu2ZYWZvc5fD+vDY3GTSOB72pAMgzICmtBQd1MnGoSYYehUzuhdLjLwZ4wRyd9ejyLdn@vger.kernel.org X-Gm-Message-State: AOJu0YwUQyh9IeyAEnEa41BxKTI7/A4BLdC8R0yx9LCECm9dq7UOEuo0 uco0V51s7A/o8mgIlNH7Nr/n7DnmZXf9W8ZndEvUy8ba1Hw87g34aLjQ X-Gm-Gg: ASbGncs4AQHel8QlggfET5utaS3CskpBvLZO9YlbAjc3HQvnoLm6eDY1k1g0PgeWb9J krJFnRO0IPZTAcLUGm9fEC9n/NXTgEGOoRR5id8Xqj8TPoSCA+FFRpWBqsiYTeb6fbwEXjtgNuO adOgBEFgGvEb2DQj45qeSwjtL/DE/xpjRwxBCyp7mTMmps92z6gc2POuZ+iMSjRA5JNIf5mQxyv z/zEsa3EU20WfAoumM9kObj1DdAOkYICtDdOdovEB3PO6Fb1SkIieyiV6Med3uznyzf9ZDYx2oV jym3DnUitqhnJZamt7YgvJvS8AK9iCJHQVefFothjWD5Q+12dyvRhj/1lLg3gEQkK4Gj+aDBCgK eMFsZfcXlOBY= X-Google-Smtp-Source: AGHT+IGEjHlJDStNIwkP8Oi9/D+SsbtVZvx4kJ2veVBMXoB0Q5ZWeA/es6NJMmXbS3ixTLrrN6MvNQ== X-Received: by 2002:a05:6000:2891:b0:3a3:6e62:d8e8 with SMTP id ffacd0b85a97d-3b5e454564emr3083059f8f.55.1752077318496; Wed, 09 Jul 2025 09:08:38 -0700 (PDT) Received: from iku.Home ([2a06:5906:61b:2d00:c930:b02d:bf60:750b]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3b471b9671asm16639686f8f.53.2025.07.09.09.08.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Jul 2025 09:08:37 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Linus Walleij Cc: linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , John Madieu , Lad Prabhakar Subject: [PATCH v2 7/7] pinctrl: renesas: rzg2l: Drop oen_read and oen_write callbacks Date: Wed, 9 Jul 2025 17:08:19 +0100 Message-ID: <20250709160819.306875-8-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250709160819.306875-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250709160819.306875-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Remove oen_read and oen_write callbacks from rzg2l_pinctrl_data as all SoCs now use the same rzg2l_read_oen() and rzg2l_write_oen() functions directly. Change rzg2l_read_oen() return type to int for proper error reporting and update callers to handle errors consistently. This simplifies the code by removing redundant callbacks and ensures uniform OEN handling across all supported SoCs. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 35 +++++++------------------ 1 file changed, 9 insertions(+), 26 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/rene= sas/pinctrl-rzg2l.c index a6580d06db13..1e4fc4be6713 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -298,8 +298,6 @@ struct rzg2l_pinctrl_data { void (*pwpr_pfc_lock_unlock)(struct rzg2l_pinctrl *pctrl, bool lock); void (*pmc_writeb)(struct rzg2l_pinctrl *pctrl, u8 val, u16 offset); int (*pin_to_oen_bit)(struct rzg2l_pinctrl *pctrl, unsigned int _pin); - u32 (*oen_read)(struct rzg2l_pinctrl *pctrl, unsigned int _pin); - int (*oen_write)(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen); int (*hw_to_bias_param)(unsigned int val); int (*bias_param_to_hw)(enum pin_config_param param); }; @@ -1092,15 +1090,15 @@ static int rzg2l_pin_to_oen_bit(struct rzg2l_pinctr= l *pctrl, unsigned int _pin) return -EINVAL; } =20 -static u32 rzg2l_read_oen(struct rzg2l_pinctrl *pctrl, unsigned int _pin) +static int rzg2l_read_oen(struct rzg2l_pinctrl *pctrl, unsigned int _pin) { int bit; =20 if (!pctrl->data->pin_to_oen_bit) - return 0; + return -EOPNOTSUPP; bit =3D pctrl->data->pin_to_oen_bit(pctrl, _pin); if (bit < 0) - return 0; + return -EINVAL; =20 return !(readb(pctrl->base + pctrl->data->hwcfg->regs.oen) & BIT(bit)); } @@ -1114,7 +1112,7 @@ static int rzg2l_write_oen(struct rzg2l_pinctrl *pctr= l, unsigned int _pin, u8 oe int bit; =20 if (!pctrl->data->pin_to_oen_bit) - return -EINVAL; + return -EOPNOTSUPP; bit =3D pctrl->data->pin_to_oen_bit(pctrl, _pin); if (bit < 0) return -EINVAL; @@ -1296,11 +1294,10 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl= _dev *pctldev, case PIN_CONFIG_OUTPUT_ENABLE: if (!(cfg & PIN_CFG_OEN)) return -EINVAL; - if (!pctrl->data->oen_read) - return -EOPNOTSUPP; - arg =3D pctrl->data->oen_read(pctrl, _pin); - if (!arg) - return -EINVAL; + ret =3D rzg2l_read_oen(pctrl, _pin); + if (ret < 0) + return ret; + arg =3D ret; break; =20 case PIN_CONFIG_POWER_SOURCE: @@ -1459,9 +1456,7 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_d= ev *pctldev, case PIN_CONFIG_OUTPUT_ENABLE: if (!(cfg & PIN_CFG_OEN)) return -EINVAL; - if (!pctrl->data->oen_write) - return -EOPNOTSUPP; - ret =3D pctrl->data->oen_write(pctrl, _pin, !!arg); + ret =3D rzg2l_write_oen(pctrl, _pin, !!arg); if (ret) return ret; break; @@ -3298,8 +3293,6 @@ static struct rzg2l_pinctrl_data r9a07g043_data =3D { .pwpr_pfc_lock_unlock =3D &rzg2l_pwpr_pfc_lock_unlock, .pmc_writeb =3D &rzg2l_pmc_writeb, .pin_to_oen_bit =3D &rzg2l_pin_to_oen_bit, - .oen_read =3D &rzg2l_read_oen, - .oen_write =3D &rzg2l_write_oen, .hw_to_bias_param =3D &rzg2l_hw_to_bias_param, .bias_param_to_hw =3D &rzg2l_bias_param_to_hw, }; @@ -3316,8 +3309,6 @@ static struct rzg2l_pinctrl_data r9a07g044_data =3D { .pwpr_pfc_lock_unlock =3D &rzg2l_pwpr_pfc_lock_unlock, .pmc_writeb =3D &rzg2l_pmc_writeb, .pin_to_oen_bit =3D &rzg2l_pin_to_oen_bit, - .oen_read =3D &rzg2l_read_oen, - .oen_write =3D &rzg2l_write_oen, .hw_to_bias_param =3D &rzg2l_hw_to_bias_param, .bias_param_to_hw =3D &rzg2l_bias_param_to_hw, }; @@ -3333,8 +3324,6 @@ static struct rzg2l_pinctrl_data r9a08g045_data =3D { .pwpr_pfc_lock_unlock =3D &rzg2l_pwpr_pfc_lock_unlock, .pmc_writeb =3D &rzg2l_pmc_writeb, .pin_to_oen_bit =3D &rzg3s_pin_to_oen_bit, - .oen_read =3D &rzg2l_read_oen, - .oen_write =3D &rzg2l_write_oen, .hw_to_bias_param =3D &rzg2l_hw_to_bias_param, .bias_param_to_hw =3D &rzg2l_bias_param_to_hw, }; @@ -3357,8 +3346,6 @@ static struct rzg2l_pinctrl_data r9a09g047_data =3D { .pwpr_pfc_lock_unlock =3D &rzv2h_pwpr_pfc_lock_unlock, .pmc_writeb =3D &rzv2h_pmc_writeb, .pin_to_oen_bit =3D &rzg3e_pin_to_oen_bit, - .oen_read =3D &rzg2l_read_oen, - .oen_write =3D &rzg2l_write_oen, .hw_to_bias_param =3D &rzv2h_hw_to_bias_param, .bias_param_to_hw =3D &rzv2h_bias_param_to_hw, }; @@ -3381,8 +3368,6 @@ static struct rzg2l_pinctrl_data r9a09g056_data =3D { .pwpr_pfc_lock_unlock =3D &rzv2h_pwpr_pfc_lock_unlock, .pmc_writeb =3D &rzv2h_pmc_writeb, .pin_to_oen_bit =3D &rzv2h_pin_to_oen_bit, - .oen_read =3D &rzg2l_read_oen, - .oen_write =3D &rzg2l_write_oen, .hw_to_bias_param =3D &rzv2h_hw_to_bias_param, .bias_param_to_hw =3D &rzv2h_bias_param_to_hw, }; @@ -3406,8 +3391,6 @@ static struct rzg2l_pinctrl_data r9a09g057_data =3D { .pwpr_pfc_lock_unlock =3D &rzv2h_pwpr_pfc_lock_unlock, .pmc_writeb =3D &rzv2h_pmc_writeb, .pin_to_oen_bit =3D &rzv2h_pin_to_oen_bit, - .oen_read =3D &rzg2l_read_oen, - .oen_write =3D &rzg2l_write_oen, .hw_to_bias_param =3D &rzv2h_hw_to_bias_param, .bias_param_to_hw =3D &rzv2h_bias_param_to_hw, }; --=20 2.49.0