From nobody Tue Oct 7 13:08:06 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ED78C2E8E10; Wed, 9 Jul 2025 15:53:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752076427; cv=none; b=GVcF0V3LDAgh82OxoLr0wyYtIpnLM8J0Tuk/uJBD4rAKG6B+dRRJnRtS3oAQTZxYkN8+OAJeK4A3mm1suQ0AbVaUMvgrSejEbg5PSiP+Z1dOs1r0ZmNh03b3rfLDZ0htP9tE0cM+QfmQwjTfWgX+EWMC/6boDT61ZiPQ6DPrOLc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752076427; c=relaxed/simple; bh=7Wbq7YVdQYBRh6HqmuZ0nMrzeWobJHu0jczoLtBCBC8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=nuRXdgWrr8SuLgosKWtVrjCRn94B9LltxC9YUiLNgWG/75fVAX6Nchjp3sgy35Whe2PazDL7JXUp364FFU4jZZcI2ZdaEcbziD8UqorO5Oxdz5oZsUau3O5VfRvZ1SrmixnlvH7CHn6yIWTnABDDrKGZM2I6/A0vMdFq2wU2dFk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ho/KmTGG; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ho/KmTGG" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 710B9C4AF0B; Wed, 9 Jul 2025 15:53:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1752076426; bh=7Wbq7YVdQYBRh6HqmuZ0nMrzeWobJHu0jczoLtBCBC8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ho/KmTGG+BEj8Z3EAJH+upQ5rpbS3W1yyfhGSC/VrkauLBphKHQ4pHT9VNoV7oGFo DkLp0MplaNZO8dfHh+nRJGpy4Ok0MXbyRe+/5wkVs8bVMNjM7Wsn0I/7AxRQiRx9jE pc6j4dGoCNCbZHttHmR9PCmFa7Oz/qo0DejqbqOEDbj2nkBxr67iDHVGliwAqlEBz6 ydlovTSIXcEwofYOKaAuCH97Os9AlCWHDmZfSai6/u9Jxbzhv4TW8fEFI7vRidkLpO oHZPzrnaABoha9Vo675Bgb53dYaU6nQcpVWzuVsJh8hi74N2AKHEXcW6ZrauMWqLaR lFoIPVybXp+Gw== Received: by wens.tw (Postfix, from userid 1000) id 36E955FBBD; Wed, 9 Jul 2025 23:53:44 +0800 (CST) From: Chen-Yu Tsai To: Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-sunxi@lists.linux.dev, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Andre Przywara Subject: [PATCH v2 1/4] dt-bindings: power: Add A523 PPU and PCK600 power controllers Date: Wed, 9 Jul 2025 23:53:40 +0800 Message-Id: <20250709155343.3765227-2-wens@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250709155343.3765227-1-wens@kernel.org> References: <20250709155343.3765227-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen-Yu Tsai The A523 PPU is likely the same kind of hardware seen on previous SoCs. The A523 PCK600, as the name suggests, is likely a customized version of ARM's PCK-600 power controller. Comparing the BSP driver against ARM's PPU datasheet shows that the basic registers line up, but Allwinner's hardware has some additional delay controls in the reserved register range. As such it is likely not fully compatible with the standard ARM version. Document A523 PPU and PCK600 compatibles. Also reorder the compatible string entries so they are grouped and ordered by family first, then by SoC model. Reviewed-by: Andre Przywara Signed-off-by: Chen-Yu Tsai Reviewed-by: Rob Herring (Arm) --- Changes since v1: - Re-order compatible string entries - Fix name of header file to match compatible string --- .../bindings/power/allwinner,sun20i-d1-ppu.yaml | 4 +++- .../power/allwinner,sun55i-a523-pck-600.h | 15 +++++++++++++++ .../dt-bindings/power/allwinner,sun55i-a523-ppu.h | 12 ++++++++++++ 3 files changed, 30 insertions(+), 1 deletion(-) create mode 100644 include/dt-bindings/power/allwinner,sun55i-a523-pck-600= .h create mode 100644 include/dt-bindings/power/allwinner,sun55i-a523-ppu.h diff --git a/Documentation/devicetree/bindings/power/allwinner,sun20i-d1-pp= u.yaml b/Documentation/devicetree/bindings/power/allwinner,sun20i-d1-ppu.ya= ml index f578be6a3bc8..a28e75a9cb6a 100644 --- a/Documentation/devicetree/bindings/power/allwinner,sun20i-d1-ppu.yaml +++ b/Documentation/devicetree/bindings/power/allwinner,sun20i-d1-ppu.yaml @@ -16,8 +16,10 @@ description: properties: compatible: enum: - - allwinner,sun20i-d1-ppu - allwinner,sun8i-v853-ppu + - allwinner,sun20i-d1-ppu + - allwinner,sun55i-a523-pck-600 + - allwinner,sun55i-a523-ppu =20 reg: maxItems: 1 diff --git a/include/dt-bindings/power/allwinner,sun55i-a523-pck-600.h b/in= clude/dt-bindings/power/allwinner,sun55i-a523-pck-600.h new file mode 100644 index 000000000000..6b3d8ea7bb69 --- /dev/null +++ b/include/dt-bindings/power/allwinner,sun55i-a523-pck-600.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_POWER_SUN55I_A523_PCK600_H_ +#define _DT_BINDINGS_POWER_SUN55I_A523_PCK600_H_ + +#define PD_VE 0 +#define PD_GPU 1 +#define PD_VI 2 +#define PD_VO0 3 +#define PD_VO1 4 +#define PD_DE 5 +#define PD_NAND 6 +#define PD_PCIE 7 + +#endif /* _DT_BINDINGS_POWER_SUN55I_A523_PCK600_H_ */ diff --git a/include/dt-bindings/power/allwinner,sun55i-a523-ppu.h b/includ= e/dt-bindings/power/allwinner,sun55i-a523-ppu.h new file mode 100644 index 000000000000..bc9aba73c19a --- /dev/null +++ b/include/dt-bindings/power/allwinner,sun55i-a523-ppu.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_POWER_SUN55I_A523_PPU_H_ +#define _DT_BINDINGS_POWER_SUN55I_A523_PPU_H_ + +#define PD_DSP 0 +#define PD_NPU 1 +#define PD_AUDIO 2 +#define PD_SRAM 3 +#define PD_RISCV 4 + +#endif /* _DT_BINDINGS_POWER_SUN55I_A523_PPU_H_ */ --=20 2.39.5 From nobody Tue Oct 7 13:08:06 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ED6BC28EBFE; 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charset="utf-8" From: Chen-Yu Tsai A523 has a PPU like the one in the Allwinner D1 SoC. Add a compatible entry and a list of power domain names for it. Reviewed-by: Andre Przywara Signed-off-by: Chen-Yu Tsai --- drivers/pmdomain/sunxi/sun20i-ppu.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/pmdomain/sunxi/sun20i-ppu.c b/drivers/pmdomain/sunxi/s= un20i-ppu.c index 9f002748d224..b65876a68cc1 100644 --- a/drivers/pmdomain/sunxi/sun20i-ppu.c +++ b/drivers/pmdomain/sunxi/sun20i-ppu.c @@ -193,6 +193,19 @@ static const struct sun20i_ppu_desc sun8i_v853_ppu_des= c =3D { .num_domains =3D ARRAY_SIZE(sun8i_v853_ppu_pd_names), }; =20 +static const char *const sun55i_a523_ppu_pd_names[] =3D { + "DSP", + "NPU", + "AUDIO", + "SRAM", + "RISCV", +}; + +static const struct sun20i_ppu_desc sun55i_a523_ppu_desc =3D { + .names =3D sun55i_a523_ppu_pd_names, + .num_domains =3D ARRAY_SIZE(sun55i_a523_ppu_pd_names), +}; + static const struct of_device_id sun20i_ppu_of_match[] =3D { { .compatible =3D "allwinner,sun20i-d1-ppu", @@ -202,6 +215,10 @@ static const struct of_device_id sun20i_ppu_of_match[]= =3D { .compatible =3D "allwinner,sun8i-v853-ppu", .data =3D &sun8i_v853_ppu_desc, }, + { + .compatible =3D "allwinner,sun55i-a523-ppu", + .data =3D &sun55i_a523_ppu_desc, + }, { } }; MODULE_DEVICE_TABLE(of, sun20i_ppu_of_match); --=20 2.39.5 From nobody Tue Oct 7 13:08:06 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 21D202E92C3; Wed, 9 Jul 2025 15:53:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752076427; cv=none; b=XEAKFpCs0188Ca4DoTv16on//8ndOx4H41ZZPQgjZDXMx/l4ns0seIEf5g1veuJhNxKJu9umBRxuL2ybXfOdxYAVq+DyLiC7VY7bRH/c9MlXOhpXd0zvWSdR6XOJMSrFUdXwv3P7El6lbpeJIIpKY/kJUCZZTHcUkX2KIRLfGAM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752076427; c=relaxed/simple; bh=bhvlZxpF344s3Cn9ppDtECocZaX1zt5idxwPfkm+U2o=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=prPb9SHjlSqPW6EcjZpYUYR2ybil5HVFINYQjEaE0vXrZVb/Psa6JLyuLt0yqIurcxvBt5QEj9Ehyo5OF8xFv0vOsiaPuliWtCoZXY/eA4sBRJwVxAE2BYXsz2G0LFGJuFp7PYgZyg7OHsQlRGdvDJiwdJLA7l/iOhdvEnggp3g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=U327POfd; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="U327POfd" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6CD1AC4CEEF; Wed, 9 Jul 2025 15:53:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1752076426; bh=bhvlZxpF344s3Cn9ppDtECocZaX1zt5idxwPfkm+U2o=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=U327POfdPOi8fE11KxgEtuCd102NY8ngw5i99vLiJql9ESB8/eTeWEKVW9qQsggoE FJ0uMO3yrN9GVsDJx/hGKjOuH81XuZRUoFAgEsVKpsZTn9ljCRjRrgxCKR+Q9QMmvx WEJ884zPlGOrc6Z5WtNfO65MhTWHiZOnR0NJHdfznU//QOmmDmAA68QDp9M636esJF Ffc1qenOFAy2lsm0a3di9KS4L/kXFgsVOOyrcSL/qS0dnlKBqBwrol66d27GgoXXE+ mCwsHbtDa9FnpNWD7AvHQttLOWu1BaSOvKyOR/fCTIUgCRgCqhGDQ6GwuCG5gv67Vt /UkgM8x303avg== Received: by wens.tw (Postfix, from userid 1000) id 45DBF5FEA4; Wed, 9 Jul 2025 23:53:44 +0800 (CST) From: Chen-Yu Tsai To: Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-sunxi@lists.linux.dev, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH v2 3/4] pmdomain: sunxi: add driver for Allwinner A523's PCK-600 power controller Date: Wed, 9 Jul 2025 23:53:42 +0800 Message-Id: <20250709155343.3765227-4-wens@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250709155343.3765227-1-wens@kernel.org> References: <20250709155343.3765227-1-wens@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Chen-Yu Tsai Allwinner A523 family has a second power controller, named PCK-600 in the datasheets and BSP. It is likely based on ARM's PCK-600 hardware block, with some additional delay controls. The only documentation for this hardware is the BSP driver. The standard registers defined in ARM's Power Policy Unit Architecture Specification line up. Some extra delay controls are found in the reserved range of registers. Add a driver for this power controller. Delay control register values and power domain names are from the BSP driver. Signed-off-by: Chen-Yu Tsai --- drivers/pmdomain/sunxi/Kconfig | 8 + drivers/pmdomain/sunxi/Makefile | 1 + drivers/pmdomain/sunxi/sun55i-pck600.c | 225 +++++++++++++++++++++++++ 3 files changed, 234 insertions(+) create mode 100644 drivers/pmdomain/sunxi/sun55i-pck600.c diff --git a/drivers/pmdomain/sunxi/Kconfig b/drivers/pmdomain/sunxi/Kconfig index 43eecb3ea981..3e2b77cd9a2b 100644 --- a/drivers/pmdomain/sunxi/Kconfig +++ b/drivers/pmdomain/sunxi/Kconfig @@ -18,3 +18,11 @@ config SUN50I_H6_PRCM_PPU Say y to enable the Allwinner H6/H616 PRCM power domain driver. This is required to enable the Mali GPU in the H616 SoC, it is optional for the H6. + +config SUN55I_PCK600 + bool "Allwinner A523 PCK-600 power domain driver" + depends on PM + select PM_GENERIC_DOMAINS + help + Say y to enable the PCK-600 power domain driver. This saves power + when certain peripherals, such as the video engine, are idle. diff --git a/drivers/pmdomain/sunxi/Makefile b/drivers/pmdomain/sunxi/Makef= ile index c1343e123759..e344b232fc9f 100644 --- a/drivers/pmdomain/sunxi/Makefile +++ b/drivers/pmdomain/sunxi/Makefile @@ -1,3 +1,4 @@ # SPDX-License-Identifier: GPL-2.0-only obj-$(CONFIG_SUN20I_PPU) +=3D sun20i-ppu.o obj-$(CONFIG_SUN50I_H6_PRCM_PPU) +=3D sun50i-h6-prcm-ppu.o +obj-$(CONFIG_SUN55I_PCK600) +=3D sun55i-pck600.o diff --git a/drivers/pmdomain/sunxi/sun55i-pck600.c b/drivers/pmdomain/sunx= i/sun55i-pck600.c new file mode 100644 index 000000000000..7248f6113665 --- /dev/null +++ b/drivers/pmdomain/sunxi/sun55i-pck600.c @@ -0,0 +1,225 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Allwinner PCK-600 power domain support + * + * Copyright (c) 2025 Chen-Yu Tsai + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define PPU_PWPR 0x0 +#define PPU_PWSR 0x8 +#define PPU_DCDR0 0x170 +#define PPU_DCDR1 0x174 + +#define PPU_PWSR_PWR_STATUS GENMASK(3, 0) +#define PPU_POWER_MODE_ON 0x8 +#define PPU_POWER_MODE_OFF 0x0 + +#define PPU_REG_SIZE 0x1000 + +struct sunxi_pck600_desc { + const char * const *pd_names; + unsigned int num_domains; + u32 logic_power_switch0_delay_offset; + u32 logic_power_switch1_delay_offset; + u32 off2on_delay_offset; + u32 device_ctrl0_delay; + u32 device_ctrl1_delay; + u32 logic_power_switch0_delay; + u32 logic_power_switch1_delay; + u32 off2on_delay; +}; + +struct sunxi_pck600_pd { + struct generic_pm_domain genpd; + struct sunxi_pck600 *pck; + void __iomem *base; +}; + +struct sunxi_pck600 { + struct device *dev; + struct genpd_onecell_data genpd_data; + struct sunxi_pck600_pd pds[]; +}; + +#define to_sunxi_pd(gpd) container_of(gpd, struct sunxi_pck600_pd, genpd) + +static int sunxi_pck600_pd_set_power(struct sunxi_pck600_pd *pd, bool on) +{ + struct sunxi_pck600 *pck =3D pd->pck; + struct generic_pm_domain *genpd =3D &pd->genpd; + int ret; + u32 val, reg; + + val =3D on ? PPU_POWER_MODE_ON : PPU_POWER_MODE_OFF; + + reg =3D readl(pd->base + PPU_PWPR); + FIELD_MODIFY(PPU_PWSR_PWR_STATUS, ®, val); + writel(reg, pd->base + PPU_PWPR); + + /* push write out to hardware */ + reg =3D readl(pd->base + PPU_PWPR); + + ret =3D readl_poll_timeout_atomic(pd->base + PPU_PWSR, reg, + FIELD_GET(PPU_PWSR_PWR_STATUS, reg) =3D=3D val, + 0, 10000); + if (ret) + dev_err(pck->dev, "failed to turn domain \"%s\" %s: %d\n", + genpd->name, str_on_off(on), ret); + + return ret; +} + +static int sunxi_pck600_power_on(struct generic_pm_domain *domain) +{ + struct sunxi_pck600_pd *pd =3D to_sunxi_pd(domain); + + return sunxi_pck600_pd_set_power(pd, true); +} + +static int sunxi_pck600_power_off(struct generic_pm_domain *domain) +{ + struct sunxi_pck600_pd *pd =3D to_sunxi_pd(domain); + + return sunxi_pck600_pd_set_power(pd, false); +} + +static void sunxi_pck600_pd_setup(struct sunxi_pck600_pd *pd, + const struct sunxi_pck600_desc *desc) +{ + writel(desc->device_ctrl0_delay, pd->base + PPU_DCDR0); + writel(desc->device_ctrl1_delay, pd->base + PPU_DCDR1); + writel(desc->logic_power_switch0_delay, + pd->base + desc->logic_power_switch0_delay_offset); + writel(desc->logic_power_switch1_delay, + pd->base + desc->logic_power_switch1_delay_offset); + writel(desc->off2on_delay, pd->base + desc->off2on_delay_offset); +} + +static int sunxi_pck600_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + const struct sunxi_pck600_desc *desc; + struct genpd_onecell_data *genpds; + struct sunxi_pck600 *pck; + struct reset_control *rst; + struct clk *clk; + void __iomem *base; + int i, ret; + + desc =3D of_device_get_match_data(dev); + + pck =3D devm_kzalloc(dev, struct_size(pck, pds, desc->num_domains), GFP_K= ERNEL); + if (!pck) + return -ENOMEM; + + pck->dev =3D &pdev->dev; + platform_set_drvdata(pdev, pck); + + genpds =3D &pck->genpd_data; + genpds->num_domains =3D desc->num_domains; + genpds->domains =3D devm_kcalloc(dev, desc->num_domains, + sizeof(*genpds->domains), GFP_KERNEL); + if (!genpds->domains) + return -ENOMEM; + + base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + rst =3D devm_reset_control_get_exclusive_released(dev, NULL); + if (IS_ERR(rst)) + return dev_err_probe(dev, PTR_ERR(rst), "failed to get reset control\n"); + + clk =3D devm_clk_get_enabled(dev, NULL); + if (IS_ERR(clk)) + return dev_err_probe(dev, PTR_ERR(clk), "failed to get clock\n"); + + for (i =3D 0; i < desc->num_domains; i++) { + struct sunxi_pck600_pd *pd =3D &pck->pds[i]; + + pd->genpd.name =3D desc->pd_names[i]; + pd->genpd.power_off =3D sunxi_pck600_power_off; + pd->genpd.power_on =3D sunxi_pck600_power_on; + pd->base =3D base + PPU_REG_SIZE * i; + + sunxi_pck600_pd_setup(pd, desc); + ret =3D pm_genpd_init(&pd->genpd, NULL, false); + if (ret) { + dev_err_probe(dev, ret, "failed to initialize power domain\n"); + goto err_remove_pds; + } + + genpds->domains[i] =3D &pd->genpd; + } + + ret =3D of_genpd_add_provider_onecell(dev_of_node(dev), genpds); + if (ret) { + dev_err_probe(dev, ret, "failed to add PD provider\n"); + goto err_remove_pds; + } + + return 0; + +err_remove_pds: + for (i--; i >=3D 0; i--) + pm_genpd_remove(genpds->domains[i]); + + return ret; +} + +static const char * const sun55i_a523_pck600_pd_names[] =3D { + "VE", "GPU", "VI", "VO0", "VO1", "DE", "NAND", "PCIE" +}; + +static const struct sunxi_pck600_desc sun55i_a523_pck600_desc =3D { + .pd_names =3D sun55i_a523_pck600_pd_names, + .num_domains =3D ARRAY_SIZE(sun55i_a523_pck600_pd_names), + .logic_power_switch0_delay_offset =3D 0xc00, + .logic_power_switch1_delay_offset =3D 0xc04, + .off2on_delay_offset =3D 0xc10, + .device_ctrl0_delay =3D 0xffffff, + .device_ctrl1_delay =3D 0xffff, + .logic_power_switch0_delay =3D 0x8080808, + .logic_power_switch1_delay =3D 0x808, + .off2on_delay =3D 0x8 +}; + +static const struct of_device_id sunxi_pck600_of_match[] =3D { + { + .compatible =3D "allwinner,sun55i-a523-pck-600", + .data =3D &sun55i_a523_pck600_desc, + }, + {} +}; +MODULE_DEVICE_TABLE(of, sunxi_pck600_of_match); + +static struct platform_driver sunxi_pck600_driver =3D { + .probe =3D sunxi_pck600_probe, + .driver =3D { + .name =3D "sunxi-pck-600", + .of_match_table =3D sunxi_pck600_of_match, + /* Power domains cannot be removed if in use. */ + .suppress_bind_attrs =3D true, + }, +}; +module_platform_driver(sunxi_pck600_driver); + +MODULE_DESCRIPTION("Allwinner PCK-600 power domain driver"); +MODULE_AUTHOR("Chen-Yu Tsai "); +MODULE_LICENSE("GPL"); --=20 2.39.5 From nobody Tue Oct 7 13:08:06 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ED62F23B60A; Wed, 9 Jul 2025 15:53:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752076427; 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charset="utf-8" From: Chen-Yu Tsai The A523 SoC family has two power controllers, one based on the existing PPU, and one newer one based on ARM's PCK-600. Add device nodes for both of them. Reviewed-by: Andre Przywara Signed-off-by: Chen-Yu Tsai --- arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi b/arch/arm64/bo= ot/dts/allwinner/sun55i-a523.dtsi index cf0bc39aab04..dd6fa22f960f 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi @@ -7,6 +7,8 @@ #include #include #include +#include +#include =20 / { interrupt-parent =3D <&gic>; @@ -576,6 +578,14 @@ mdio0: mdio { }; }; =20 + ppu: power-controller@7001400 { + compatible =3D "allwinner,sun55i-a523-ppu"; + reg =3D <0x07001400 0x400>; + clocks =3D <&r_ccu CLK_BUS_R_PPU1>; + resets =3D <&r_ccu RST_BUS_R_PPU1>; + #power-domain-cells =3D <1>; + }; + r_ccu: clock-controller@7010000 { compatible =3D "allwinner,sun55i-a523-r-ccu"; reg =3D <0x7010000 0x250>; @@ -622,6 +632,14 @@ r_i2c_pins: r-i2c-pins { }; }; =20 + pck600: power-controller@7060000 { + compatible =3D "allwinner,sun55i-a523-pck-600"; + reg =3D <0x07060000 0x8000>; + clocks =3D <&r_ccu CLK_BUS_R_PPU0>; + resets =3D <&r_ccu RST_BUS_R_PPU0>; + #power-domain-cells =3D <1>; + }; + r_i2c0: i2c@7081400 { compatible =3D "allwinner,sun55i-a523-i2c", "allwinner,sun8i-v536-i2c", --=20 2.39.5