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X-OriginatorOrg: phytec.fr X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Jul 2025 15:10:13.5480 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: dbfcc7c5-0ef3-4edc-0bf4-08ddbefab485 X-MS-Exchange-CrossTenant-Id: e609157c-80e2-446d-9be3-9c99c2399d29 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e609157c-80e2-446d-9be3-9c99c2399d29;Ip=[91.26.50.189];Helo=[Diagnostix.phytec.de] X-MS-Exchange-CrossTenant-AuthSource: DB1PEPF000509ED.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DU4P195MB2616 Content-Type: text/plain; charset="utf-8" Rename "stm32mp157c-phycore-*" device tree for the following reasons: - The name of the dts should match to the phyBOARD name and not the name of the SoM ("phycore-stm32mp1-3" was initialy coming from the name of the yocto machine from meta-phytec). - PHYTEC manages different SoM configurations with different STM32MP15x SoC versions, so common dtsi files starting with "stm32mp15xx-*" should be used (as it is done for ST boards for example). - Add "-rdk" as suffix (for "Rapid Development Kit") to match our others phytec boards dts names (imx6, imx6ul,..). - "model" property is updated to introduce the name "phyBOARD-Sargas". Signed-off-by: Christophe Parant --- arch/arm/boot/dts/st/Makefile | 2 +- ...ore-stm32mp1-3.dts =3D> stm32mp157c-phyboard-sargas-rdk.dts} | 4 ++-- ...re-stm32mp15-som.dtsi =3D> stm32mp15xx-phyboard-sargas.dtsi} | 3 --- 3 files changed, 3 insertions(+), 6 deletions(-) rename arch/arm/boot/dts/st/{stm32mp157c-phycore-stm32mp1-3.dts =3D> stm32= mp157c-phyboard-sargas-rdk.dts} (89%) rename arch/arm/boot/dts/st/{stm32mp157c-phycore-stm32mp15-som.dtsi =3D> s= tm32mp15xx-phyboard-sargas.dtsi} (99%) diff --git a/arch/arm/boot/dts/st/Makefile b/arch/arm/boot/dts/st/Makefile index cc9948b9870f..099199f3e5f3 100644 --- a/arch/arm/boot/dts/st/Makefile +++ b/arch/arm/boot/dts/st/Makefile @@ -71,7 +71,7 @@ dtb-$(CONFIG_ARCH_STM32) +=3D \ stm32mp157c-lxa-tac-gen2.dtb \ stm32mp157c-odyssey.dtb \ stm32mp157c-osd32mp1-red.dtb \ - stm32mp157c-phycore-stm32mp1-3.dtb \ + stm32mp157c-phyboard-sargas-rdk.dtb \ stm32mp157c-ultra-fly-sbc.dtb dtb-$(CONFIG_ARCH_U8500) +=3D \ ste-snowball.dtb \ diff --git a/arch/arm/boot/dts/st/stm32mp157c-phycore-stm32mp1-3.dts b/arch= /arm/boot/dts/st/stm32mp157c-phyboard-sargas-rdk.dts similarity index 89% rename from arch/arm/boot/dts/st/stm32mp157c-phycore-stm32mp1-3.dts rename to arch/arm/boot/dts/st/stm32mp157c-phyboard-sargas-rdk.dts index 28d7203264ce..26995eb2a619 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-phycore-stm32mp1-3.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-phyboard-sargas-rdk.dts @@ -10,10 +10,10 @@ #include "stm32mp157.dtsi" #include "stm32mp15xc.dtsi" #include "stm32mp15xxac-pinctrl.dtsi" -#include "stm32mp157c-phycore-stm32mp15-som.dtsi" +#include "stm32mp15xx-phyboard-sargas.dtsi" =20 / { - model =3D "PHYTEC phyCORE-STM32MP1-3 Dev Board"; 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X-OriginatorOrg: phytec.fr X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Jul 2025 15:10:13.8691 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f2223a7d-4a71-4634-b639-08ddbefab4b6 X-MS-Exchange-CrossTenant-Id: e609157c-80e2-446d-9be3-9c99c2399d29 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e609157c-80e2-446d-9be3-9c99c2399d29;Ip=[91.26.50.189];Helo=[Diagnostix.phytec.de] X-MS-Exchange-CrossTenant-AuthSource: DB1PEPF000509ED.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: GV1P195MB2638 Content-Type: text/plain; charset="utf-8" Add stm32mp15xx-phycore-som.dtsi device tree file to split hardware features between the phyBOARD (baseboard) and the phyCORE (SoM). Signed-off-by: Christophe Parant --- .../st/stm32mp157c-phyboard-sargas-rdk.dts | 2 +- .../dts/st/stm32mp15xx-phyboard-sargas.dtsi | 317 +---------------- .../boot/dts/st/stm32mp15xx-phycore-som.dtsi | 329 ++++++++++++++++++ 3 files changed, 331 insertions(+), 317 deletions(-) create mode 100644 arch/arm/boot/dts/st/stm32mp15xx-phycore-som.dtsi diff --git a/arch/arm/boot/dts/st/stm32mp157c-phyboard-sargas-rdk.dts b/arc= h/arm/boot/dts/st/stm32mp157c-phyboard-sargas-rdk.dts index 26995eb2a619..48adc3462958 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-phyboard-sargas-rdk.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-phyboard-sargas-rdk.dts @@ -9,7 +9,7 @@ #include #include "stm32mp157.dtsi" #include "stm32mp15xc.dtsi" -#include "stm32mp15xxac-pinctrl.dtsi" +#include "stm32mp15xx-phycore-som.dtsi" #include "stm32mp15xx-phyboard-sargas.dtsi" =20 / { diff --git a/arch/arm/boot/dts/st/stm32mp15xx-phyboard-sargas.dtsi b/arch/a= rm/boot/dts/st/stm32mp15xx-phyboard-sargas.dtsi index ebbb82c09a1e..2fdab99fc562 100644 --- a/arch/arm/boot/dts/st/stm32mp15xx-phyboard-sargas.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15xx-phyboard-sargas.dtsi @@ -5,23 +5,13 @@ * Author: Dom VOVARD . */ =20 -#include -#include + #include #include #include #include -#include -#include -#include "stm32mp15-pinctrl.dtsi" =20 / { - aliases { - ethernet0 =3D ðernet0; - rtc0 =3D &i2c4_rtc; - rtc1 =3D &rtc; - }; - chosen { stdout-path =3D "serial0:115200n8"; }; @@ -42,48 +32,6 @@ key-enter { }; }; =20 - reserved-memory { - #address-cells =3D <1>; - #size-cells =3D <1>; - ranges; - - retram: retram@38000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x38000000 0x10000>; - no-map; - }; - - mcuram: mcuram@30000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x30000000 0x40000>; - no-map; - }; - - mcuram2: mcuram2@10000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x10000000 0x40000>; - no-map; - }; - - vdev0vring0: vdev0vring0@10040000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x10040000 0x1000>; - no-map; - }; - - vdev0vring1: vdev0vring1@10041000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x10041000 0x1000>; - no-map; - }; - - vdev0buffer: vdev0buffer@10042000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x10042000 0x4000>; - no-map; - }; - }; - sound { compatible =3D "audio-graph-card"; label =3D "STM32MP1-PHYCORE"; @@ -93,44 +41,6 @@ sound { dais =3D <&sai2b_port>, <&sai2a_port>; }; - - regulator_vin: regulator { - compatible =3D "regulator-fixed"; - regulator-name =3D "vin"; - regulator-min-microvolt =3D <5000000>; - regulator-max-microvolt =3D <5000000>; - regulator-always-on; - }; -}; - -ðernet0 { - pinctrl-0 =3D <ðernet0_rgmii_pins_d>; - pinctrl-1 =3D <ðernet0_rgmii_sleep_pins_d>; - pinctrl-names =3D "default", "sleep"; - phy-mode =3D "rgmii-id"; - max-speed =3D <1000>; - phy-handle =3D <&phy0>; - st,eth-clk-sel; - status =3D "okay"; - - mdio { - #address-cells =3D <1>; - #size-cells =3D <0>; - compatible =3D "snps,dwmac-mdio"; - - phy0: ethernet-phy@1 { - compatible =3D "ethernet-phy-ieee802.3-c22"; - reg =3D <1>; - interrupt-parent =3D <&gpiog>; - interrupts =3D <12 IRQ_TYPE_EDGE_FALLING>; - ti,rx-internal-delay =3D ; - ti,tx-internal-delay =3D ; - ti,fifo-depth =3D ; - ti,min-output-impedance; - enet-phy-lane-no-swap; - ti,clk-output-sel =3D ; - }; - }; }; =20 &i2c1 { @@ -222,176 +132,6 @@ led-2 { }; }; =20 -&i2c4 { - pinctrl-names =3D "default", "sleep"; - pinctrl-0 =3D <&i2c4_pins_a>; - pinctrl-1 =3D <&i2c4_sleep_pins_a>; - i2c-scl-rising-time-ns =3D <185>; - i2c-scl-falling-time-ns =3D <20>; - status =3D "okay"; - - pmic@33 { - compatible =3D "st,stpmic1"; - reg =3D <0x33>; - interrupts-extended =3D <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; - interrupt-controller; - #interrupt-cells =3D <2>; - - regulators { - compatible =3D "st,stpmic1-regulators"; - buck1-supply =3D <®ulator_vin>; - buck2-supply =3D <®ulator_vin>; - buck3-supply =3D <®ulator_vin>; - buck4-supply =3D <®ulator_vin>; - ldo1-supply =3D <&v3v3>; - ldo2-supply =3D <&v3v3>; - ldo3-supply =3D <&vdd_ddr>; - ldo4-supply =3D <®ulator_vin>; - ldo5-supply =3D <&v3v3>; - ldo6-supply =3D <&v3v3>; - boost-supply =3D <®ulator_vin>; - pwr_sw1-supply =3D <&bst_out>; - pwr_sw2-supply =3D <&bst_out>; - - vddcore: buck1 { - regulator-name =3D "vddcore"; - regulator-min-microvolt =3D <1200000>; - regulator-max-microvolt =3D <1350000>; - regulator-always-on; - regulator-initial-mode =3D <0>; - }; - - vdd_ddr: buck2 { - regulator-name =3D "vdd_ddr"; - regulator-min-microvolt =3D <1350000>; - regulator-max-microvolt =3D <1350000>; - regulator-always-on; - regulator-initial-mode =3D <0>; - }; - - vdd: buck3 { - regulator-name =3D "vdd"; - regulator-min-microvolt =3D <3300000>; - regulator-max-microvolt =3D <3300000>; - regulator-always-on; - st,mask-reset; - regulator-initial-mode =3D <0>; - }; - - v3v3: buck4 { - regulator-name =3D "v3v3"; - regulator-min-microvolt =3D <3300000>; - regulator-max-microvolt =3D <3300000>; - regulator-always-on; - regulator-initial-mode =3D <0>; - }; - - v1v8_audio: ldo1 { - regulator-name =3D "v1v8_audio"; - regulator-min-microvolt =3D <1800000>; - regulator-max-microvolt =3D <1800000>; - regulator-always-on; - interrupts =3D ; - - }; - - vdd_eth_2v5: ldo2 { - regulator-name =3D "dd_eth_2v5"; - regulator-min-microvolt =3D <2500000>; - regulator-max-microvolt =3D <2500000>; - regulator-always-on; - interrupts =3D ; - - }; - - vtt_ddr: ldo3 { - regulator-name =3D "vtt_ddr"; - regulator-min-microvolt =3D <500000>; - regulator-max-microvolt =3D <750000>; - regulator-always-on; - regulator-over-current-protection; - }; - - vdd_usb: ldo4 { - regulator-name =3D "vdd_usb"; - interrupts =3D ; - }; - - vdda: ldo5 { - regulator-name =3D "vdda"; - regulator-min-microvolt =3D <2900000>; - regulator-max-microvolt =3D <2900000>; - interrupts =3D ; - regulator-boot-on; - }; - - vdd_eth_1v0: ldo6 { - regulator-name =3D "vdd_eth_1v0"; - regulator-min-microvolt =3D <1000000>; - regulator-max-microvolt =3D <1000000>; - regulator-always-on; - interrupts =3D ; - - }; - - vref_ddr: vref_ddr { - regulator-name =3D "vref_ddr"; - regulator-always-on; - }; - - bst_out: boost { - regulator-name =3D "bst_out"; - interrupts =3D ; - }; - - vbus_otg: pwr_sw1 { - regulator-name =3D "vbus_otg"; - interrupts =3D ; - regulator-active-discharge =3D <1>; - }; - - vbus_sw: pwr_sw2 { - regulator-name =3D "vbus_sw"; - interrupts =3D ; - regulator-active-discharge =3D <1>; - }; - }; - - onkey { - compatible =3D "st,stpmic1-onkey"; - interrupts =3D , - ; - interrupt-names =3D "onkey-falling", - "onkey-rising"; - power-off-time-sec =3D <10>; - }; - - watchdog { - compatible =3D "st,stpmic1-wdt"; - }; - }; - - i2c4_eeprom: eeprom@50 { - compatible =3D "microchip,24c32", - "atmel,24c32"; - reg =3D <0x50>; - }; - - i2c4_rtc: rtc@52 { - compatible =3D "microcrystal,rv3028"; - reg =3D <0x52>; - }; -}; - -&ipcc { - status =3D "okay"; -}; - -&iwdg2 { - timeout-sec =3D <32>; - status =3D "okay"; -}; - &m_can2 { pinctrl-names =3D "default", "sleep"; pinctrl-0 =3D <&m_can2_pins_a>; @@ -399,46 +139,6 @@ &m_can2 { status =3D "okay"; }; =20 -&m4_rproc { - memory-region =3D <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>, - <&vdev0vring1>, <&vdev0buffer>; - mboxes =3D <&ipcc 0>, <&ipcc 1>, <&ipcc 2>, <&ipcc 3>; - mbox-names =3D "vq0", "vq1", "shutdown", "detach"; - interrupt-parent =3D <&exti>; - interrupts =3D <68 1>; - status =3D "okay"; -}; - -&pwr_regulators { - vdd-supply =3D <&vdd>; - vdd_3v3_usbfs-supply =3D <&vdd_usb>; -}; - -&qspi { - pinctrl-names =3D "default", "sleep"; - pinctrl-0 =3D <&qspi_clk_pins_a &qspi_bk1_pins_a>; - pinctrl-1 =3D <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a>; - status =3D "okay"; - - flash0: flash@0 { - compatible =3D "winbond,w25q128", "jedec,spi-nor"; - reg =3D <0>; - spi-rx-bus-width =3D <4>; - spi-max-frequency =3D <50000000>; - m25p,fast-read; - #address-cells =3D <1>; - #size-cells =3D <1>; - }; -}; - -&rng1 { - status =3D "okay"; -}; - -&rtc { - status =3D "okay"; -}; - &sai2 { clocks =3D <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>; clock-names =3D "pclk", "x8k", "x11k"; @@ -492,21 +192,6 @@ &sdmmc1 { status =3D "okay"; }; =20 -&sdmmc2 { - pinctrl-names =3D "default", "opendrain", "sleep"; - pinctrl-0 =3D <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_e>; - pinctrl-1 =3D <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_e>; - pinctrl-2 =3D <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_e>; - non-removable; - no-sd; - no-sdio; - st,neg-edge; - bus-width =3D <8>; - vmmc-supply =3D <&v3v3>; - vqmmc-supply =3D <&v3v3>; - mmc-ddr-3_3v; -}; - &spi1 { pinctrl-names =3D "default", "sleep"; pinctrl-0 =3D <&spi1_pins_a>; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-phycore-som.dtsi b/arch/arm/b= oot/dts/st/stm32mp15xx-phycore-som.dtsi new file mode 100644 index 000000000000..660cdc260963 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp15xx-phycore-som.dtsi @@ -0,0 +1,329 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) Phytec GmbH 2019-2020 - All Rights Reserved + * Author: Dom VOVARD + * Copyright (C) 2022-2023 Steffen Trumtrar + * Copyright (C) 2024 PHYTEC Messtechnik GmbH + * Author: Christophe Parant + */ + +#include +#include +#include +#include +#include "stm32mp15-pinctrl.dtsi" +#include "stm32mp15xxac-pinctrl.dtsi" + +/ { + + aliases { + ethernet0 =3D ðernet0; + rtc0 =3D &i2c4_rtc; + rtc1 =3D &rtc; + }; + + reserved-memory { + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges; + + retram: retram@38000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x38000000 0x10000>; + no-map; + }; + + mcuram: mcuram@30000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x30000000 0x40000>; + no-map; + }; + + mcuram2: mcuram2@10000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x10000000 0x40000>; + no-map; + }; + + vdev0vring0: vdev0vring0@10040000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x10040000 0x1000>; + no-map; + }; + + vdev0vring1: vdev0vring1@10041000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x10041000 0x1000>; + no-map; + }; + + vdev0buffer: vdev0buffer@10042000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x10042000 0x4000>; + no-map; + }; + }; + + regulator_vin: regulator { + compatible =3D "regulator-fixed"; + regulator-name =3D "vin"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + regulator-always-on; + }; +}; + +ðernet0 { + pinctrl-0 =3D <ðernet0_rgmii_pins_d>; + pinctrl-1 =3D <ðernet0_rgmii_sleep_pins_d>; + pinctrl-names =3D "default", "sleep"; + phy-mode =3D "rgmii-id"; + max-speed =3D <1000>; + phy-handle =3D <&phy0>; + st,eth-clk-sel; + status =3D "okay"; + + mdio { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "snps,dwmac-mdio"; + + phy0: ethernet-phy@1 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <1>; + interrupt-parent =3D <&gpiog>; + interrupts =3D <12 IRQ_TYPE_EDGE_FALLING>; + ti,rx-internal-delay =3D ; + ti,tx-internal-delay =3D ; + ti,fifo-depth =3D ; + ti,min-output-impedance; + enet-phy-lane-no-swap; + ti,clk-output-sel =3D ; + }; + }; +}; + +&i2c4 { + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&i2c4_pins_a>; + pinctrl-1 =3D <&i2c4_sleep_pins_a>; + i2c-scl-rising-time-ns =3D <185>; + i2c-scl-falling-time-ns =3D <20>; + status =3D "okay"; + + pmic@33 { + compatible =3D "st,stpmic1"; + reg =3D <0x33>; + interrupts-extended =3D <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells =3D <2>; + + regulators { + compatible =3D "st,stpmic1-regulators"; + buck1-supply =3D <®ulator_vin>; + buck2-supply =3D <®ulator_vin>; + buck3-supply =3D <®ulator_vin>; + buck4-supply =3D <®ulator_vin>; + ldo1-supply =3D <&v3v3>; + ldo2-supply =3D <&v3v3>; + ldo3-supply =3D <&vdd_ddr>; + ldo4-supply =3D <®ulator_vin>; + ldo5-supply =3D <&v3v3>; + ldo6-supply =3D <&v3v3>; + boost-supply =3D <®ulator_vin>; + pwr_sw1-supply =3D <&bst_out>; + pwr_sw2-supply =3D <&bst_out>; + + vddcore: buck1 { + regulator-name =3D "vddcore"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1350000>; + regulator-always-on; + regulator-initial-mode =3D <0>; + }; + + vdd_ddr: buck2 { + regulator-name =3D "vdd_ddr"; + regulator-min-microvolt =3D <1350000>; + regulator-max-microvolt =3D <1350000>; + regulator-always-on; + regulator-initial-mode =3D <0>; + }; + + vdd: buck3 { + regulator-name =3D "vdd"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-always-on; + st,mask-reset; + regulator-initial-mode =3D <0>; + }; + + v3v3: buck4 { + regulator-name =3D "v3v3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-always-on; + regulator-initial-mode =3D <0>; + }; + + v1v8_audio: ldo1 { + regulator-name =3D "v1v8_audio"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-always-on; + interrupts =3D ; + + }; + + vdd_eth_2v5: ldo2 { + regulator-name =3D "dd_eth_2v5"; + regulator-min-microvolt =3D <2500000>; + regulator-max-microvolt =3D <2500000>; + regulator-always-on; + interrupts =3D ; + + }; + + vtt_ddr: ldo3 { + regulator-name =3D "vtt_ddr"; + regulator-min-microvolt =3D <500000>; + regulator-max-microvolt =3D <750000>; + regulator-always-on; + regulator-over-current-protection; + }; + + vdd_usb: ldo4 { + regulator-name =3D "vdd_usb"; + interrupts =3D ; + }; + + vdda: ldo5 { + regulator-name =3D "vdda"; + regulator-min-microvolt =3D <2900000>; + regulator-max-microvolt =3D <2900000>; + interrupts =3D ; + regulator-boot-on; + }; + + vdd_eth_1v0: ldo6 { + regulator-name =3D "vdd_eth_1v0"; + regulator-min-microvolt =3D <1000000>; + regulator-max-microvolt =3D <1000000>; + regulator-always-on; + interrupts =3D ; + + }; + + vref_ddr: vref_ddr { + regulator-name =3D "vref_ddr"; + regulator-always-on; + }; + + bst_out: boost { + regulator-name =3D "bst_out"; + interrupts =3D ; + }; + + vbus_otg: pwr_sw1 { + regulator-name =3D "vbus_otg"; + interrupts =3D ; + regulator-active-discharge =3D <1>; + }; + + vbus_sw: pwr_sw2 { + regulator-name =3D "vbus_sw"; + interrupts =3D ; + regulator-active-discharge =3D <1>; + }; + }; + + onkey { + compatible =3D "st,stpmic1-onkey"; + interrupts =3D , + ; + interrupt-names =3D "onkey-falling", + "onkey-rising"; + power-off-time-sec =3D <10>; + }; + + watchdog { + compatible =3D "st,stpmic1-wdt"; + }; + }; + + i2c4_eeprom: eeprom@50 { + compatible =3D "microchip,24c32", + "atmel,24c32"; + reg =3D <0x50>; + }; + + i2c4_rtc: rtc@52 { + compatible =3D "microcrystal,rv3028"; + reg =3D <0x52>; + }; +}; + +&ipcc { + status =3D "okay"; +}; + +&iwdg2 { + timeout-sec =3D <32>; + status =3D "okay"; +}; + +&m4_rproc { + memory-region =3D <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>, + <&vdev0vring1>, <&vdev0buffer>; + mboxes =3D <&ipcc 0>, <&ipcc 1>, <&ipcc 2>, <&ipcc 3>; + mbox-names =3D "vq0", "vq1", "shutdown", "detach"; + interrupt-parent =3D <&exti>; + interrupts =3D <68 1>; + status =3D "okay"; +}; + +&pwr_regulators { + vdd-supply =3D <&vdd>; + vdd_3v3_usbfs-supply =3D <&vdd_usb>; +}; + +&qspi { + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&qspi_clk_pins_a &qspi_bk1_pins_a>; + pinctrl-1 =3D <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a>; + status =3D "okay"; + + flash0: flash@0 { + compatible =3D "winbond,w25q128", "jedec,spi-nor"; + reg =3D <0>; + spi-rx-bus-width =3D <4>; + spi-max-frequency =3D <50000000>; + m25p,fast-read; + #address-cells =3D <1>; + #size-cells =3D <1>; + }; +}; + +&rng1 { + status =3D "okay"; +}; + +&rtc { + status =3D "okay"; +}; + +&sdmmc2 { + pinctrl-names =3D "default", "opendrain", "sleep"; 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X-OriginatorOrg: phytec.fr X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Jul 2025 15:10:17.3441 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: de192625-d3fa-4495-4ffb-08ddbefab6c8 X-MS-Exchange-CrossTenant-Id: e609157c-80e2-446d-9be3-9c99c2399d29 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e609157c-80e2-446d-9be3-9c99c2399d29;Ip=[91.26.50.189];Helo=[Diagnostix.phytec.de] X-MS-Exchange-CrossTenant-AuthSource: DB1PEPF000509ED.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PAXP195MB1213 Content-Type: text/plain; charset="utf-8" As Phytec manages different SoM configurations with different STM32MP15 SoC versions, modify the phyBOARD and SoM compatible items to "enum" instead of "const". The description concerns PHYTEC SoM equipped with STM32MP157 ("st,stm32mp157" is "const"). Also add comments in front of the enum items to be able to identify the compatible string with the phyBOARD/phyCORE names. Signed-off-by: Christophe Parant --- Documentation/devicetree/bindings/arm/stm32/stm32.yaml | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml b/Docum= entation/devicetree/bindings/arm/stm32/stm32.yaml index 408532504a24..fbd3d364c1f7 100644 --- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml @@ -182,10 +182,12 @@ properties: - const: seeed,stm32mp157c-odyssey-som - const: st,stm32mp157 =20 - - description: Phytec STM32MP1 SoM based Boards + - description: Phytec STM32MP157 SoM based Boards items: - - const: phytec,phycore-stm32mp1-3 - - const: phytec,phycore-stm32mp157c-som + - enum: + - phytec,phycore-stm32mp1-3 # phyBOARD-Sargas with phyCORE-S= TM32MP157C SoM + - enum: + - phytec,phycore-stm32mp157c-som # phyCORE-STM32MP157C SoM - const: st,stm32mp157 =20 - description: Ultratronik STM32MP1 SBC based Boards --=20 2.34.1 From nobody Tue Oct 7 13:28:35 2025 Received: from EUR05-AM6-obe.outbound.protection.outlook.com (mail-am6eur05on2090.outbound.protection.outlook.com [40.107.22.90]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D95362E7199; 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X-OriginatorOrg: phytec.fr X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Jul 2025 15:10:17.7342 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6f21b0ac-5a0d-4983-f351-08ddbefab703 X-MS-Exchange-CrossTenant-Id: e609157c-80e2-446d-9be3-9c99c2399d29 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e609157c-80e2-446d-9be3-9c99c2399d29;Ip=[91.26.50.189];Helo=[Diagnostix.phytec.de] X-MS-Exchange-CrossTenant-AuthSource: DB1PEPF000509ED.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9P195MB0870 Content-Type: text/plain; charset="utf-8" Add add alternate pinmux for following interfaces used on phyBOARD-Sargas: - UART4 - LTDC - DCMI - TIM5 - SAI2 Fix "ethernet0_rgmii_pins_d" pinmux used on phyCORE-STM32MP15x: ETH_RGMII_GTX_CLK pin was missing. Signed-off-by: Christophe Parant --- arch/arm/boot/dts/st/stm32mp15-pinctrl.dtsi | 164 ++++++++++++++++++++ 1 file changed, 164 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dt= s/st/stm32mp15-pinctrl.dtsi index 40605ea85ee1..f242959e8716 100644 --- a/arch/arm/boot/dts/st/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15-pinctrl.dtsi @@ -223,6 +223,45 @@ pins { }; }; =20 + /omit-if-no-ref/ + dcmi_pins_d: dcmi-3 { + pins { + pinmux =3D ,/* DCMI_HSYNC */ + ,/* DCMI_VSYNC */ + ,/* DCMI_PIXCLK */ + ,/* DCMI_D0 */ + ,/* DCMI_D1 */ + ,/* DCMI_D2 */ + ,/* DCMI_D3 */ + ,/* DCMI_D4 */ + ,/* DCMI_D5 */ + ,/* DCMI_D6 */ + ,/* DCMI_D7 */ + ,/* DCMI_D8 */ + ;/* DCMI_D9 */ + bias-disable; + }; + }; + + /omit-if-no-ref/ + dcmi_sleep_pins_d: dcmi-sleep-3 { + pins { + pinmux =3D ,/* DCMI_HSYNC */ + ,/* DCMI_VSYNC */ + ,/* DCMI_PIXCLK */ + ,/* DCMI_D0 */ + ,/* DCMI_D1 */ + ,/* DCMI_D2 */ + ,/* DCMI_D3 */ + ,/* DCMI_D4 */ + ,/* DCMI_D5 */ + ,/* DCMI_D6 */ + ,/* DCMI_D7 */ + ,/* DCMI_D8 */ + ;/* DCMI_D9 */ + }; + }; + /omit-if-no-ref/ ethernet0_rgmii_pins_a: rgmii-0 { pins1 { @@ -386,6 +425,7 @@ pins1 { ethernet0_rgmii_pins_d: rgmii-3 { pins1 { pinmux =3D , /* ETH_RGMII_CLK125 */ + , /* ETH_RGMII_GTX_CLK */ , /* ETH_RGMII_TXD0 */ , /* ETH_RGMII_TXD1 */ , /* ETH_RGMII_TXD2 */ @@ -1304,6 +1344,65 @@ pins { }; }; =20 + /omit-if-no-ref/ + ltdc_pins_f: ltdc-5 { + pins { + pinmux =3D , /* LCD_CLK */ + , /* LCD_HSYNC */ + , /* LCD_VSYNC */ + , /* LCD_DE */ + , /* LCD_R2 */ + , /* LCD_R3 */ + , /* LCD_R4 */ + , /* LCD_R5 */ + , /* LCD_R6 */ + , /* LCD_R7 */ + , /* LCD_G2 */ + , /* LCD_G3 */ + , /* LCD_G4 */ + , /* LCD_G5 */ + , /* LCD_G6 */ + , /* LCD_G7 */ + , /* LCD_B2 */ + , /* LCD_B3 */ + , /* LCD_B4 */ + , /* LCD_B5 */ + , /* LCD_B6 */ + ; /* LCD_B7 */ + bias-disable; + drive-push-pull; + slew-rate =3D <1>; + }; + }; + + /omit-if-no-ref/ + ltdc_sleep_pins_f: ltdc-sleep-5 { + pins { + pinmux =3D , /* LCD_CLK */ + , /* LCD_HSYNC */ + , /* LCD_VSYNC */ + , /* LCD_DE */ + , /* LCD_R2 */ + , /* LCD_R3 */ + , /* LCD_R4 */ + , /* LCD_R5 */ + , /* LCD_R6 */ + , /* LCD_R7 */ + , /* LCD_G2 */ + , /* LCD_G3 */ + , /* LCD_G4 */ + , /* LCD_G5 */ + , /* LCD_G6 */ + , /* LCD_G7 */ + , /* LCD_B2 */ + , /* LCD_B3 */ + , /* LCD_B4 */ + , /* LCD_B5 */ + , /* LCD_B6 */ + ; /* LCD_B7 */ + }; + }; + /omit-if-no-ref/ mco1_pins_a: mco1-0 { pins { @@ -1644,6 +1743,23 @@ pins { }; }; =20 + /omit-if-no-ref/ + pwm5_pins_c: pwm5-2 { + pins { + pinmux =3D ; /* TIM5_CH4 */ + bias-pull-down; + drive-push-pull; + slew-rate =3D <0>; + }; + }; + + /omit-if-no-ref/ + pwm5_sleep_pins_c: pwm5-sleep-2 { + pins { + pinmux =3D ; /* TIM5_CH4 */ + }; + }; + /omit-if-no-ref/ pwm8_pins_a: pwm8-0 { pins { @@ -1869,6 +1985,21 @@ pins { }; }; =20 + /omit-if-no-ref/ + sai2a_pins_d: sai2a-3 { + pins { + pinmux =3D ; /* SAI2_SD_A */ + bias-disable; + }; + }; + + /omit-if-no-ref/ + sai2a_sleep_pins_d: sai2a-3 { + pins { + pinmux =3D ; /* SAI2_SD_A */ + }; + }; + /omit-if-no-ref/ sai2b_pins_a: sai2b-0 { pins1 { @@ -2856,6 +2987,39 @@ pins { }; }; =20 + /omit-if-no-ref/ + uart4_pins_f: uart4-5 { + pins1 { + pinmux =3D ; /* UART4_TX */ + bias-disable; + drive-push-pull; + slew-rate =3D <0>; + }; + pins2 { + pinmux =3D ; /* UART4_RX */ + bias-disable; + }; + }; + + /omit-if-no-ref/ + uart4_idle_pins_f: uart4-idle-5 { + pins1 { + pinmux =3D ; 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X-OriginatorOrg: phytec.fr X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Jul 2025 15:10:18.9543 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d1434a7d-4694-452f-0ce8-08ddbefab7be X-MS-Exchange-CrossTenant-Id: e609157c-80e2-446d-9be3-9c99c2399d29 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e609157c-80e2-446d-9be3-9c99c2399d29;Ip=[91.26.50.189];Helo=[Diagnostix.phytec.de] X-MS-Exchange-CrossTenant-AuthSource: DB1PEPF000509ED.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB8P195MB0711 Content-Type: text/plain; charset="utf-8" - UART4: "uart4_pins_a" pinmux option does not apply here, as PB9 should be used for UART4_TX instead of PG11 (PG11 is LCD_B3 on Sargas). Use "uart4_pins_f" instead. Also remove "pinctrl-3" which is useless (identical to "pinctrl-1"). - SAI2 A: "sai2a_pins_b" pinmux option does not apply here, as only PI6 is used for SAI2 A ("SAI2_SD_A"). Other pins of this group (PI7 and PD13) are not used for audio. Use "sai2a_sleep_pins_d" instead. Signed-off-by: Christophe Parant --- arch/arm/boot/dts/st/stm32mp15xx-phyboard-sargas.dtsi | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/st/stm32mp15xx-phyboard-sargas.dtsi b/arch/a= rm/boot/dts/st/stm32mp15xx-phyboard-sargas.dtsi index 2fdab99fc562..44f3aa1ddebf 100644 --- a/arch/arm/boot/dts/st/stm32mp15xx-phyboard-sargas.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15xx-phyboard-sargas.dtsi @@ -143,8 +143,8 @@ &sai2 { clocks =3D <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>; clock-names =3D "pclk", "x8k", "x11k"; pinctrl-names =3D "default", "sleep"; - pinctrl-0 =3D <&sai2a_pins_b>, <&sai2b_pins_d>; - pinctrl-1 =3D <&sai2a_sleep_pins_b>, <&sai2b_sleep_pins_d>; + pinctrl-0 =3D <&sai2a_pins_d>, <&sai2b_pins_d>; + pinctrl-1 =3D <&sai2a_sleep_pins_d>, <&sai2b_sleep_pins_d>; status =3D "okay"; }; =20 @@ -202,10 +202,9 @@ &spi1 { =20 &uart4 { pinctrl-names =3D "default", "sleep", "idle"; - pinctrl-0 =3D <&uart4_pins_a>; - pinctrl-1 =3D <&uart4_sleep_pins_a>; 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X-OriginatorOrg: phytec.fr X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Jul 2025 15:10:19.2371 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0ee9cb31-08c2-45ac-3281-08ddbefab7e9 X-MS-Exchange-CrossTenant-Id: e609157c-80e2-446d-9be3-9c99c2399d29 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e609157c-80e2-446d-9be3-9c99c2399d29;Ip=[91.26.50.189];Helo=[Diagnostix.phytec.de] X-MS-Exchange-CrossTenant-AuthSource: DB1PEPF000509ED.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DBAP195MB1018 Content-Type: text/plain; charset="utf-8" - Add missing chip select pin group in pinctrl. - Overwrite the memory map to the Flash device size (16MB) is necessary to avoid waste of virtual memory that will not be used. Without this modification, qspi probe fails because of ioremap error. Signed-off-by: Christophe Parant --- arch/arm/boot/dts/st/stm32mp15xx-phycore-som.dtsi | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/st/stm32mp15xx-phycore-som.dtsi b/arch/arm/b= oot/dts/st/stm32mp15xx-phycore-som.dtsi index 660cdc260963..72926c3de52c 100644 --- a/arch/arm/boot/dts/st/stm32mp15xx-phycore-som.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15xx-phycore-som.dtsi @@ -290,8 +290,14 @@ &pwr_regulators { =20 &qspi { pinctrl-names =3D "default", "sleep"; - pinctrl-0 =3D <&qspi_clk_pins_a &qspi_bk1_pins_a>; - pinctrl-1 =3D <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a>; + pinctrl-0 =3D <&qspi_clk_pins_a + &qspi_bk1_pins_a + &qspi_cs1_pins_a>; + pinctrl-1 =3D <&qspi_clk_sleep_pins_a + &qspi_bk1_sleep_pins_a + &qspi_cs1_sleep_pins_a>; + reg =3D <0x58003000 0x1000>, + <0x70000000 0x1000000>; status =3D "okay"; =20 flash0: flash@0 { --=20 2.34.1 From nobody Tue Oct 7 13:28:35 2025 Received: from EUR05-DB8-obe.outbound.protection.outlook.com (mail-db8eur05on2118.outbound.protection.outlook.com [40.107.20.118]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7DA632E7F00; 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X-OriginatorOrg: phytec.fr X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Jul 2025 15:10:20.4160 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 862a1b3c-dc57-4d42-1a88-08ddbefab89d X-MS-Exchange-CrossTenant-Id: e609157c-80e2-446d-9be3-9c99c2399d29 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e609157c-80e2-446d-9be3-9c99c2399d29;Ip=[91.26.50.189];Helo=[Diagnostix.phytec.de] X-MS-Exchange-CrossTenant-AuthSource: DB1PEPF000509ED.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PA3P195MB2815 Content-Type: text/plain; charset="utf-8" "memory" node is not necessary as the bootloader is taking care of passing the correct DDR size. However keep a dummy memory node with the minimum DDR size (512MB) with comment explaining that. Signed-off-by: Christophe Parant --- arch/arm/boot/dts/st/stm32mp15xx-phycore-som.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32mp15xx-phycore-som.dtsi b/arch/arm/b= oot/dts/st/stm32mp15xx-phycore-som.dtsi index 72926c3de52c..ce859b94ae26 100644 --- a/arch/arm/boot/dts/st/stm32mp15xx-phycore-som.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15xx-phycore-som.dtsi @@ -22,6 +22,15 @@ aliases { rtc1 =3D &rtc; }; =20 + /* + * Set the minimum memory size here and + * let the bootloader set the real size. + */ + memory@c0000000 { + device_type =3D "memory"; + reg =3D <0xc0000000 0x20000000>; + }; + reserved-memory { #address-cells =3D <1>; #size-cells =3D <1>; --=20 2.34.1 From nobody Tue Oct 7 13:28:35 2025 Received: from EUR05-AM6-obe.outbound.protection.outlook.com (mail-am6eur05on2125.outbound.protection.outlook.com [40.107.22.125]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9BD832E7F10; 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X-OriginatorOrg: phytec.fr X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Jul 2025 15:10:20.7616 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 177c95c1-f84f-4f5d-b0f2-08ddbefab8d1 X-MS-Exchange-CrossTenant-Id: e609157c-80e2-446d-9be3-9c99c2399d29 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e609157c-80e2-446d-9be3-9c99c2399d29;Ip=[91.26.50.189];Helo=[Diagnostix.phytec.de] X-MS-Exchange-CrossTenant-AuthSource: DB1PEPF000509ED.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9P195MB0999 Content-Type: text/plain; charset="utf-8" aliases are common to every phyboard-sargas version. So move it to the common phyboard dtsi file. Signed-off-by: Christophe Parant --- arch/arm/boot/dts/st/stm32mp157c-phyboard-sargas-rdk.dts | 9 --------- arch/arm/boot/dts/st/stm32mp15xx-phyboard-sargas.dtsi | 9 +++++++++ 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm/boot/dts/st/stm32mp157c-phyboard-sargas-rdk.dts b/arc= h/arm/boot/dts/st/stm32mp157c-phyboard-sargas-rdk.dts index 48adc3462958..f7c02a381304 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-phyboard-sargas-rdk.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-phyboard-sargas-rdk.dts @@ -16,15 +16,6 @@ / { model =3D "PHYTEC phyBOARD-Sargas STM32MP157C"; compatible =3D "phytec,phycore-stm32mp1-3", "phytec,phycore-stm32mp157c-som", "st,stm32mp157"; - - aliases { - mmc0 =3D &sdmmc1; - mmc1 =3D &sdmmc2; - mmc2 =3D &sdmmc3; - serial0 =3D &uart4; - serial1 =3D &usart3; - serial2 =3D &usart1; - }; }; =20 &cryp1 { diff --git a/arch/arm/boot/dts/st/stm32mp15xx-phyboard-sargas.dtsi b/arch/a= rm/boot/dts/st/stm32mp15xx-phyboard-sargas.dtsi index 44f3aa1ddebf..9578e78bcc1d 100644 --- a/arch/arm/boot/dts/st/stm32mp15xx-phyboard-sargas.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15xx-phyboard-sargas.dtsi @@ -12,6 +12,15 @@ #include =20 / { + aliases { + mmc0 =3D &sdmmc1; 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X-OriginatorOrg: phytec.fr X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Jul 2025 15:10:21.0490 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 478bc73b-4b22-4000-a9cf-08ddbefab8fd X-MS-Exchange-CrossTenant-Id: e609157c-80e2-446d-9be3-9c99c2399d29 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e609157c-80e2-446d-9be3-9c99c2399d29;Ip=[91.26.50.189];Helo=[Diagnostix.phytec.de] X-MS-Exchange-CrossTenant-AuthSource: DB1PEPF000509ED.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB4P195MB2018 Content-Type: text/plain; charset="utf-8" Following peripherals are optional on phyCORE-STM32MP15x following PHYTEC standard SoM variants: external RTC, EEPROM, SPI NOR. Also NAND (fmc) can be populated instead of eMMC (sdmmc2). So disable those peripherals on SoM dtsi file and enable them on board dts file. Additionally, enable by default the "DTS" SoC IP on common SoM dtsi file as it is not an optional IP in STM32MP15x SoC. Signed-off-by: Christophe Parant --- arch/arm/boot/dts/st/stm32mp157c-phyboard-sargas-rdk.dts | 8 -------- arch/arm/boot/dts/st/stm32mp15xx-phycore-som.dtsi | 9 ++++++++- 2 files changed, 8 insertions(+), 9 deletions(-) diff --git a/arch/arm/boot/dts/st/stm32mp157c-phyboard-sargas-rdk.dts b/arc= h/arm/boot/dts/st/stm32mp157c-phyboard-sargas-rdk.dts index f7c02a381304..c90b12a479c9 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-phyboard-sargas-rdk.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-phyboard-sargas-rdk.dts @@ -22,14 +22,6 @@ &cryp1 { status =3D "okay"; }; =20 -&dts { - status =3D "okay"; -}; - -&fmc { - status =3D "disabled"; -}; - &gpu { status =3D "okay"; }; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-phycore-som.dtsi b/arch/arm/b= oot/dts/st/stm32mp15xx-phycore-som.dtsi index ce859b94ae26..3f60f184978c 100644 --- a/arch/arm/boot/dts/st/stm32mp15xx-phycore-som.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15xx-phycore-som.dtsi @@ -265,11 +265,13 @@ i2c4_eeprom: eeprom@50 { compatible =3D "microchip,24c32", "atmel,24c32"; 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X-OriginatorOrg: phytec.fr X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Jul 2025 15:10:21.5162 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8e1e2e4d-d4f6-4e87-f1c0-08ddbefab944 X-MS-Exchange-CrossTenant-Id: e609157c-80e2-446d-9be3-9c99c2399d29 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e609157c-80e2-446d-9be3-9c99c2399d29;Ip=[91.26.50.189];Helo=[Diagnostix.phytec.de] X-MS-Exchange-CrossTenant-AuthSource: DB1PEPF000509ED.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB8P195MB0535 Content-Type: text/plain; charset="utf-8" - Remove "stm32-pinfunc.h" include as it is already include in "stm32mp15-pinctrl.dtsi" file. - reserved-memory: reorder the memory sections (lower to higher addresses). - Move vendor properties (go last). - Remove useless compatible values: - QSPI flash: remove the winbond compatible. jedec is enought as the NOR flahses are detectable. - EEPROM: "atmel,24c32" is enought. - Use uppercase for regulator-name properties. - In pmic node: use the names from the PHYTEC SoM schematics. - stmpe811 touch: fix dts schema to comply with st,stmpe.yaml. - Fix one "multiple blank lines" detected by checkpatch. Signed-off-by: Christophe Parant --- .../st/stm32mp157c-phyboard-sargas-rdk.dts | 1 - .../dts/st/stm32mp15xx-phyboard-sargas.dtsi | 13 ++-- .../boot/dts/st/stm32mp15xx-phycore-som.dtsi | 64 +++++++++---------- 3 files changed, 36 insertions(+), 42 deletions(-) diff --git a/arch/arm/boot/dts/st/stm32mp157c-phyboard-sargas-rdk.dts b/arc= h/arm/boot/dts/st/stm32mp157c-phyboard-sargas-rdk.dts index c90b12a479c9..c18a37266083 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-phyboard-sargas-rdk.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-phyboard-sargas-rdk.dts @@ -6,7 +6,6 @@ =20 /dts-v1/; =20 -#include #include "stm32mp157.dtsi" #include "stm32mp15xc.dtsi" #include "stm32mp15xx-phycore-som.dtsi" diff --git a/arch/arm/boot/dts/st/stm32mp15xx-phyboard-sargas.dtsi b/arch/a= rm/boot/dts/st/stm32mp15xx-phyboard-sargas.dtsi index 9578e78bcc1d..20684b497c99 100644 --- a/arch/arm/boot/dts/st/stm32mp15xx-phyboard-sargas.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15xx-phyboard-sargas.dtsi @@ -5,7 +5,6 @@ * Author: Dom VOVARD . */ =20 - #include #include #include @@ -101,13 +100,13 @@ touch@44 { interrupt-parent =3D <&gpioi>; vio-supply =3D <&v3v3>; vcc-supply =3D <&v3v3>; + st,sample-time =3D <4>; + st,mod-12b =3D <1>; + st,ref-sel =3D <0>; + st,adc-freq =3D <1>; =20 touchscreen { compatible =3D "st,stmpe-ts"; - st,sample-time =3D <4>; - st,mod-12b =3D <1>; - st,ref-sel =3D <0>; - st,adc-freq =3D <1>; st,ave-ctrl =3D <1>; st,touch-det-delay =3D <2>; st,settling =3D <2>; @@ -159,10 +158,10 @@ &sai2 { =20 &sai2a { dma-names =3D "rx"; - st,sync =3D <&sai2b 2>; clocks =3D <&rcc SAI2_K>, <&sai2b>; clock-names =3D "sai_ck", "MCLK"; #clock-cells =3D <0>; + st,sync =3D <&sai2b 2>; =20 sai2a_port: port { sai2a_endpoint: endpoint { @@ -195,9 +194,9 @@ &sdmmc1 { pinctrl-2 =3D <&sdmmc1_b4_sleep_pins_b>; cd-gpios =3D <&gpiof 3 GPIO_ACTIVE_LOW>; disable-wp; - st,neg-edge; bus-width =3D <4>; vmmc-supply =3D <&v3v3>; + st,neg-edge; status =3D "okay"; }; =20 diff --git a/arch/arm/boot/dts/st/stm32mp15xx-phycore-som.dtsi b/arch/arm/b= oot/dts/st/stm32mp15xx-phycore-som.dtsi index 3f60f184978c..0689967b8c56 100644 --- a/arch/arm/boot/dts/st/stm32mp15xx-phycore-som.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15xx-phycore-som.dtsi @@ -36,18 +36,6 @@ reserved-memory { #size-cells =3D <1>; ranges; =20 - retram: retram@38000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x38000000 0x10000>; - no-map; - }; - - mcuram: mcuram@30000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x30000000 0x40000>; - no-map; - }; - mcuram2: mcuram2@10000000 { compatible =3D "shared-dma-pool"; reg =3D <0x10000000 0x40000>; @@ -71,11 +59,22 @@ vdev0buffer: vdev0buffer@10042000 { reg =3D <0x10042000 0x4000>; no-map; }; + mcuram: mcuram@30000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x30000000 0x40000>; + no-map; + }; + + retram: retram@38000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x38000000 0x10000>; + no-map; + }; }; =20 regulator_vin: regulator { compatible =3D "regulator-fixed"; - regulator-name =3D "vin"; + regulator-name =3D "VIN"; regulator-min-microvolt =3D <5000000>; regulator-max-microvolt =3D <5000000>; regulator-always-on; @@ -102,11 +101,11 @@ phy0: ethernet-phy@1 { reg =3D <1>; interrupt-parent =3D <&gpiog>; interrupts =3D <12 IRQ_TYPE_EDGE_FALLING>; + enet-phy-lane-no-swap; ti,rx-internal-delay =3D ; ti,tx-internal-delay =3D ; ti,fifo-depth =3D ; ti,min-output-impedance; - enet-phy-lane-no-swap; ti,clk-output-sel =3D ; }; }; @@ -144,7 +143,7 @@ regulators { pwr_sw2-supply =3D <&bst_out>; =20 vddcore: buck1 { - regulator-name =3D "vddcore"; + regulator-name =3D "VDD_CORE"; regulator-min-microvolt =3D <1200000>; regulator-max-microvolt =3D <1350000>; regulator-always-on; @@ -152,7 +151,7 @@ vddcore: buck1 { }; =20 vdd_ddr: buck2 { - regulator-name =3D "vdd_ddr"; + regulator-name =3D "VDD_DDR"; regulator-min-microvolt =3D <1350000>; regulator-max-microvolt =3D <1350000>; regulator-always-on; @@ -160,7 +159,7 @@ vdd_ddr: buck2 { }; =20 vdd: buck3 { - regulator-name =3D "vdd"; + regulator-name =3D "VDD"; regulator-min-microvolt =3D <3300000>; regulator-max-microvolt =3D <3300000>; regulator-always-on; @@ -169,7 +168,7 @@ vdd: buck3 { }; =20 v3v3: buck4 { - regulator-name =3D "v3v3"; + regulator-name =3D "VDD_BUCK4"; regulator-min-microvolt =3D <3300000>; regulator-max-microvolt =3D <3300000>; regulator-always-on; @@ -177,7 +176,7 @@ v3v3: buck4 { }; =20 v1v8_audio: ldo1 { - regulator-name =3D "v1v8_audio"; + regulator-name =3D "VDD_LDO1"; regulator-min-microvolt =3D <1800000>; regulator-max-microvolt =3D <1800000>; regulator-always-on; @@ -186,7 +185,7 @@ v1v8_audio: ldo1 { }; =20 vdd_eth_2v5: ldo2 { - regulator-name =3D "dd_eth_2v5"; + regulator-name =3D "VDD_ETH_2V5"; regulator-min-microvolt =3D <2500000>; regulator-max-microvolt =3D <2500000>; regulator-always-on; @@ -195,7 +194,7 @@ vdd_eth_2v5: ldo2 { }; =20 vtt_ddr: ldo3 { - regulator-name =3D "vtt_ddr"; + regulator-name =3D "VTT_DDR"; regulator-min-microvolt =3D <500000>; regulator-max-microvolt =3D <750000>; regulator-always-on; @@ -203,12 +202,12 @@ vtt_ddr: ldo3 { }; =20 vdd_usb: ldo4 { - regulator-name =3D "vdd_usb"; + regulator-name =3D "VDD_USB"; interrupts =3D ; }; =20 vdda: ldo5 { - regulator-name =3D "vdda"; + regulator-name =3D "VDDA"; regulator-min-microvolt =3D <2900000>; regulator-max-microvolt =3D <2900000>; interrupts =3D ; @@ -216,7 +215,7 @@ vdda: ldo5 { }; =20 vdd_eth_1v0: ldo6 { - regulator-name =3D "vdd_eth_1v0"; + regulator-name =3D "VDD_ETH_1V0"; regulator-min-microvolt =3D <1000000>; regulator-max-microvolt =3D <1000000>; regulator-always-on; @@ -225,23 +224,23 @@ vdd_eth_1v0: ldo6 { }; =20 vref_ddr: vref_ddr { - regulator-name =3D "vref_ddr"; + regulator-name =3D "VDD_REFDDR"; regulator-always-on; }; =20 bst_out: boost { - regulator-name =3D "bst_out"; + regulator-name =3D "BST_OUT"; interrupts =3D ; }; =20 vbus_otg: pwr_sw1 { - regulator-name =3D "vbus_otg"; + regulator-name =3D "VBUS_OTG"; interrupts =3D ; regulator-active-discharge =3D <1>; }; =20 vbus_sw: pwr_sw2 { - regulator-name =3D "vbus_sw"; + regulator-name =3D "VBUS_SW"; interrupts =3D ; regulator-active-discharge =3D <1>; }; @@ -262,8 +261,7 @@ watchdog { }; =20 i2c4_eeprom: eeprom@50 { - compatible =3D "microchip,24c32", - "atmel,24c32"; + compatible =3D "atmel,24c32"; reg =3D <0x50>; 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X-OriginatorOrg: phytec.fr X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Jul 2025 15:10:24.1154 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b64c8d2f-5e5b-4502-6cae-08ddbefabad1 X-MS-Exchange-CrossTenant-Id: e609157c-80e2-446d-9be3-9c99c2399d29 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e609157c-80e2-446d-9be3-9c99c2399d29;Ip=[91.26.50.189];Helo=[Diagnostix.phytec.de] X-MS-Exchange-CrossTenant-AuthSource: DB1PEPF000509ED.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DU0P195MB1592 Content-Type: text/plain; charset="utf-8" - stm32mp15xx-phycore-som: add NAND device on FMC interface to support the SoM version equipped with NAND flash instead of eMMC. - stm32mp15xx-phyboard-sargas: define pinctrl for PWM5, LTDC and DCMI interfaces used on phyBOARD-Sargas. Those interfaces are not enabled by default as PHYTEC displays and PHYTEC cameras are enabled and configured throught device tree overlays. PWM5 is used for LCD backlight command. Signed-off-by: Christophe Parant --- .../dts/st/stm32mp15xx-phyboard-sargas.dtsi | 23 +++++++++++++++++++ .../boot/dts/st/stm32mp15xx-phycore-som.dtsi | 16 +++++++++++++ 2 files changed, 39 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32mp15xx-phyboard-sargas.dtsi b/arch/a= rm/boot/dts/st/stm32mp15xx-phyboard-sargas.dtsi index 20684b497c99..28a21dec9cd7 100644 --- a/arch/arm/boot/dts/st/stm32mp15xx-phyboard-sargas.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15xx-phyboard-sargas.dtsi @@ -260,3 +260,26 @@ &usbphyc_port0 { &usbphyc_port1 { phy-supply =3D <&vdd_usb>; }; + +&timers5 { + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + pwm5: pwm { + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&pwm5_pins_c>; + pinctrl-1 =3D <&pwm5_sleep_pins_c>; + }; +}; + +<dc { + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <<dc_pins_f>; + pinctrl-1 =3D <<dc_sleep_pins_f>; +}; + +&dcmi { + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&dcmi_pins_d>; + pinctrl-1 =3D <&dcmi_sleep_pins_d>; +}; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-phycore-som.dtsi b/arch/arm/b= oot/dts/st/stm32mp15xx-phycore-som.dtsi index 0689967b8c56..23db635c39a1 100644 --- a/arch/arm/boot/dts/st/stm32mp15xx-phycore-som.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15xx-phycore-som.dtsi @@ -345,3 +345,19 @@ &sdmmc2 { st,neg-edge; status =3D "disabled"; }; + +&fmc { + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&fmc_pins_a>; + pinctrl-1 =3D <&fmc_sleep_pins_a>; + status =3D "disabled"; + + nand-controller@4,0 { + nand0: nand@0 { + reg =3D <0>; + nand-on-flash-bbt; + nand-ecc-strength =3D <4>; + nand-ecc-step-size =3D <512>; + }; + }; +}; --=20 2.34.1