From nobody Tue Oct 7 13:28:35 2025 Received: from metis.whiteo.stw.pengutronix.de (metis.whiteo.stw.pengutronix.de [185.203.201.7]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8966F289368 for ; Wed, 9 Jul 2025 13:08:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.203.201.7 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752066490; cv=none; b=AaJ5hQXV0TFuEDnA/YyCGUw51mFzmEHkmKsxeA+DSsqmZQvuSHb0JYd/XVm8HYpD8amzy84rwyUZwLJTRLHZulebQ0JjO1mQ2wZRqf9IHThEbHyYv5MNLQ0D0EkirZzuPxlc0wdG4FnPiu0QuIqTwLZU2kdum7kM6I9s02vFi0w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752066490; c=relaxed/simple; bh=KbQkGauBnJ7Yg2RJHXECgDLTB81gGN+tu3f81Z/wcjM=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=mIf8LxtssRoM2z8JZca0Wuyv1keaO3cN2RtCvU4IIfbCK/riCbg+2cQ6CqksrVcuqob/suPV9CP6guW+N6e3j3Bt2navcFxTUE2s6/sQZj89wxFDWu6EQbgDbE+tlU/Ue5RA5vVJuKsFoYESW9ky4J8LgLV0770vsM+whXbNCzs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de; spf=pass smtp.mailfrom=pengutronix.de; arc=none smtp.client-ip=185.203.201.7 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pengutronix.de Received: from drehscheibe.grey.stw.pengutronix.de ([2a0a:edc0:0:c01:1d::a2]) by metis.whiteo.stw.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1uZUWj-00036o-Fp; Wed, 09 Jul 2025 15:07:57 +0200 Received: from dude04.red.stw.pengutronix.de ([2a0a:edc0:0:1101:1d::ac]) by drehscheibe.grey.stw.pengutronix.de with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.96) (envelope-from ) id 1uZUWi-007afS-2x; Wed, 09 Jul 2025 15:07:56 +0200 Received: from ore by dude04.red.stw.pengutronix.de with local (Exim 4.96) (envelope-from ) id 1uZUWi-00Gl9L-2h; Wed, 09 Jul 2025 15:07:56 +0200 From: Oleksij Rempel To: "David S. Miller" , Andrew Lunn , Eric Dumazet , Florian Fainelli , Jakub Kicinski , Paolo Abeni , Woojung Huh , Arun Ramadoss , Heiner Kallweit , Russell King , Yuiko Oshino Cc: Oleksij Rempel , kernel@pengutronix.de, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, UNGLinuxDriver@microchip.com, Phil Elwell Subject: [PATCH net v1 1/2] net: phy: microchip: Use genphy_soft_reset() to purge stale LPA bits Date: Wed, 9 Jul 2025 15:07:52 +0200 Message-Id: <20250709130753.3994461-2-o.rempel@pengutronix.de> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250709130753.3994461-1-o.rempel@pengutronix.de> References: <20250709130753.3994461-1-o.rempel@pengutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 2a0a:edc0:0:c01:1d::a2 X-SA-Exim-Mail-From: ore@pengutronix.de X-SA-Exim-Scanned: No (on metis.whiteo.stw.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Enable .soft_reset for the LAN88xx PHY driver by assigning genphy_soft_reset() to ensure that the phylib core performs a proper soft reset during reconfiguration. Previously, the driver left .soft_reset unimplemented, so calls to phy_init_hw() (e.g., from lan88xx_link_change_notify()) did not fully reset the PHY. As a result, stale contents in the Link Partner Ability (LPA) register could persist, causing the PHY to incorrectly report that the link partner advertised autonegotiation even when it did not. Using genphy_soft_reset() guarantees a clean reset of the PHY and corrects the false autoneg reporting in these scenarios. Fixes: ccb989e4d1ef ("net: phy: microchip: Reset LAN88xx PHY to ensure clea= n link state on LAN7800/7850") Signed-off-by: Oleksij Rempel Reviewed-by: Andrew Lunn --- drivers/net/phy/microchip.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/net/phy/microchip.c b/drivers/net/phy/microchip.c index 13570f628aa5..5e590b0a75e5 100644 --- a/drivers/net/phy/microchip.c +++ b/drivers/net/phy/microchip.c @@ -488,6 +488,7 @@ static struct phy_driver microchip_phy_driver[] =3D { .config_init =3D lan88xx_config_init, .config_aneg =3D lan88xx_config_aneg, .link_change_notify =3D lan88xx_link_change_notify, + .soft_reset =3D genphy_soft_reset, =20 /* Interrupt handling is broken, do not define related * functions to force polling. --=20 2.39.5 From nobody Tue Oct 7 13:28:35 2025 Received: from metis.whiteo.stw.pengutronix.de (metis.whiteo.stw.pengutronix.de [185.203.201.7]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D49C62DAFCB for ; Wed, 9 Jul 2025 13:08:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.203.201.7 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752066488; cv=none; b=eyVDwp71m/xNHf2Gw4dqxhEwe5QXVd5ec0PV7M+EDMAZGv08xKrIsxeD8Nrg+/LSJfHddQhLLjB8ySnq2kEmlBVFJjmJ1YA02SB48sVANE1Nzyy5yQrO75R2ko/K1prPtoi49vP/r1EfLUAihgzmg6x0yINv9APmEzvWL3jJCFA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752066488; c=relaxed/simple; bh=nsRb6Jt0ZvIj8IV577kGjE5cSbZ4oqA0SsnkIACHag0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=aG+Cg7jyhqVYWwVn7H8uG3lF/mhBUG27ASBKLWM9hziVv1UfsSAHte6AIiZxHhlXUB5LTGAKNw2V8pE6B2mUJZu+2W4BF+FF6+C8hMP2Gp7bw7ozFWZJ5kqW8JIBjHFxncgj2YKeEVjAKBCKbVKjGklMJe4Rf2ZLxF2SOzFF6vw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de; spf=pass smtp.mailfrom=pengutronix.de; arc=none smtp.client-ip=185.203.201.7 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pengutronix.de Received: from drehscheibe.grey.stw.pengutronix.de ([2a0a:edc0:0:c01:1d::a2]) by metis.whiteo.stw.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1uZUWj-00036p-Iw; Wed, 09 Jul 2025 15:07:57 +0200 Received: from dude04.red.stw.pengutronix.de ([2a0a:edc0:0:1101:1d::ac]) by drehscheibe.grey.stw.pengutronix.de with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.96) (envelope-from ) id 1uZUWj-007afV-1D; Wed, 09 Jul 2025 15:07:57 +0200 Received: from ore by dude04.red.stw.pengutronix.de with local (Exim 4.96) (envelope-from ) id 1uZUWj-00Gl9W-0x; Wed, 09 Jul 2025 15:07:57 +0200 From: Oleksij Rempel To: "David S. Miller" , Andrew Lunn , Eric Dumazet , Florian Fainelli , Jakub Kicinski , Paolo Abeni , Woojung Huh , Arun Ramadoss , Heiner Kallweit , Russell King , Yuiko Oshino Cc: Oleksij Rempel , kernel@pengutronix.de, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, UNGLinuxDriver@microchip.com, Phil Elwell Subject: [PATCH net v1 2/2] net: phy: microchip: limit 100M workaround to link-down events on LAN88xx Date: Wed, 9 Jul 2025 15:07:53 +0200 Message-Id: <20250709130753.3994461-3-o.rempel@pengutronix.de> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250709130753.3994461-1-o.rempel@pengutronix.de> References: <20250709130753.3994461-1-o.rempel@pengutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 2a0a:edc0:0:c01:1d::a2 X-SA-Exim-Mail-From: ore@pengutronix.de X-SA-Exim-Scanned: No (on metis.whiteo.stw.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Restrict the 100Mbit forced-mode workaround to link-down transitions only, to prevent repeated link reset cycles in certain configurations. The workaround was originally introduced to improve signal reliability when switching cables between long and short distances. It temporarily forces the PHY into 10 Mbps before returning to 100 Mbps. However, when used with autonegotiating link partners (e.g., Intel i350), executing this workaround on every link change can confuse the partner and cause constant renegotiation loops. This results in repeated link down/up transitions and the PHY never reaching a stable state. Limit the workaround to only run during the PHY_NOLINK state. This ensures it is triggered only once per link drop, avoiding disruptive toggling while still preserving its intended effect. Note: I am not able to reproduce the original issue that this workaround addresses. I can only confirm that 100 Mbit mode works correctly in my test setup. Based on code inspection, I assume the workaround aims to reset some internal state machine or signal block by toggling speeds. However, a PHY reset is already performed earlier in the function via phy_init_hw(), which may achieve a similar effect. Without a reproducer, I conservatively keep the workaround but restrict its conditions. Fixes: e57cf3639c32 ("net: lan78xx: fix accessing the LAN7800's internal ph= y specific registers from the MAC driver") Signed-off-by: Oleksij Rempel Reviewed-by: Andrew Lunn --- drivers/net/phy/microchip.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/phy/microchip.c b/drivers/net/phy/microchip.c index 5e590b0a75e5..dc8634e7bcbe 100644 --- a/drivers/net/phy/microchip.c +++ b/drivers/net/phy/microchip.c @@ -332,7 +332,7 @@ static void lan88xx_link_change_notify(struct phy_devic= e *phydev) * As workaround, set to 10 before setting to 100 * at forced 100 F/H mode. */ - if (!phydev->autoneg && phydev->speed =3D=3D 100) { + if (phydev->state =3D=3D PHY_NOLINK && !phydev->autoneg && phydev->speed = =3D=3D 100) { /* disable phy interrupt */ temp =3D phy_read(phydev, LAN88XX_INT_MASK); temp &=3D ~LAN88XX_INT_MASK_MDINTPIN_EN_; --=20 2.39.5