From nobody Tue Oct 7 15:01:45 2025 Received: from lelvem-ot02.ext.ti.com (lelvem-ot02.ext.ti.com [198.47.23.235]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 449B9292B3B; Wed, 9 Jul 2025 10:53:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.235 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752058419; cv=none; b=Td36ciyL91n/8gukb3zGCwOT/KvuhHue1FKYdhdSowT1BcJjjDJKyrYqt7wthzQ61RyU9Xxnv9UKLeKipWZXBX+OZakOd4Mr1PlVYwer0iIjIYf6P6VHBETuLvqgQQlJVjF5DLB9o3HpqoHumcQrpn4nWAOzhABLyZ+Icd+079w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752058419; c=relaxed/simple; bh=9ogdemP9YwJi2IIGadUBVWoXkxfDgSnCcmzpQzirtes=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=dYVcdfxk1y1AfXmDqT4S4xyfQ6kAkYLHPnSV0NAmN775kwtMs7pwIKA30/QBArytGlYG46HIVoUy7dH1JqY9eBA0Me3eF0VDULm0Kt/2UQj/N7gZ2kf75gOBGUKm6vQLoFUL1kxbtz/cy2VmSh6nw6UBirj+5P8zfJxG6M2c8qo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=Apgvx0LO; arc=none smtp.client-ip=198.47.23.235 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="Apgvx0LO" Received: from lelvem-sh01.itg.ti.com ([10.180.77.71]) by lelvem-ot02.ext.ti.com (8.15.2/8.15.2) with ESMTP id 569ArXOW1454784; Wed, 9 Jul 2025 05:53:33 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1752058413; bh=i3pKk5pK3Cqap6mdVi7c7bLd5ztwexMOYxTk4ib/do4=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Apgvx0LOD9UWr+NVPnhbo+LtbeLfMcEbxH4ccBL9zpgWCega3+d1Z95Rjc4sIa4Fs 50KKBWHbO8427S/RlkHIYed2DKPr3l5dt0W4xJc8KS2HygUYeXpPmyqyrEkXeDlJtJ yz9Kej4wCrnBFXRXD26rw0+2Ptab2EAgVs4sxdRI= Received: from DFLE110.ent.ti.com (dfle110.ent.ti.com [10.64.6.31]) by lelvem-sh01.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 569ArXXB061522 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Wed, 9 Jul 2025 05:53:33 -0500 Received: from DFLE114.ent.ti.com (10.64.6.35) by DFLE110.ent.ti.com (10.64.6.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Wed, 9 Jul 2025 05:53:33 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Wed, 9 Jul 2025 05:53:33 -0500 Received: from localhost (chintan-thinkstation-p360-tower.dhcp.ti.com [172.24.227.220]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 569ArWSF3808495; Wed, 9 Jul 2025 05:53:32 -0500 From: Chintan Vankar To: Conor Dooley , Krzysztof Kozlowski , Rob Herring , Tero Kristo , Vignesh Raghavendra , Nishanth Menon , CC: , , , , Roger Quadros Subject: [PATCH v6 3/4] arm64: dts: ti: k3-j722s-evm: Add bootph-all property to enable Ethernet boot Date: Wed, 9 Jul 2025 16:23:25 +0530 Message-ID: <20250709105326.232608-4-c-vankar@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250709105326.232608-1-c-vankar@ti.com> References: <20250709105326.232608-1-c-vankar@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Ethernet boot requires CPSW nodes to be present starting from R5 SPL stage. Add bootph-all property to required nodes to enable Ethernet boot for J722S-EVM. Reviewed-by: Roger Quadros Signed-off-by: Chintan Vankar --- Link to v5: https://lore.kernel.org/r/20250708084252.1028191-4-c-vankar@ti.com/ Changes from v5 to v6: - Added bootph-all property to cpsw_mac_syscon node. arch/arm64/boot/dts/ti/k3-j722s-evm.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts b/arch/arm64/boot/dts/= ti/k3-j722s-evm.dts index d0533723412a..9d8abfa9afd2 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts @@ -282,6 +282,14 @@ csi23_mux: mux-controller-1 { }; }; =20 +&cpsw_mac_syscon { + bootph-all; +}; + +&phy_gmii_sel { + bootph-all; +}; + &main_pmx0 { =20 main_mcan0_pins_default: main-mcan0-default-pins { @@ -346,6 +354,7 @@ mdio_pins_default: mdio-default-pins { J722S_IOPAD(0x0160, PIN_OUTPUT, 0) /* (AC24) MDIO0_MDC */ J722S_IOPAD(0x015c, PIN_INPUT, 0) /* (AD25) MDIO0_MDIO */ >; + bootph-all; }; =20 ospi0_pins_default: ospi0-default-pins { @@ -380,6 +389,7 @@ J722S_IOPAD(0x0140, PIN_OUTPUT, 0) /* (AF24) RGMII1_TD3= */ J722S_IOPAD(0x0130, PIN_OUTPUT, 0) /* (AG26) RGMII1_TXC */ J722S_IOPAD(0x012c, PIN_OUTPUT, 0) /* (AF25) RGMII1_TX_CTL */ >; + bootph-all; }; =20 main_usb1_pins_default: main-usb1-default-pins { @@ -424,6 +434,7 @@ &cpsw3g_mdio { =20 cpsw3g_phy0: ethernet-phy@0 { reg =3D <0>; + bootph-all; ti,rx-internal-delay =3D ; ti,fifo-depth =3D ; ti,min-output-impedance; @@ -434,6 +445,7 @@ &cpsw_port1 { phy-mode =3D "rgmii-rxid"; phy-handle =3D <&cpsw3g_phy0>; status =3D "okay"; + bootph-all; }; =20 &main_gpio1 { --=20 2.34.1