From nobody Tue Oct 7 13:23:05 2025 Received: from fllvem-ot03.ext.ti.com (fllvem-ot03.ext.ti.com [198.47.19.245]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E26D1280308; Wed, 9 Jul 2025 10:53:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.245 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752058417; cv=none; b=B7t5/3szWHgEV6bA6f2hIAyvjoFS27YZhngna6nywOEWXlEzoXzXx/Md7WsT7dc5bPLrhhm8h0H1d/qQ5z/L3BejRGQLUmu+wAJzmaI9WOrB2gNqnySE+UQIU6Hd90iTG6Fsc8U1q+ePhChoE4sEvzVTdiQ5pANmkQkIdp3/dzE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752058417; c=relaxed/simple; bh=OpD3DhqAMHs2IqwOrDdlVeFk4j94zpoRFyTcxS7Vfrg=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Xr5TusUpbpDoW0Vb6ShhY+7q+Uh4kFTRQO8R2RXIvAv6V4KUvGTBNbwN0Hqy0nzg6QYTWBj7T1/rf5ELpVe9ndvNN1CZXEpSwp6nfLRq3nf4Er2vg+EjMLAwKYCIbFAW91U1J4PfVyF0VlCCEhOyrFrWXwNOlb1stVcWsjg7e+E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=khRY5s+I; arc=none smtp.client-ip=198.47.19.245 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="khRY5s+I" Received: from lelvem-sh01.itg.ti.com ([10.180.77.71]) by fllvem-ot03.ext.ti.com (8.15.2/8.15.2) with ESMTP id 569ArUnO1190650; Wed, 9 Jul 2025 05:53:30 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1752058410; bh=NzUh5XvXydCYBtdAg71nfh4pU45qTnpiBTzZEZrJOAQ=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=khRY5s+IOjDXQ+1CG7EDAyeo9oSyjpDvcL23Dmq6E6yd1vjcjqII/dobZtvRESfLJ vdzgL43Y554i9kvGfmxupn0HvgcM1yReasA5gGg1alyxrGDdCQxptaLocf80SWm0UM 5WMhI8ATLzMOReUBJ0n0k0v80v5fMWDMF1c4hBB0= Received: from DLEE112.ent.ti.com (dlee112.ent.ti.com [157.170.170.23]) by lelvem-sh01.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 569ArUsU061501 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Wed, 9 Jul 2025 05:53:30 -0500 Received: from DLEE114.ent.ti.com (157.170.170.25) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Wed, 9 Jul 2025 05:53:30 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Wed, 9 Jul 2025 05:53:30 -0500 Received: from localhost (chintan-thinkstation-p360-tower.dhcp.ti.com [172.24.227.220]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 569ArTEI3808429; Wed, 9 Jul 2025 05:53:29 -0500 From: Chintan Vankar To: Conor Dooley , Krzysztof Kozlowski , Rob Herring , Tero Kristo , Vignesh Raghavendra , Nishanth Menon , CC: , , , Subject: [PATCH v6 1/4] arm64: dts: ti: k3-am68-sk-base-board: Add bootph-all property to enable Ethernet boot Date: Wed, 9 Jul 2025 16:23:23 +0530 Message-ID: <20250709105326.232608-2-c-vankar@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250709105326.232608-1-c-vankar@ti.com> References: <20250709105326.232608-1-c-vankar@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Ethernet boot requires CPSW nodes to be present starting from R5 SPL stage. Add bootph-all property to required nodes to enable Ethernet boot on SK-AM68. Reviewed-by: Siddharth Vadapalli Signed-off-by: Chintan Vankar --- Link to v5: https://lore.kernel.org/r/20250708084252.1028191-2-c-vankar@ti.com/ Changes from v5 to v6: - No changes. arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts b/arch/arm64/= boot/dts/ti/k3-am68-sk-base-board.dts index 5fa70a874d7b..e84c504c87d2 100644 --- a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts @@ -344,6 +344,7 @@ J721S2_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (E22) MCU_RG= MII1_TD3 */ J721S2_WKUP_IOPAD(0x018, PIN_OUTPUT, 0) /* (F21) MCU_RGMII1_TXC */ J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (F22) MCU_RGMII1_TX_CTL */ >; + bootph-all; }; =20 mcu_mdio_pins_default: mcu-mdio-default-pins { @@ -351,6 +352,7 @@ mcu_mdio_pins_default: mcu-mdio-default-pins { J721S2_WKUP_IOPAD(0x034, PIN_OUTPUT, 0) /* (A21) MCU_MDIO0_MDC */ J721S2_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (A22) MCU_MDIO0_MDIO */ >; + bootph-all; }; =20 mcu_mcan0_pins_default: mcu-mcan0-default-pins { @@ -412,6 +414,14 @@ J721S2_WKUP_IOPAD(0x000, PIN_INPUT, 7) /* (K26) WKUP_G= PIO0_49 */ }; }; =20 +&cpsw_mac_syscon { + bootph-all; +}; + +&phy_gmii_sel { + bootph-all; +}; + &main_gpio0 { status =3D "okay"; pinctrl-names =3D "default"; @@ -626,6 +636,7 @@ &mcu_cpsw { &davinci_mdio { phy0: ethernet-phy@0 { reg =3D <0>; + bootph-all; ti,rx-internal-delay =3D ; ti,fifo-depth =3D ; ti,min-output-impedance; @@ -635,6 +646,7 @@ phy0: ethernet-phy@0 { &cpsw_port1 { phy-mode =3D "rgmii-rxid"; phy-handle =3D <&phy0>; + bootph-all; }; =20 &mcu_mcan0 { --=20 2.34.1 From nobody Tue Oct 7 13:23:05 2025 Received: from lelvem-ot02.ext.ti.com (lelvem-ot02.ext.ti.com [198.47.23.235]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8540C9461; Wed, 9 Jul 2025 10:53:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" Ethernet boot requires CPSW nodes to be present starting from R5 SPL stage. Add bootph-all property to required nodes to enable Ethernet boot for AM62P5-SK. Reviewed-by: Roger Quadros Signed-off-by: Chintan Vankar --- Link to v5: https://lore.kernel.org/r/20250708084252.1028191-3-c-vankar@ti.com/ Changes from v5 to v6: - Added bootph-all property to cpsw_mac_syscon node. arch/arm64/boot/dts/ti/k3-am62p5-sk.dts | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts b/arch/arm64/boot/dts/= ti/k3-am62p5-sk.dts index 83c37de7d338..899da7896563 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts @@ -214,6 +214,14 @@ sound_master: simple-audio-card,codec { }; }; =20 +&cpsw_mac_syscon { + bootph-all; +}; + +&phy_gmii_sel { + bootph-all; +}; + &main_gpio0 { bootph-all; }; @@ -267,6 +275,7 @@ main_mdio1_pins_default: main-mdio1-default-pins { AM62PX_IOPAD(0x0160, PIN_OUTPUT, 0) /* (F17) MDIO0_MDC */ AM62PX_IOPAD(0x015c, PIN_INPUT, 0) /* (F16) MDIO0_MDIO */ >; + bootph-all; }; =20 main_mmc1_pins_default: main-mmc1-default-pins { @@ -547,6 +556,7 @@ &cpsw_port1 { phy-mode =3D "rgmii-rxid"; phy-handle =3D <&cpsw3g_phy0>; status =3D "okay"; + bootph-all; }; =20 &cpsw_port2 { @@ -562,6 +572,7 @@ &cpsw3g_mdio { =20 cpsw3g_phy0: ethernet-phy@0 { reg =3D <0>; + bootph-all; ti,rx-internal-delay =3D ; ti,fifo-depth =3D ; ti,min-output-impedance; --=20 2.34.1 From nobody Tue Oct 7 13:23:05 2025 Received: from lelvem-ot02.ext.ti.com (lelvem-ot02.ext.ti.com [198.47.23.235]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 449B9292B3B; Wed, 9 Jul 2025 10:53:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.235 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752058419; cv=none; b=Td36ciyL91n/8gukb3zGCwOT/KvuhHue1FKYdhdSowT1BcJjjDJKyrYqt7wthzQ61RyU9Xxnv9UKLeKipWZXBX+OZakOd4Mr1PlVYwer0iIjIYf6P6VHBETuLvqgQQlJVjF5DLB9o3HpqoHumcQrpn4nWAOzhABLyZ+Icd+079w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; 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Wed, 9 Jul 2025 05:53:33 -0500 Received: from localhost (chintan-thinkstation-p360-tower.dhcp.ti.com [172.24.227.220]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 569ArWSF3808495; Wed, 9 Jul 2025 05:53:32 -0500 From: Chintan Vankar To: Conor Dooley , Krzysztof Kozlowski , Rob Herring , Tero Kristo , Vignesh Raghavendra , Nishanth Menon , CC: , , , , Roger Quadros Subject: [PATCH v6 3/4] arm64: dts: ti: k3-j722s-evm: Add bootph-all property to enable Ethernet boot Date: Wed, 9 Jul 2025 16:23:25 +0530 Message-ID: <20250709105326.232608-4-c-vankar@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250709105326.232608-1-c-vankar@ti.com> References: <20250709105326.232608-1-c-vankar@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Ethernet boot requires CPSW nodes to be present starting from R5 SPL stage. Add bootph-all property to required nodes to enable Ethernet boot for J722S-EVM. Reviewed-by: Roger Quadros Signed-off-by: Chintan Vankar --- Link to v5: https://lore.kernel.org/r/20250708084252.1028191-4-c-vankar@ti.com/ Changes from v5 to v6: - Added bootph-all property to cpsw_mac_syscon node. arch/arm64/boot/dts/ti/k3-j722s-evm.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts b/arch/arm64/boot/dts/= ti/k3-j722s-evm.dts index d0533723412a..9d8abfa9afd2 100644 --- a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts @@ -282,6 +282,14 @@ csi23_mux: mux-controller-1 { }; }; =20 +&cpsw_mac_syscon { + bootph-all; +}; + +&phy_gmii_sel { + bootph-all; +}; + &main_pmx0 { =20 main_mcan0_pins_default: main-mcan0-default-pins { @@ -346,6 +354,7 @@ mdio_pins_default: mdio-default-pins { J722S_IOPAD(0x0160, PIN_OUTPUT, 0) /* (AC24) MDIO0_MDC */ J722S_IOPAD(0x015c, PIN_INPUT, 0) /* (AD25) MDIO0_MDIO */ >; + bootph-all; }; =20 ospi0_pins_default: ospi0-default-pins { @@ -380,6 +389,7 @@ J722S_IOPAD(0x0140, PIN_OUTPUT, 0) /* (AF24) RGMII1_TD3= */ J722S_IOPAD(0x0130, PIN_OUTPUT, 0) /* (AG26) RGMII1_TXC */ J722S_IOPAD(0x012c, PIN_OUTPUT, 0) /* (AF25) RGMII1_TX_CTL */ >; + bootph-all; }; =20 main_usb1_pins_default: main-usb1-default-pins { @@ -424,6 +434,7 @@ &cpsw3g_mdio { =20 cpsw3g_phy0: ethernet-phy@0 { reg =3D <0>; + bootph-all; ti,rx-internal-delay =3D ; ti,fifo-depth =3D ; ti,min-output-impedance; @@ -434,6 +445,7 @@ &cpsw_port1 { phy-mode =3D "rgmii-rxid"; phy-handle =3D <&cpsw3g_phy0>; status =3D "okay"; + bootph-all; }; =20 &main_gpio1 { --=20 2.34.1 From nobody Tue Oct 7 13:23:05 2025 Received: from lelvem-ot02.ext.ti.com (lelvem-ot02.ext.ti.com [198.47.23.235]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8EC50293B7A; Wed, 9 Jul 2025 10:53:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.235 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752058421; cv=none; b=CqgR9j0GccREwbUqS6vI43LMANq1WPbzRdr70jhEHuEhS1pHQZ4mAMfSabs9/EdpdzIcayz2yIW6YVSQM7VeHdGa6umHZZyG7tbRwPr5NnS9gPj7eH6/HABM4BLxvVuhna/Mo0hV3ftEy/txpkwpffLozD85kN00NmU6TU3GaUQ= ARC-Message-Signature: i=1; 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Wed, 9 Jul 2025 05:53:34 -0500 Received: from localhost (chintan-thinkstation-p360-tower.dhcp.ti.com [172.24.227.220]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 569ArX7n3516423; Wed, 9 Jul 2025 05:53:34 -0500 From: Chintan Vankar To: Conor Dooley , Krzysztof Kozlowski , Rob Herring , Tero Kristo , Vignesh Raghavendra , Nishanth Menon , CC: , , , Subject: [PATCH v6 4/4] arm64: dts: ti: k3-am69-sk: Add bootph-all property to enable Ethernet boot Date: Wed, 9 Jul 2025 16:23:26 +0530 Message-ID: <20250709105326.232608-5-c-vankar@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250709105326.232608-1-c-vankar@ti.com> References: <20250709105326.232608-1-c-vankar@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Ethernet boot requires CPSW nodes to be present starting from R5 SPL stage. Add bootph-all property to required nodes to enable Ethernet boot for SK-AM69. Reviewed-by: Siddharth Vadapalli Signed-off-by: Chintan Vankar --- Link to v5: https://lore.kernel.org/r/20250708084252.1028191-5-c-vankar@ti.com/ Changes from v5 to v6: - Added bootph-all property to cpsw_mac_syscon node. - Corrected "bootph-all" which was misspelled in previous version. arch/arm64/boot/dts/ti/k3-am69-sk.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am69-sk.dts b/arch/arm64/boot/dts/ti= /k3-am69-sk.dts index f28375629739..a09dcb812648 100644 --- a/arch/arm64/boot/dts/ti/k3-am69-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am69-sk.dts @@ -568,6 +568,7 @@ J784S4_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (E38) MCU_RG= MII1_TD3 */ J784S4_WKUP_IOPAD(0x018, PIN_OUTPUT, 0) /* (E36) MCU_RGMII1_TXC */ J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (C38) MCU_RGMII1_TX_CTL */ >; + bootph-all; }; =20 mcu_mdio_pins_default: mcu-mdio-default-pins { @@ -575,6 +576,7 @@ mcu_mdio_pins_default: mcu-mdio-default-pins { J784S4_WKUP_IOPAD(0x034, PIN_OUTPUT, 0) /* (A36) MCU_MDIO0_MDC */ J784S4_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (B35) MCU_MDIO0_MDIO */ >; + bootph-all; }; =20 mcu_rpi_hdr1_gpio0_pins_default: mcu-rpi-hdr1-gpio0-default-pins { @@ -630,6 +632,14 @@ J784S4_WKUP_IOPAD(0x0, PIN_INPUT, 7) /* (M33) WKUP_GPI= O0_49 */ }; }; =20 +&cpsw_mac_syscon { + bootph-all; +}; + +&phy_gmii_sel { + bootph-all; +}; + &mailbox0_cluster0 { status =3D "okay"; interrupts =3D <436>; @@ -968,6 +978,7 @@ &mcu_cpsw { &davinci_mdio { mcu_phy0: ethernet-phy@0 { reg =3D <0>; + bootph-all; ti,rx-internal-delay =3D ; ti,fifo-depth =3D ; ti,min-output-impedance; @@ -978,6 +989,7 @@ &mcu_cpsw_port1 { status =3D "okay"; phy-mode =3D "rgmii-rxid"; phy-handle =3D <&mcu_phy0>; + bootph-all; }; =20 &mcu_r5fss0_core0 { --=20 2.34.1