From nobody Tue Oct 7 14:06:29 2025 Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 17CA2223DD1; Wed, 9 Jul 2025 08:02:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=114.242.206.163 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752048162; cv=none; b=UpiLE93zYdzVZ05HEJbv1QW+LwFCZrpC7QSSJJQyieSjwl/z8VjEUSC8CK4XGNbIT6k8sUeH5VG4jsSujM+KtMA6DYk/hBiTWaMc7gd4Pd/LsIZArdTHgZF5JQdh7Mss+VYDw2tpKK6LAAHT1DMR91Hb9qAB59SIy2/eWsXW1MM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752048162; c=relaxed/simple; bh=BD/U6Gb7mKOZ/jRgYkNjVnDyOwfa/V4wS7qRfOnb0cM=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=bKWqyH6DI82ibkuCUSZc1rCb8V6ce7h7zUrHSpvqrMAb9m499seZIe596R7Petxk3oB4SdB0NeNz0Ne1csfG+d14hxq0zTXcoligr1dghEVv6oPaAYFmH3oBeJ3+X3eR7peqNFItzCdN/fs2oTUx92E2iuTK22EAVyccsXV16II= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn; spf=pass smtp.mailfrom=loongson.cn; arc=none smtp.client-ip=114.242.206.163 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=loongson.cn Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8CxG6waIm5oUiklAQ--.38583S3; Wed, 09 Jul 2025 16:02:34 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJBxpeQZIm5oS6cPAA--.24964S3; Wed, 09 Jul 2025 16:02:34 +0800 (CST) From: Bibo Mao To: Tianrui Zhao , Huacai Chen , Xianglai Li Cc: kvm@vger.kernel.org, loongarch@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH v6 1/8] LoongArch: KVM: Use standard bitops API with eiointc Date: Wed, 9 Jul 2025 16:02:26 +0800 Message-Id: <20250709080233.3948503-2-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250709080233.3948503-1-maobibo@loongson.cn> References: <20250709080233.3948503-1-maobibo@loongson.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJBxpeQZIm5oS6cPAA--.24964S3 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Content-Type: text/plain; charset="utf-8" Standard bitops APIs such test_bit() is used here, rather than manually calculate the offset and mask. Also use non-atomic API __set_bit() and __clear_bit() rather than set_bit() and clear_bit(), since global spinlock is held already. Signed-off-by: Bibo Mao --- arch/loongarch/kvm/intc/eiointc.c | 27 +++++++++++---------------- 1 file changed, 11 insertions(+), 16 deletions(-) diff --git a/arch/loongarch/kvm/intc/eiointc.c b/arch/loongarch/kvm/intc/ei= ointc.c index a75f865d6fb9..3cf9894999da 100644 --- a/arch/loongarch/kvm/intc/eiointc.c +++ b/arch/loongarch/kvm/intc/eiointc.c @@ -9,7 +9,7 @@ =20 static void eiointc_set_sw_coreisr(struct loongarch_eiointc *s) { - int ipnum, cpu, cpuid, irq_index, irq_mask, irq; + int ipnum, cpu, cpuid, irq; struct kvm_vcpu *vcpu; =20 for (irq =3D 0; irq < EIOINTC_IRQS; irq++) { @@ -18,8 +18,6 @@ static void eiointc_set_sw_coreisr(struct loongarch_eioin= tc *s) ipnum =3D count_trailing_zeros(ipnum); ipnum =3D (ipnum >=3D 0 && ipnum < 4) ? ipnum : 0; } - irq_index =3D irq / 32; - irq_mask =3D BIT(irq & 0x1f); =20 cpuid =3D s->coremap.reg_u8[irq]; vcpu =3D kvm_get_vcpu_by_cpuid(s->kvm, cpuid); @@ -27,16 +25,16 @@ static void eiointc_set_sw_coreisr(struct loongarch_eio= intc *s) continue; =20 cpu =3D vcpu->vcpu_id; - if (!!(s->coreisr.reg_u32[cpu][irq_index] & irq_mask)) - set_bit(irq, s->sw_coreisr[cpu][ipnum]); + if (test_bit(irq, (unsigned long *)s->coreisr.reg_u32[cpu])) + __set_bit(irq, s->sw_coreisr[cpu][ipnum]); else - clear_bit(irq, s->sw_coreisr[cpu][ipnum]); + __clear_bit(irq, s->sw_coreisr[cpu][ipnum]); } } =20 static void eiointc_update_irq(struct loongarch_eiointc *s, int irq, int l= evel) { - int ipnum, cpu, found, irq_index, irq_mask; + int ipnum, cpu, found; struct kvm_vcpu *vcpu; struct kvm_interrupt vcpu_irq; =20 @@ -48,19 +46,16 @@ static void eiointc_update_irq(struct loongarch_eiointc= *s, int irq, int level) =20 cpu =3D s->sw_coremap[irq]; vcpu =3D kvm_get_vcpu(s->kvm, cpu); - irq_index =3D irq / 32; - irq_mask =3D BIT(irq & 0x1f); - if (level) { /* if not enable return false */ - if (((s->enable.reg_u32[irq_index]) & irq_mask) =3D=3D 0) + if (!test_bit(irq, (unsigned long *)s->enable.reg_u32)) return; - s->coreisr.reg_u32[cpu][irq_index] |=3D irq_mask; + __set_bit(irq, (unsigned long *)s->coreisr.reg_u32[cpu]); found =3D find_first_bit(s->sw_coreisr[cpu][ipnum], EIOINTC_IRQS); - set_bit(irq, s->sw_coreisr[cpu][ipnum]); + __set_bit(irq, s->sw_coreisr[cpu][ipnum]); } else { - s->coreisr.reg_u32[cpu][irq_index] &=3D ~irq_mask; - clear_bit(irq, s->sw_coreisr[cpu][ipnum]); + __clear_bit(irq, (unsigned long *)s->coreisr.reg_u32[cpu]); + __clear_bit(irq, s->sw_coreisr[cpu][ipnum]); found =3D find_first_bit(s->sw_coreisr[cpu][ipnum], EIOINTC_IRQS); } =20 @@ -110,8 +105,8 @@ void eiointc_set_irq(struct loongarch_eiointc *s, int i= rq, int level) unsigned long flags; unsigned long *isr =3D (unsigned long *)s->isr.reg_u8; =20 - level ? set_bit(irq, isr) : clear_bit(irq, isr); spin_lock_irqsave(&s->lock, flags); + level ? __set_bit(irq, isr) : __clear_bit(irq, isr); eiointc_update_irq(s, irq, level); spin_unlock_irqrestore(&s->lock, flags); } --=20 2.39.3 From nobody Tue Oct 7 14:06:29 2025 Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 7C2992749DC; Wed, 9 Jul 2025 08:02:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=114.242.206.163 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752048168; cv=none; b=rr8kroxpdCKltL1RjZhMOvDz3VYR5szPUUsUVv18HFWsGInetu9JMekNYbxCZd7ilTQ87ahognIXHXDpHYeTWfRkTks5Xxy2LI2HX4cfnE/wKnWv9HWGWfzngYWPW5Kml8cR6cRdLJF/HYkC4frKT+J64j0swFe3d0eR1lJxb+8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752048168; c=relaxed/simple; bh=o4TIx92RBZnLsQZf5EAsiMP4FKhwveOeG+D2/fxYzmQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=VylOGSSBq1aqmElgR7pcgiHPInoNZDJa0bnxYCg5GmV/0IXYRUoNJYgTtUXyePPChxgObnnbZ+mCE9FD+7QkoadBZDdlDU6r7Oba8zJ8Pq4jt14zWJdX8xHWR+ReJkIUjxx7qO6Yc+1z8XR9YFpJlWiX1LPAuxhU675V+SpqXII= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn; spf=pass smtp.mailfrom=loongson.cn; arc=none smtp.client-ip=114.242.206.163 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=loongson.cn Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8CxqmobIm5oVSklAQ--.38718S3; Wed, 09 Jul 2025 16:02:35 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJBxpeQZIm5oS6cPAA--.24964S4; Wed, 09 Jul 2025 16:02:34 +0800 (CST) From: Bibo Mao To: Tianrui Zhao , Huacai Chen , Xianglai Li Cc: kvm@vger.kernel.org, loongarch@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH v6 2/8] LoongArch: KVM: Remove unused parameter len Date: Wed, 9 Jul 2025 16:02:27 +0800 Message-Id: <20250709080233.3948503-3-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250709080233.3948503-1-maobibo@loongson.cn> References: <20250709080233.3948503-1-maobibo@loongson.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJBxpeQZIm5oS6cPAA--.24964S4 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Content-Type: text/plain; charset="utf-8" Parameter len is unused in some functions with eiointc emulation driver, remove it here. Signed-off-by: Bibo Mao --- arch/loongarch/kvm/intc/eiointc.c | 32 +++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/arch/loongarch/kvm/intc/eiointc.c b/arch/loongarch/kvm/intc/ei= ointc.c index 3cf9894999da..acd975ce9608 100644 --- a/arch/loongarch/kvm/intc/eiointc.c +++ b/arch/loongarch/kvm/intc/eiointc.c @@ -131,7 +131,7 @@ static inline void eiointc_enable_irq(struct kvm_vcpu *= vcpu, } =20 static int loongarch_eiointc_readb(struct kvm_vcpu *vcpu, struct loongarch= _eiointc *s, - gpa_t addr, int len, void *val) + gpa_t addr, void *val) { int index, ret =3D 0; u8 data =3D 0; @@ -173,7 +173,7 @@ static int loongarch_eiointc_readb(struct kvm_vcpu *vcp= u, struct loongarch_eioin } =20 static int loongarch_eiointc_readw(struct kvm_vcpu *vcpu, struct loongarch= _eiointc *s, - gpa_t addr, int len, void *val) + gpa_t addr, void *val) { int index, ret =3D 0; u16 data =3D 0; @@ -215,7 +215,7 @@ static int loongarch_eiointc_readw(struct kvm_vcpu *vcp= u, struct loongarch_eioin } =20 static int loongarch_eiointc_readl(struct kvm_vcpu *vcpu, struct loongarch= _eiointc *s, - gpa_t addr, int len, void *val) + gpa_t addr, void *val) { int index, ret =3D 0; u32 data =3D 0; @@ -257,7 +257,7 @@ static int loongarch_eiointc_readl(struct kvm_vcpu *vcp= u, struct loongarch_eioin } =20 static int loongarch_eiointc_readq(struct kvm_vcpu *vcpu, struct loongarch= _eiointc *s, - gpa_t addr, int len, void *val) + gpa_t addr, void *val) { int index, ret =3D 0; u64 data =3D 0; @@ -320,16 +320,16 @@ static int kvm_eiointc_read(struct kvm_vcpu *vcpu, spin_lock_irqsave(&eiointc->lock, flags); switch (len) { case 1: - ret =3D loongarch_eiointc_readb(vcpu, eiointc, addr, len, val); + ret =3D loongarch_eiointc_readb(vcpu, eiointc, addr, val); break; case 2: - ret =3D loongarch_eiointc_readw(vcpu, eiointc, addr, len, val); + ret =3D loongarch_eiointc_readw(vcpu, eiointc, addr, val); break; case 4: - ret =3D loongarch_eiointc_readl(vcpu, eiointc, addr, len, val); + ret =3D loongarch_eiointc_readl(vcpu, eiointc, addr, val); break; case 8: - ret =3D loongarch_eiointc_readq(vcpu, eiointc, addr, len, val); + ret =3D loongarch_eiointc_readq(vcpu, eiointc, addr, val); break; default: WARN_ONCE(1, "%s: Abnormal address access: addr 0x%llx, size %d\n", @@ -342,7 +342,7 @@ static int kvm_eiointc_read(struct kvm_vcpu *vcpu, =20 static int loongarch_eiointc_writeb(struct kvm_vcpu *vcpu, struct loongarch_eiointc *s, - gpa_t addr, int len, const void *val) + gpa_t addr, const void *val) { int index, irq, bits, ret =3D 0; u8 cpu; @@ -421,7 +421,7 @@ static int loongarch_eiointc_writeb(struct kvm_vcpu *vc= pu, =20 static int loongarch_eiointc_writew(struct kvm_vcpu *vcpu, struct loongarch_eiointc *s, - gpa_t addr, int len, const void *val) + gpa_t addr, const void *val) { int i, index, irq, bits, ret =3D 0; u8 cpu; @@ -506,7 +506,7 @@ static int loongarch_eiointc_writew(struct kvm_vcpu *vc= pu, =20 static int loongarch_eiointc_writel(struct kvm_vcpu *vcpu, struct loongarch_eiointc *s, - gpa_t addr, int len, const void *val) + gpa_t addr, const void *val) { int i, index, irq, bits, ret =3D 0; u8 cpu; @@ -591,7 +591,7 @@ static int loongarch_eiointc_writel(struct kvm_vcpu *vc= pu, =20 static int loongarch_eiointc_writeq(struct kvm_vcpu *vcpu, struct loongarch_eiointc *s, - gpa_t addr, int len, const void *val) + gpa_t addr, const void *val) { int i, index, irq, bits, ret =3D 0; u8 cpu; @@ -696,16 +696,16 @@ static int kvm_eiointc_write(struct kvm_vcpu *vcpu, spin_lock_irqsave(&eiointc->lock, flags); switch (len) { case 1: - ret =3D loongarch_eiointc_writeb(vcpu, eiointc, addr, len, val); + ret =3D loongarch_eiointc_writeb(vcpu, eiointc, addr, val); break; case 2: - ret =3D loongarch_eiointc_writew(vcpu, eiointc, addr, len, val); + ret =3D loongarch_eiointc_writew(vcpu, eiointc, addr, val); break; case 4: - ret =3D loongarch_eiointc_writel(vcpu, eiointc, addr, len, val); + ret =3D loongarch_eiointc_writel(vcpu, eiointc, addr, val); break; case 8: - ret =3D loongarch_eiointc_writeq(vcpu, eiointc, addr, len, val); + ret =3D loongarch_eiointc_writeq(vcpu, eiointc, addr, val); break; default: WARN_ONCE(1, "%s: Abnormal address access: addr 0x%llx, size %d\n", --=20 2.39.3 From nobody Tue Oct 7 14:06:29 2025 Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 840652192F1; Wed, 9 Jul 2025 08:02:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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spf=pass smtp.mailfrom=loongson.cn Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8AxHHIcIm5oWSklAQ--.13802S3; Wed, 09 Jul 2025 16:02:36 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJBxpeQZIm5oS6cPAA--.24964S5; Wed, 09 Jul 2025 16:02:35 +0800 (CST) From: Bibo Mao To: Tianrui Zhao , Huacai Chen , Xianglai Li Cc: kvm@vger.kernel.org, loongarch@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH v6 3/8] LoongArch: KVM: Add stat information with kernel irqchip Date: Wed, 9 Jul 2025 16:02:28 +0800 Message-Id: <20250709080233.3948503-4-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250709080233.3948503-1-maobibo@loongson.cn> References: <20250709080233.3948503-1-maobibo@loongson.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJBxpeQZIm5oS6cPAA--.24964S5 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Content-Type: text/plain; charset="utf-8" Move stat information about kernel irqchip from VM to vCPU, since all vm exiting events should be vCPU relative. And also add entry with structure kvm_vcpu_stats_desc[], so that it can display with directory /sys/kernel/debug/kvm. Signed-off-by: Bibo Mao --- arch/loongarch/include/asm/kvm_host.h | 12 ++++++------ arch/loongarch/kvm/intc/eiointc.c | 4 ++-- arch/loongarch/kvm/intc/ipi.c | 28 ++++----------------------- arch/loongarch/kvm/intc/pch_pic.c | 4 ++-- arch/loongarch/kvm/vcpu.c | 8 +++++++- 5 files changed, 21 insertions(+), 35 deletions(-) diff --git a/arch/loongarch/include/asm/kvm_host.h b/arch/loongarch/include= /asm/kvm_host.h index a3c4cc46c892..0cecbd038bb3 100644 --- a/arch/loongarch/include/asm/kvm_host.h +++ b/arch/loongarch/include/asm/kvm_host.h @@ -50,12 +50,6 @@ struct kvm_vm_stat { struct kvm_vm_stat_generic generic; u64 pages; u64 hugepages; - u64 ipi_read_exits; - u64 ipi_write_exits; - u64 eiointc_read_exits; - u64 eiointc_write_exits; - u64 pch_pic_read_exits; - u64 pch_pic_write_exits; }; =20 struct kvm_vcpu_stat { @@ -65,6 +59,12 @@ struct kvm_vcpu_stat { u64 cpucfg_exits; u64 signal_exits; u64 hypercall_exits; + u64 ipi_read_exits; + u64 ipi_write_exits; + u64 eiointc_read_exits; + u64 eiointc_write_exits; + u64 pch_pic_read_exits; + u64 pch_pic_write_exits; }; =20 #define KVM_MEM_HUGEPAGE_CAPABLE (1UL << 0) diff --git a/arch/loongarch/kvm/intc/eiointc.c b/arch/loongarch/kvm/intc/ei= ointc.c index acd975ce9608..92bae1dea8eb 100644 --- a/arch/loongarch/kvm/intc/eiointc.c +++ b/arch/loongarch/kvm/intc/eiointc.c @@ -316,7 +316,7 @@ static int kvm_eiointc_read(struct kvm_vcpu *vcpu, return -EINVAL; } =20 - vcpu->kvm->stat.eiointc_read_exits++; + vcpu->stat.eiointc_read_exits++; spin_lock_irqsave(&eiointc->lock, flags); switch (len) { case 1: @@ -692,7 +692,7 @@ static int kvm_eiointc_write(struct kvm_vcpu *vcpu, return -EINVAL; } =20 - vcpu->kvm->stat.eiointc_write_exits++; + vcpu->stat.eiointc_write_exits++; spin_lock_irqsave(&eiointc->lock, flags); switch (len) { case 1: diff --git a/arch/loongarch/kvm/intc/ipi.c b/arch/loongarch/kvm/intc/ipi.c index fe734dc062ed..e658d5b37c04 100644 --- a/arch/loongarch/kvm/intc/ipi.c +++ b/arch/loongarch/kvm/intc/ipi.c @@ -268,36 +268,16 @@ static int kvm_ipi_read(struct kvm_vcpu *vcpu, struct kvm_io_device *dev, gpa_t addr, int len, void *val) { - int ret; - struct loongarch_ipi *ipi; - - ipi =3D vcpu->kvm->arch.ipi; - if (!ipi) { - kvm_err("%s: ipi irqchip not valid!\n", __func__); - return -EINVAL; - } - ipi->kvm->stat.ipi_read_exits++; - ret =3D loongarch_ipi_readl(vcpu, addr, len, val); - - return ret; + vcpu->stat.ipi_read_exits++; + return loongarch_ipi_readl(vcpu, addr, len, val); } =20 static int kvm_ipi_write(struct kvm_vcpu *vcpu, struct kvm_io_device *dev, gpa_t addr, int len, const void *val) { - int ret; - struct loongarch_ipi *ipi; - - ipi =3D vcpu->kvm->arch.ipi; - if (!ipi) { - kvm_err("%s: ipi irqchip not valid!\n", __func__); - return -EINVAL; - } - ipi->kvm->stat.ipi_write_exits++; - ret =3D loongarch_ipi_writel(vcpu, addr, len, val); - - return ret; + vcpu->stat.ipi_write_exits++; + return loongarch_ipi_writel(vcpu, addr, len, val); } =20 static const struct kvm_io_device_ops kvm_ipi_ops =3D { diff --git a/arch/loongarch/kvm/intc/pch_pic.c b/arch/loongarch/kvm/intc/pc= h_pic.c index 08fce845f668..6f00ffe05c54 100644 --- a/arch/loongarch/kvm/intc/pch_pic.c +++ b/arch/loongarch/kvm/intc/pch_pic.c @@ -196,7 +196,7 @@ static int kvm_pch_pic_read(struct kvm_vcpu *vcpu, } =20 /* statistics of pch pic reading */ - vcpu->kvm->stat.pch_pic_read_exits++; + vcpu->stat.pch_pic_read_exits++; ret =3D loongarch_pch_pic_read(s, addr, len, val); =20 return ret; @@ -303,7 +303,7 @@ static int kvm_pch_pic_write(struct kvm_vcpu *vcpu, } =20 /* statistics of pch pic writing */ - vcpu->kvm->stat.pch_pic_write_exits++; + vcpu->stat.pch_pic_write_exits++; ret =3D loongarch_pch_pic_write(s, addr, len, val); =20 return ret; diff --git a/arch/loongarch/kvm/vcpu.c b/arch/loongarch/kvm/vcpu.c index 5af32ec62cb1..d1b8c50941ca 100644 --- a/arch/loongarch/kvm/vcpu.c +++ b/arch/loongarch/kvm/vcpu.c @@ -20,7 +20,13 @@ const struct _kvm_stats_desc kvm_vcpu_stats_desc[] =3D { STATS_DESC_COUNTER(VCPU, idle_exits), STATS_DESC_COUNTER(VCPU, cpucfg_exits), STATS_DESC_COUNTER(VCPU, signal_exits), - STATS_DESC_COUNTER(VCPU, hypercall_exits) + STATS_DESC_COUNTER(VCPU, hypercall_exits), + STATS_DESC_COUNTER(VCPU, ipi_read_exits), + STATS_DESC_COUNTER(VCPU, ipi_write_exits), + STATS_DESC_COUNTER(VCPU, eiointc_read_exits), + STATS_DESC_COUNTER(VCPU, eiointc_write_exits), + STATS_DESC_COUNTER(VCPU, pch_pic_read_exits), + STATS_DESC_COUNTER(VCPU, pch_pic_write_exits) }; =20 const struct kvm_stats_header kvm_vcpu_stats_header =3D { --=20 2.39.3 From nobody Tue Oct 7 14:06:29 2025 Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 18A6222DA0B; Wed, 9 Jul 2025 08:04:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=114.242.206.163 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752048268; cv=none; b=MiZe0Hi2UpTcDyOocawgIxjbwPOlrmJBYuxC1P8Vv3UxsaArj7Z4EdHMG5zVIlY9u1/yQc+IhfWazZAb+xQgrJkBtFGZBwyWsSrFVDcTK9Q6PoSvJGPiOHJy9C/bWb5R3ICuQFkeKD6c1BDiOYxDyShUHvVjFRoKCicKAqosRaU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752048268; c=relaxed/simple; bh=ryb6hx0FWcCXe6vAqcJ437xJ27ug4a9xTIatX/wE6HU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=XdCGV2ZTVkcs+ae2QuYWJCQ4SkZeHAh5JSJ4lHJRrXv4KduKSUlvXbGLmHh6cPx433QaLXyuycMo8MTRa8udb2GYAtKBIr7lAavoTG6wzDQW2JmGSqMono00Hhdg9ktPOws1SB/xlca9UbW4rsV77CJcwbNBqgNXKPTWRe0F42o= ARC-Authentication-Results: i=1; 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charset="utf-8" IOCSR instruction supports 1/2/4/8 bytes access, len must be 1/2/4/8 bytes from iocsr exit emulation function kvm_emu_iocsr(), remove the default case in switch case statements. Signed-off-by: Bibo Mao --- arch/loongarch/kvm/intc/eiointc.c | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/arch/loongarch/kvm/intc/eiointc.c b/arch/loongarch/kvm/intc/ei= ointc.c index 92bae1dea8eb..137cd3adca80 100644 --- a/arch/loongarch/kvm/intc/eiointc.c +++ b/arch/loongarch/kvm/intc/eiointc.c @@ -328,12 +328,9 @@ static int kvm_eiointc_read(struct kvm_vcpu *vcpu, case 4: ret =3D loongarch_eiointc_readl(vcpu, eiointc, addr, val); break; - case 8: + default: ret =3D loongarch_eiointc_readq(vcpu, eiointc, addr, val); break; - default: - WARN_ONCE(1, "%s: Abnormal address access: addr 0x%llx, size %d\n", - __func__, addr, len); } spin_unlock_irqrestore(&eiointc->lock, flags); =20 @@ -704,12 +701,9 @@ static int kvm_eiointc_write(struct kvm_vcpu *vcpu, case 4: ret =3D loongarch_eiointc_writel(vcpu, eiointc, addr, val); break; - case 8: + default: ret =3D loongarch_eiointc_writeq(vcpu, eiointc, addr, val); break; - default: - WARN_ONCE(1, "%s: Abnormal address access: addr 0x%llx, size %d\n", - __func__, addr, len); } spin_unlock_irqrestore(&eiointc->lock, flags); =20 --=20 2.39.3 From nobody Tue Oct 7 14:06:29 2025 Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 12D2321ADAE; Wed, 9 Jul 2025 08:02:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=114.242.206.163 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752048162; cv=none; b=kxBEZSSylhjpT7il5joX7jCO9B99fbFHl9G88nj3tA1E7NvZE7ifSGw0IO2D65FdC9o7+d/y94ALL4lUHJkO4jrpaZ0VybB5U19BcDWF5zZsRFgltsXz2oKEi3aEgh/wWYvTXgv9wVOwbL+HwWJlJeh9fJHFdo5HVsOey8gjFE0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752048162; c=relaxed/simple; bh=ZozhxM42GWK0QwVZ3q7SmgDYN6haL4E4J7xu4mbH4O4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=oknVmOjRsGAKZlJ2hFEMQc4uXjnhBtjyOOHXXaElNwPZxQMl9N08779MiH0B6QbhPqUleO2utUmL6Rcc4x6CB/qHAk/pDiJZZoRGY4rKTWnJBpgmTqhGRnnwiLJva/do21gN3OtknJw69AkGSl1axylyND6fH6wtlcaYcn8P30I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn; spf=pass smtp.mailfrom=loongson.cn; arc=none smtp.client-ip=114.242.206.163 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=loongson.cn Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8DxzOIcIm5oXyklAQ--.13338S3; Wed, 09 Jul 2025 16:02:36 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJBxpeQZIm5oS6cPAA--.24964S7; Wed, 09 Jul 2025 16:02:36 +0800 (CST) From: Bibo Mao To: Tianrui Zhao , Huacai Chen , Xianglai Li Cc: kvm@vger.kernel.org, loongarch@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH v6 5/8] LoongArch: KVM: Use generic function loongarch_eiointc_read() Date: Wed, 9 Jul 2025 16:02:30 +0800 Message-Id: <20250709080233.3948503-6-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250709080233.3948503-1-maobibo@loongson.cn> References: <20250709080233.3948503-1-maobibo@loongson.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJBxpeQZIm5oS6cPAA--.24964S7 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Content-Type: text/plain; charset="utf-8" Generic read function loongarch_eiointc_read() is used for 1/2/4/8 bytes read access. It reads 8 bytes from emulated software state and shift right from address offset. Also the similar with kvm_complete_iocsr_read(), destination register of IOCSRRD.{B/H/W} is sign extension from byte/half word/word. Signed-off-by: Bibo Mao --- arch/loongarch/kvm/intc/eiointc.c | 153 ++++-------------------------- 1 file changed, 17 insertions(+), 136 deletions(-) diff --git a/arch/loongarch/kvm/intc/eiointc.c b/arch/loongarch/kvm/intc/ei= ointc.c index 137cd3adca80..3e8dc844be76 100644 --- a/arch/loongarch/kvm/intc/eiointc.c +++ b/arch/loongarch/kvm/intc/eiointc.c @@ -130,134 +130,8 @@ static inline void eiointc_enable_irq(struct kvm_vcpu= *vcpu, } } =20 -static int loongarch_eiointc_readb(struct kvm_vcpu *vcpu, struct loongarch= _eiointc *s, - gpa_t addr, void *val) -{ - int index, ret =3D 0; - u8 data =3D 0; - gpa_t offset; - - offset =3D addr - EIOINTC_BASE; - switch (offset) { - case EIOINTC_NODETYPE_START ... EIOINTC_NODETYPE_END: - index =3D offset - EIOINTC_NODETYPE_START; - data =3D s->nodetype.reg_u8[index]; - break; - case EIOINTC_IPMAP_START ... EIOINTC_IPMAP_END: - index =3D offset - EIOINTC_IPMAP_START; - data =3D s->ipmap.reg_u8[index]; - break; - case EIOINTC_ENABLE_START ... EIOINTC_ENABLE_END: - index =3D offset - EIOINTC_ENABLE_START; - data =3D s->enable.reg_u8[index]; - break; - case EIOINTC_BOUNCE_START ... EIOINTC_BOUNCE_END: - index =3D offset - EIOINTC_BOUNCE_START; - data =3D s->bounce.reg_u8[index]; - break; - case EIOINTC_COREISR_START ... EIOINTC_COREISR_END: - index =3D offset - EIOINTC_COREISR_START; - data =3D s->coreisr.reg_u8[vcpu->vcpu_id][index]; - break; - case EIOINTC_COREMAP_START ... EIOINTC_COREMAP_END: - index =3D offset - EIOINTC_COREMAP_START; - data =3D s->coremap.reg_u8[index]; - break; - default: - ret =3D -EINVAL; - break; - } - *(u8 *)val =3D data; - - return ret; -} - -static int loongarch_eiointc_readw(struct kvm_vcpu *vcpu, struct loongarch= _eiointc *s, - gpa_t addr, void *val) -{ - int index, ret =3D 0; - u16 data =3D 0; - gpa_t offset; - - offset =3D addr - EIOINTC_BASE; - switch (offset) { - case EIOINTC_NODETYPE_START ... EIOINTC_NODETYPE_END: - index =3D (offset - EIOINTC_NODETYPE_START) >> 1; - data =3D s->nodetype.reg_u16[index]; - break; - case EIOINTC_IPMAP_START ... EIOINTC_IPMAP_END: - index =3D (offset - EIOINTC_IPMAP_START) >> 1; - data =3D s->ipmap.reg_u16[index]; - break; - case EIOINTC_ENABLE_START ... EIOINTC_ENABLE_END: - index =3D (offset - EIOINTC_ENABLE_START) >> 1; - data =3D s->enable.reg_u16[index]; - break; - case EIOINTC_BOUNCE_START ... EIOINTC_BOUNCE_END: - index =3D (offset - EIOINTC_BOUNCE_START) >> 1; - data =3D s->bounce.reg_u16[index]; - break; - case EIOINTC_COREISR_START ... EIOINTC_COREISR_END: - index =3D (offset - EIOINTC_COREISR_START) >> 1; - data =3D s->coreisr.reg_u16[vcpu->vcpu_id][index]; - break; - case EIOINTC_COREMAP_START ... EIOINTC_COREMAP_END: - index =3D (offset - EIOINTC_COREMAP_START) >> 1; - data =3D s->coremap.reg_u16[index]; - break; - default: - ret =3D -EINVAL; - break; - } - *(u16 *)val =3D data; - - return ret; -} - -static int loongarch_eiointc_readl(struct kvm_vcpu *vcpu, struct loongarch= _eiointc *s, - gpa_t addr, void *val) -{ - int index, ret =3D 0; - u32 data =3D 0; - gpa_t offset; - - offset =3D addr - EIOINTC_BASE; - switch (offset) { - case EIOINTC_NODETYPE_START ... EIOINTC_NODETYPE_END: - index =3D (offset - EIOINTC_NODETYPE_START) >> 2; - data =3D s->nodetype.reg_u32[index]; - break; - case EIOINTC_IPMAP_START ... EIOINTC_IPMAP_END: - index =3D (offset - EIOINTC_IPMAP_START) >> 2; - data =3D s->ipmap.reg_u32[index]; - break; - case EIOINTC_ENABLE_START ... EIOINTC_ENABLE_END: - index =3D (offset - EIOINTC_ENABLE_START) >> 2; - data =3D s->enable.reg_u32[index]; - break; - case EIOINTC_BOUNCE_START ... EIOINTC_BOUNCE_END: - index =3D (offset - EIOINTC_BOUNCE_START) >> 2; - data =3D s->bounce.reg_u32[index]; - break; - case EIOINTC_COREISR_START ... EIOINTC_COREISR_END: - index =3D (offset - EIOINTC_COREISR_START) >> 2; - data =3D s->coreisr.reg_u32[vcpu->vcpu_id][index]; - break; - case EIOINTC_COREMAP_START ... EIOINTC_COREMAP_END: - index =3D (offset - EIOINTC_COREMAP_START) >> 2; - data =3D s->coremap.reg_u32[index]; - break; - default: - ret =3D -EINVAL; - break; - } - *(u32 *)val =3D data; - - return ret; -} - -static int loongarch_eiointc_readq(struct kvm_vcpu *vcpu, struct loongarch= _eiointc *s, - gpa_t addr, void *val) +static int loongarch_eiointc_read(struct kvm_vcpu *vcpu, struct loongarch_= eiointc *s, + gpa_t addr, unsigned long *val) { int index, ret =3D 0; u64 data =3D 0; @@ -293,7 +167,7 @@ static int loongarch_eiointc_readq(struct kvm_vcpu *vcp= u, struct loongarch_eioin ret =3D -EINVAL; break; } - *(u64 *)val =3D data; + *val =3D data; =20 return ret; } @@ -303,7 +177,7 @@ static int kvm_eiointc_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *val) { int ret =3D -EINVAL; - unsigned long flags; + unsigned long flags, data, offset; struct loongarch_eiointc *eiointc =3D vcpu->kvm->arch.eiointc; =20 if (!eiointc) { @@ -317,24 +191,31 @@ static int kvm_eiointc_read(struct kvm_vcpu *vcpu, } =20 vcpu->stat.eiointc_read_exits++; + offset =3D addr & 0x7; + addr -=3D offset; spin_lock_irqsave(&eiointc->lock, flags); + ret =3D loongarch_eiointc_read(vcpu, eiointc, addr, &data); + spin_unlock_irqrestore(&eiointc->lock, flags); + if (ret) + return ret; + + data =3D data >> (offset * 8); switch (len) { case 1: - ret =3D loongarch_eiointc_readb(vcpu, eiointc, addr, val); + *(long *)val =3D (s8)data; break; case 2: - ret =3D loongarch_eiointc_readw(vcpu, eiointc, addr, val); + *(long *)val =3D (s16)data; break; case 4: - ret =3D loongarch_eiointc_readl(vcpu, eiointc, addr, val); + *(long *)val =3D (s32)data; break; default: - ret =3D loongarch_eiointc_readq(vcpu, eiointc, addr, val); + *(long *)val =3D (long)data; break; } - spin_unlock_irqrestore(&eiointc->lock, flags); =20 - return ret; + return 0; } =20 static int loongarch_eiointc_writeb(struct kvm_vcpu *vcpu, --=20 2.39.3 From nobody Tue Oct 7 14:06:29 2025 Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 1475E2222C3; Wed, 9 Jul 2025 08:02:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=114.242.206.163 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752048161; cv=none; b=Xzy+MbE5TBPb6cRC0h1S016tI+jhALky7SrLbXuN9rTSo1jFhnlNCuNP0V0EpTSypcydLsnPb9hJ/XmZjDf93HgrqGKVsNMh3/9UlAuj1DirikI/dRp6f47XWXL7o5LSqNdNx2CklUgOARmO0hBha2Mq5XqxFL6furNGs7t1n+o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752048161; c=relaxed/simple; bh=x1bsEwS/nk/wakvnnYWRljMmzdrRQq5PzkcTVa0j/jo=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=FztlzhuaZOnXmAgoS/aEOyagt4TIeSE91sdrcRqsp8Hvn0661fPLfP/yQAEkO6HvfFYWzEBsXJhwFdEU1It26N9MmaU0OmsQVU2scFsBTditsw3nVmsuc9LzyJhsog6ZKALFUZGvf0G77Di6tfL25KJLymGwicZQ74zDA/CXNRY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn; spf=pass smtp.mailfrom=loongson.cn; arc=none smtp.client-ip=114.242.206.163 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=loongson.cn Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8CxG6wdIm5oYyklAQ--.38586S3; Wed, 09 Jul 2025 16:02:37 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJBxpeQZIm5oS6cPAA--.24964S8; Wed, 09 Jul 2025 16:02:36 +0800 (CST) From: Bibo Mao To: Tianrui Zhao , Huacai Chen , Xianglai Li Cc: kvm@vger.kernel.org, loongarch@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH v6 6/8] LoongArch: KVM: Remove some unnecessary local variables Date: Wed, 9 Jul 2025 16:02:31 +0800 Message-Id: <20250709080233.3948503-7-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250709080233.3948503-1-maobibo@loongson.cn> References: <20250709080233.3948503-1-maobibo@loongson.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJBxpeQZIm5oS6cPAA--.24964S8 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Content-Type: text/plain; charset="utf-8" Local variable coreisr and old_coreisr is replaced with data and old_data, and the latter is widely used in other places. Also local variable offset is removed and addr is used directly. Signed-off-by: Bibo Mao --- arch/loongarch/kvm/intc/eiointc.c | 31 ++++++++++++++----------------- 1 file changed, 14 insertions(+), 17 deletions(-) diff --git a/arch/loongarch/kvm/intc/eiointc.c b/arch/loongarch/kvm/intc/ei= ointc.c index 3e8dc844be76..bed5f7bdc8b4 100644 --- a/arch/loongarch/kvm/intc/eiointc.c +++ b/arch/loongarch/kvm/intc/eiointc.c @@ -474,15 +474,13 @@ static int loongarch_eiointc_writeq(struct kvm_vcpu *= vcpu, int i, index, irq, bits, ret =3D 0; u8 cpu; u64 data, old_data; - u64 coreisr, old_coreisr; - gpa_t offset; =20 data =3D *(u64 *)val; - offset =3D addr - EIOINTC_BASE; + addr -=3D EIOINTC_BASE; =20 - switch (offset) { + switch (addr) { case EIOINTC_NODETYPE_START ... EIOINTC_NODETYPE_END: - index =3D (offset - EIOINTC_NODETYPE_START) >> 3; + index =3D (addr - EIOINTC_NODETYPE_START) >> 3; s->nodetype.reg_u64[index] =3D data; break; case EIOINTC_IPMAP_START ... EIOINTC_IPMAP_END: @@ -490,11 +488,11 @@ static int loongarch_eiointc_writeq(struct kvm_vcpu *= vcpu, * ipmap cannot be set at runtime, can be set only at the beginning * of irqchip driver, need not update upper irq level */ - index =3D (offset - EIOINTC_IPMAP_START) >> 3; + index =3D (addr - EIOINTC_IPMAP_START) >> 3; s->ipmap.reg_u64 =3D data; break; case EIOINTC_ENABLE_START ... EIOINTC_ENABLE_END: - index =3D (offset - EIOINTC_ENABLE_START) >> 3; + index =3D (addr - EIOINTC_ENABLE_START) >> 3; old_data =3D s->enable.reg_u64[index]; s->enable.reg_u64[index] =3D data; /* @@ -518,28 +516,27 @@ static int loongarch_eiointc_writeq(struct kvm_vcpu *= vcpu, break; case EIOINTC_BOUNCE_START ... EIOINTC_BOUNCE_END: /* do not emulate hw bounced irq routing */ - index =3D (offset - EIOINTC_BOUNCE_START) >> 3; + index =3D (addr - EIOINTC_BOUNCE_START) >> 3; s->bounce.reg_u64[index] =3D data; break; case EIOINTC_COREISR_START ... EIOINTC_COREISR_END: - index =3D (offset - EIOINTC_COREISR_START) >> 3; + index =3D (addr - EIOINTC_COREISR_START) >> 3; /* use attrs to get current cpu index */ cpu =3D vcpu->vcpu_id; - coreisr =3D data; - old_coreisr =3D s->coreisr.reg_u64[cpu][index]; + old_data =3D s->coreisr.reg_u64[cpu][index]; /* write 1 to clear interrupt */ - s->coreisr.reg_u64[cpu][index] =3D old_coreisr & ~coreisr; - coreisr &=3D old_coreisr; + s->coreisr.reg_u64[cpu][index] =3D old_data & ~data; + data &=3D old_data; bits =3D sizeof(data) * 8; - irq =3D find_first_bit((void *)&coreisr, bits); + irq =3D find_first_bit((void *)&data, bits); while (irq < bits) { eiointc_update_irq(s, irq + index * bits, 0); - bitmap_clear((void *)&coreisr, irq, 1); - irq =3D find_first_bit((void *)&coreisr, bits); + bitmap_clear((void *)&data, irq, 1); + irq =3D find_first_bit((void *)&data, bits); } break; case EIOINTC_COREMAP_START ... EIOINTC_COREMAP_END: - irq =3D offset - EIOINTC_COREMAP_START; + irq =3D addr - EIOINTC_COREMAP_START; index =3D irq >> 3; s->coremap.reg_u64[index] =3D data; eiointc_update_sw_coremap(s, irq, data, sizeof(data), true); --=20 2.39.3 From nobody Tue Oct 7 14:06:29 2025 Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by smtp.subspace.kernel.org (Postfix) with ESMTP id D1BCF22FDFA; Wed, 9 Jul 2025 08:04:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=114.242.206.163 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752048268; cv=none; b=Ak9yK2FgXL8g0u22Pf+ER89qHWLlCCmn5G3zbB0qxEVYTQ9HpSNTwKhI9BGmBqVoGJx0QEYpeaKeTHqDwc2DV46Lg3BbvZZEAUTEit95oqmchKCdRbwI8F3zdsrnMhtr4JsgQxqbiexhjVkrUb2Hi+FcAX8ozCY+axc1kQUd2SU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752048268; c=relaxed/simple; bh=AZ9YbrbfLTIVuCpz3dYeCu2OiVygiGbtmFkeNcGzuIw=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=dlbNRq8rDoj0LjegZJ1oTSjRNRmIqg6FxUhrKRTBUJwy4AP77ITk1gGqlQ6frd5FfBDp/zOXYTSpxaMDRBbxFyB6WlUa3ZmNx5mH2HZ23lyKybNtrwssGdO88nFX4v1SJpYo+vaEoX1bCmkXwakmuDg3VVcuJvF4wxKUKuKV7IY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn; spf=pass smtp.mailfrom=loongson.cn; arc=none smtp.client-ip=114.242.206.163 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=loongson.cn Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8AxnOIdIm5oZiklAQ--.44014S3; Wed, 09 Jul 2025 16:02:37 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJBxpeQZIm5oS6cPAA--.24964S9; Wed, 09 Jul 2025 16:02:37 +0800 (CST) From: Bibo Mao To: Tianrui Zhao , Huacai Chen , Xianglai Li Cc: kvm@vger.kernel.org, loongarch@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH v6 7/8] LoongArch: KVM: Replace eiointc_enable_irq() with eiointc_update_irq() Date: Wed, 9 Jul 2025 16:02:32 +0800 Message-Id: <20250709080233.3948503-8-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250709080233.3948503-1-maobibo@loongson.cn> References: <20250709080233.3948503-1-maobibo@loongson.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJBxpeQZIm5oS6cPAA--.24964S9 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Content-Type: text/plain; charset="utf-8" Function eiointc_enable_irq() checks mask value with char type, and call eiointc_update_irq() eventually. Function eiointc_update_irq() will update one single irq status directly. Here it can check mask value with unsigned long type and call function eiointc_update_irq(), that is simple and direct. Signed-off-by: Bibo Mao --- arch/loongarch/kvm/intc/eiointc.c | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/arch/loongarch/kvm/intc/eiointc.c b/arch/loongarch/kvm/intc/ei= ointc.c index bed5f7bdc8b4..edcf87055b3c 100644 --- a/arch/loongarch/kvm/intc/eiointc.c +++ b/arch/loongarch/kvm/intc/eiointc.c @@ -471,7 +471,7 @@ static int loongarch_eiointc_writeq(struct kvm_vcpu *vc= pu, struct loongarch_eiointc *s, gpa_t addr, const void *val) { - int i, index, irq, bits, ret =3D 0; + int index, irq, ret =3D 0; u8 cpu; u64 data, old_data; =20 @@ -500,18 +500,20 @@ static int loongarch_eiointc_writeq(struct kvm_vcpu *= vcpu, * update irq when isr is set. */ data =3D s->enable.reg_u64[index] & ~old_data & s->isr.reg_u64[index]; - for (i =3D 0; i < sizeof(data); i++) { - u8 mask =3D (data >> (i * 8)) & 0xff; - eiointc_enable_irq(vcpu, s, index * 8 + i, mask, 1); + while (data) { + irq =3D __ffs(data); + eiointc_update_irq(s, irq + index * 64, 1); + data &=3D ~BIT_ULL(irq); } /* * 0: disable irq. * update irq when isr is set. */ data =3D ~s->enable.reg_u64[index] & old_data & s->isr.reg_u64[index]; - for (i =3D 0; i < sizeof(data); i++) { - u8 mask =3D (data >> (i * 8)) & 0xff; - eiointc_enable_irq(vcpu, s, index * 8 + i, mask, 0); + while (data) { + irq =3D __ffs(data); + eiointc_update_irq(s, irq + index * 64, 0); + data &=3D ~BIT_ULL(irq); } break; case EIOINTC_BOUNCE_START ... EIOINTC_BOUNCE_END: @@ -527,12 +529,10 @@ static int loongarch_eiointc_writeq(struct kvm_vcpu *= vcpu, /* write 1 to clear interrupt */ s->coreisr.reg_u64[cpu][index] =3D old_data & ~data; data &=3D old_data; - bits =3D sizeof(data) * 8; - irq =3D find_first_bit((void *)&data, bits); - while (irq < bits) { - eiointc_update_irq(s, irq + index * bits, 0); - bitmap_clear((void *)&data, irq, 1); - irq =3D find_first_bit((void *)&data, bits); + while (data) { + irq =3D __ffs(data); + eiointc_update_irq(s, irq + index * 64, 0); + data &=3D ~BIT_ULL(irq); } break; case EIOINTC_COREMAP_START ... EIOINTC_COREMAP_END: --=20 2.39.3 From nobody Tue Oct 7 14:06:29 2025 Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by smtp.subspace.kernel.org (Postfix) with ESMTP id D1B5B22FDE8; Wed, 9 Jul 2025 08:04:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=114.242.206.163 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752048268; cv=none; b=IE47amA5ueoQ8+HH90vtsi1LauPfJSFXDqzeme9vUPSdoM7WuPyW+ixVuCS29X5q0dgYycrfu6Neoe3yvv8IkfzthFhIMML710mFE5fDZKvdPPwpC0tRFQxH6nq/lQOFo0n5LYP7QUMqqrmTNgAxCt7MwUBuLgVed4WwmF0nlcU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752048268; c=relaxed/simple; bh=yZthooZwNqYlz9nExFCfhZkWUW2cCWFi8h7e4H9KpH4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=ks67VfxdB7idjmX/ZcfQzw39m7HYskdJrh0VlP4UHeyD6jrbSiMxRt1RnuOXZRDr0wBtbeOgwhhpvVni1OdGmEZvUN85jVy1GpTU3hsETq9bHQFIhtCIo+Kl/36PFqC6ZxVqJWAQR/XosGU4bXtcWUqwXL98+39fn6/mTGa9UeE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn; spf=pass smtp.mailfrom=loongson.cn; arc=none smtp.client-ip=114.242.206.163 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=loongson.cn Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8BxnmsdIm5oaSklAQ--.38658S3; Wed, 09 Jul 2025 16:02:37 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJBxpeQZIm5oS6cPAA--.24964S10; Wed, 09 Jul 2025 16:02:37 +0800 (CST) From: Bibo Mao To: Tianrui Zhao , Huacai Chen , Xianglai Li Cc: kvm@vger.kernel.org, loongarch@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH v6 8/8] LoongArch: KVM: Add generic function loongarch_eiointc_write() Date: Wed, 9 Jul 2025 16:02:33 +0800 Message-Id: <20250709080233.3948503-9-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250709080233.3948503-1-maobibo@loongson.cn> References: <20250709080233.3948503-1-maobibo@loongson.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJBxpeQZIm5oS6cPAA--.24964S10 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Content-Type: text/plain; charset="utf-8" With all eiointc iocsr register write operation with 1/2/4/8 bytes size, generic function loongarch_eiointc_write() is used here. And function loongarch_eiointc_writeb(), loongarch_eiointc_writew(), loongarch_eiointc_writel() are removed. Signed-off-by: Bibo Mao --- arch/loongarch/kvm/intc/eiointc.c | 329 ++++-------------------------- 1 file changed, 35 insertions(+), 294 deletions(-) diff --git a/arch/loongarch/kvm/intc/eiointc.c b/arch/loongarch/kvm/intc/ei= ointc.c index edcf87055b3c..cac59b10fa79 100644 --- a/arch/loongarch/kvm/intc/eiointc.c +++ b/arch/loongarch/kvm/intc/eiointc.c @@ -111,25 +111,6 @@ void eiointc_set_irq(struct loongarch_eiointc *s, int = irq, int level) spin_unlock_irqrestore(&s->lock, flags); } =20 -static inline void eiointc_enable_irq(struct kvm_vcpu *vcpu, - struct loongarch_eiointc *s, int index, u8 mask, int level) -{ - u8 val; - int irq; - - val =3D mask & s->isr.reg_u8[index]; - irq =3D ffs(val); - while (irq !=3D 0) { - /* - * enable bit change from 0 to 1, - * need to update irq by pending bits - */ - eiointc_update_irq(s, irq - 1 + index * 8, level); - val &=3D ~BIT(irq - 1); - irq =3D ffs(val); - } -} - static int loongarch_eiointc_read(struct kvm_vcpu *vcpu, struct loongarch_= eiointc *s, gpa_t addr, unsigned long *val) { @@ -218,288 +199,42 @@ static int kvm_eiointc_read(struct kvm_vcpu *vcpu, return 0; } =20 -static int loongarch_eiointc_writeb(struct kvm_vcpu *vcpu, - struct loongarch_eiointc *s, - gpa_t addr, const void *val) -{ - int index, irq, bits, ret =3D 0; - u8 cpu; - u8 data, old_data; - u8 coreisr, old_coreisr; - gpa_t offset; - - data =3D *(u8 *)val; - offset =3D addr - EIOINTC_BASE; - - switch (offset) { - case EIOINTC_NODETYPE_START ... EIOINTC_NODETYPE_END: - index =3D (offset - EIOINTC_NODETYPE_START); - s->nodetype.reg_u8[index] =3D data; - break; - case EIOINTC_IPMAP_START ... EIOINTC_IPMAP_END: - /* - * ipmap cannot be set at runtime, can be set only at the beginning - * of irqchip driver, need not update upper irq level - */ - index =3D (offset - EIOINTC_IPMAP_START); - s->ipmap.reg_u8[index] =3D data; - break; - case EIOINTC_ENABLE_START ... EIOINTC_ENABLE_END: - index =3D (offset - EIOINTC_ENABLE_START); - old_data =3D s->enable.reg_u8[index]; - s->enable.reg_u8[index] =3D data; - /* - * 1: enable irq. - * update irq when isr is set. - */ - data =3D s->enable.reg_u8[index] & ~old_data & s->isr.reg_u8[index]; - eiointc_enable_irq(vcpu, s, index, data, 1); - /* - * 0: disable irq. - * update irq when isr is set. - */ - data =3D ~s->enable.reg_u8[index] & old_data & s->isr.reg_u8[index]; - eiointc_enable_irq(vcpu, s, index, data, 0); - break; - case EIOINTC_BOUNCE_START ... EIOINTC_BOUNCE_END: - /* do not emulate hw bounced irq routing */ - index =3D offset - EIOINTC_BOUNCE_START; - s->bounce.reg_u8[index] =3D data; - break; - case EIOINTC_COREISR_START ... EIOINTC_COREISR_END: - index =3D (offset - EIOINTC_COREISR_START); - /* use attrs to get current cpu index */ - cpu =3D vcpu->vcpu_id; - coreisr =3D data; - old_coreisr =3D s->coreisr.reg_u8[cpu][index]; - /* write 1 to clear interrupt */ - s->coreisr.reg_u8[cpu][index] =3D old_coreisr & ~coreisr; - coreisr &=3D old_coreisr; - bits =3D sizeof(data) * 8; - irq =3D find_first_bit((void *)&coreisr, bits); - while (irq < bits) { - eiointc_update_irq(s, irq + index * bits, 0); - bitmap_clear((void *)&coreisr, irq, 1); - irq =3D find_first_bit((void *)&coreisr, bits); - } - break; - case EIOINTC_COREMAP_START ... EIOINTC_COREMAP_END: - irq =3D offset - EIOINTC_COREMAP_START; - index =3D irq; - s->coremap.reg_u8[index] =3D data; - eiointc_update_sw_coremap(s, irq, data, sizeof(data), true); - break; - default: - ret =3D -EINVAL; - break; - } - - return ret; -} - -static int loongarch_eiointc_writew(struct kvm_vcpu *vcpu, - struct loongarch_eiointc *s, - gpa_t addr, const void *val) -{ - int i, index, irq, bits, ret =3D 0; - u8 cpu; - u16 data, old_data; - u16 coreisr, old_coreisr; - gpa_t offset; - - data =3D *(u16 *)val; - offset =3D addr - EIOINTC_BASE; - - switch (offset) { - case EIOINTC_NODETYPE_START ... EIOINTC_NODETYPE_END: - index =3D (offset - EIOINTC_NODETYPE_START) >> 1; - s->nodetype.reg_u16[index] =3D data; - break; - case EIOINTC_IPMAP_START ... EIOINTC_IPMAP_END: - /* - * ipmap cannot be set at runtime, can be set only at the beginning - * of irqchip driver, need not update upper irq level - */ - index =3D (offset - EIOINTC_IPMAP_START) >> 1; - s->ipmap.reg_u16[index] =3D data; - break; - case EIOINTC_ENABLE_START ... EIOINTC_ENABLE_END: - index =3D (offset - EIOINTC_ENABLE_START) >> 1; - old_data =3D s->enable.reg_u16[index]; - s->enable.reg_u16[index] =3D data; - /* - * 1: enable irq. - * update irq when isr is set. - */ - data =3D s->enable.reg_u16[index] & ~old_data & s->isr.reg_u16[index]; - for (i =3D 0; i < sizeof(data); i++) { - u8 mask =3D (data >> (i * 8)) & 0xff; - eiointc_enable_irq(vcpu, s, index * 2 + i, mask, 1); - } - /* - * 0: disable irq. - * update irq when isr is set. - */ - data =3D ~s->enable.reg_u16[index] & old_data & s->isr.reg_u16[index]; - for (i =3D 0; i < sizeof(data); i++) { - u8 mask =3D (data >> (i * 8)) & 0xff; - eiointc_enable_irq(vcpu, s, index * 2 + i, mask, 0); - } - break; - case EIOINTC_BOUNCE_START ... EIOINTC_BOUNCE_END: - /* do not emulate hw bounced irq routing */ - index =3D (offset - EIOINTC_BOUNCE_START) >> 1; - s->bounce.reg_u16[index] =3D data; - break; - case EIOINTC_COREISR_START ... EIOINTC_COREISR_END: - index =3D (offset - EIOINTC_COREISR_START) >> 1; - /* use attrs to get current cpu index */ - cpu =3D vcpu->vcpu_id; - coreisr =3D data; - old_coreisr =3D s->coreisr.reg_u16[cpu][index]; - /* write 1 to clear interrupt */ - s->coreisr.reg_u16[cpu][index] =3D old_coreisr & ~coreisr; - coreisr &=3D old_coreisr; - bits =3D sizeof(data) * 8; - irq =3D find_first_bit((void *)&coreisr, bits); - while (irq < bits) { - eiointc_update_irq(s, irq + index * bits, 0); - bitmap_clear((void *)&coreisr, irq, 1); - irq =3D find_first_bit((void *)&coreisr, bits); - } - break; - case EIOINTC_COREMAP_START ... EIOINTC_COREMAP_END: - irq =3D offset - EIOINTC_COREMAP_START; - index =3D irq >> 1; - s->coremap.reg_u16[index] =3D data; - eiointc_update_sw_coremap(s, irq, data, sizeof(data), true); - break; - default: - ret =3D -EINVAL; - break; - } - - return ret; -} - -static int loongarch_eiointc_writel(struct kvm_vcpu *vcpu, - struct loongarch_eiointc *s, - gpa_t addr, const void *val) -{ - int i, index, irq, bits, ret =3D 0; - u8 cpu; - u32 data, old_data; - u32 coreisr, old_coreisr; - gpa_t offset; - - data =3D *(u32 *)val; - offset =3D addr - EIOINTC_BASE; - - switch (offset) { - case EIOINTC_NODETYPE_START ... EIOINTC_NODETYPE_END: - index =3D (offset - EIOINTC_NODETYPE_START) >> 2; - s->nodetype.reg_u32[index] =3D data; - break; - case EIOINTC_IPMAP_START ... EIOINTC_IPMAP_END: - /* - * ipmap cannot be set at runtime, can be set only at the beginning - * of irqchip driver, need not update upper irq level - */ - index =3D (offset - EIOINTC_IPMAP_START) >> 2; - s->ipmap.reg_u32[index] =3D data; - break; - case EIOINTC_ENABLE_START ... EIOINTC_ENABLE_END: - index =3D (offset - EIOINTC_ENABLE_START) >> 2; - old_data =3D s->enable.reg_u32[index]; - s->enable.reg_u32[index] =3D data; - /* - * 1: enable irq. - * update irq when isr is set. - */ - data =3D s->enable.reg_u32[index] & ~old_data & s->isr.reg_u32[index]; - for (i =3D 0; i < sizeof(data); i++) { - u8 mask =3D (data >> (i * 8)) & 0xff; - eiointc_enable_irq(vcpu, s, index * 4 + i, mask, 1); - } - /* - * 0: disable irq. - * update irq when isr is set. - */ - data =3D ~s->enable.reg_u32[index] & old_data & s->isr.reg_u32[index]; - for (i =3D 0; i < sizeof(data); i++) { - u8 mask =3D (data >> (i * 8)) & 0xff; - eiointc_enable_irq(vcpu, s, index * 4 + i, mask, 0); - } - break; - case EIOINTC_BOUNCE_START ... EIOINTC_BOUNCE_END: - /* do not emulate hw bounced irq routing */ - index =3D (offset - EIOINTC_BOUNCE_START) >> 2; - s->bounce.reg_u32[index] =3D data; - break; - case EIOINTC_COREISR_START ... EIOINTC_COREISR_END: - index =3D (offset - EIOINTC_COREISR_START) >> 2; - /* use attrs to get current cpu index */ - cpu =3D vcpu->vcpu_id; - coreisr =3D data; - old_coreisr =3D s->coreisr.reg_u32[cpu][index]; - /* write 1 to clear interrupt */ - s->coreisr.reg_u32[cpu][index] =3D old_coreisr & ~coreisr; - coreisr &=3D old_coreisr; - bits =3D sizeof(data) * 8; - irq =3D find_first_bit((void *)&coreisr, bits); - while (irq < bits) { - eiointc_update_irq(s, irq + index * bits, 0); - bitmap_clear((void *)&coreisr, irq, 1); - irq =3D find_first_bit((void *)&coreisr, bits); - } - break; - case EIOINTC_COREMAP_START ... EIOINTC_COREMAP_END: - irq =3D offset - EIOINTC_COREMAP_START; - index =3D irq >> 2; - s->coremap.reg_u32[index] =3D data; - eiointc_update_sw_coremap(s, irq, data, sizeof(data), true); - break; - default: - ret =3D -EINVAL; - break; - } - - return ret; -} - -static int loongarch_eiointc_writeq(struct kvm_vcpu *vcpu, +static int loongarch_eiointc_write(struct kvm_vcpu *vcpu, struct loongarch_eiointc *s, - gpa_t addr, const void *val) + gpa_t addr, u64 value, u64 field_mask) { - int index, irq, ret =3D 0; + int index, irq, offset, ret =3D 0; u8 cpu; - u64 data, old_data; + u64 data, old, mask; =20 - data =3D *(u64 *)val; - addr -=3D EIOINTC_BASE; + offset =3D addr & 7; + mask =3D field_mask << (offset * 8); + data =3D (value & field_mask) << (offset * 8); + addr -=3D EIOINTC_BASE + offset; =20 switch (addr) { case EIOINTC_NODETYPE_START ... EIOINTC_NODETYPE_END: index =3D (addr - EIOINTC_NODETYPE_START) >> 3; - s->nodetype.reg_u64[index] =3D data; + old =3D s->nodetype.reg_u64[index]; + s->nodetype.reg_u64[index] =3D (old & ~mask) | data; break; case EIOINTC_IPMAP_START ... EIOINTC_IPMAP_END: /* * ipmap cannot be set at runtime, can be set only at the beginning * of irqchip driver, need not update upper irq level */ - index =3D (addr - EIOINTC_IPMAP_START) >> 3; - s->ipmap.reg_u64 =3D data; + old =3D s->ipmap.reg_u64; + s->ipmap.reg_u64 =3D (old & ~mask) | data; break; case EIOINTC_ENABLE_START ... EIOINTC_ENABLE_END: index =3D (addr - EIOINTC_ENABLE_START) >> 3; - old_data =3D s->enable.reg_u64[index]; - s->enable.reg_u64[index] =3D data; + old =3D s->enable.reg_u64[index]; + s->enable.reg_u64[index] =3D (old & ~mask) | data; /* * 1: enable irq. * update irq when isr is set. */ - data =3D s->enable.reg_u64[index] & ~old_data & s->isr.reg_u64[index]; + data =3D s->enable.reg_u64[index] & ~old & s->isr.reg_u64[index]; while (data) { irq =3D __ffs(data); eiointc_update_irq(s, irq + index * 64, 1); @@ -509,7 +244,7 @@ static int loongarch_eiointc_writeq(struct kvm_vcpu *vc= pu, * 0: disable irq. * update irq when isr is set. */ - data =3D ~s->enable.reg_u64[index] & old_data & s->isr.reg_u64[index]; + data =3D ~s->enable.reg_u64[index] & old & s->isr.reg_u64[index]; while (data) { irq =3D __ffs(data); eiointc_update_irq(s, irq + index * 64, 0); @@ -519,16 +254,17 @@ static int loongarch_eiointc_writeq(struct kvm_vcpu *= vcpu, case EIOINTC_BOUNCE_START ... EIOINTC_BOUNCE_END: /* do not emulate hw bounced irq routing */ index =3D (addr - EIOINTC_BOUNCE_START) >> 3; - s->bounce.reg_u64[index] =3D data; + old =3D s->bounce.reg_u64[index]; + s->bounce.reg_u64[index] =3D (old & ~mask) | data; break; case EIOINTC_COREISR_START ... EIOINTC_COREISR_END: index =3D (addr - EIOINTC_COREISR_START) >> 3; /* use attrs to get current cpu index */ cpu =3D vcpu->vcpu_id; - old_data =3D s->coreisr.reg_u64[cpu][index]; + old =3D s->coreisr.reg_u64[cpu][index]; /* write 1 to clear interrupt */ - s->coreisr.reg_u64[cpu][index] =3D old_data & ~data; - data &=3D old_data; + s->coreisr.reg_u64[cpu][index] =3D old & ~data; + data &=3D old; while (data) { irq =3D __ffs(data); eiointc_update_irq(s, irq + index * 64, 0); @@ -536,10 +272,11 @@ static int loongarch_eiointc_writeq(struct kvm_vcpu *= vcpu, } break; case EIOINTC_COREMAP_START ... EIOINTC_COREMAP_END: - irq =3D addr - EIOINTC_COREMAP_START; - index =3D irq >> 3; - s->coremap.reg_u64[index] =3D data; - eiointc_update_sw_coremap(s, irq, data, sizeof(data), true); + index =3D (addr - EIOINTC_COREMAP_START) >> 3; + old =3D s->coremap.reg_u64[index]; + s->coremap.reg_u64[index] =3D (old & ~mask) | data; + data =3D s->coremap.reg_u64[index]; + eiointc_update_sw_coremap(s, index * 8, data, sizeof(data), true); break; default: ret =3D -EINVAL; @@ -554,7 +291,7 @@ static int kvm_eiointc_write(struct kvm_vcpu *vcpu, gpa_t addr, int len, const void *val) { int ret =3D -EINVAL; - unsigned long flags; + unsigned long flags, value; struct loongarch_eiointc *eiointc =3D vcpu->kvm->arch.eiointc; =20 if (!eiointc) { @@ -571,16 +308,20 @@ static int kvm_eiointc_write(struct kvm_vcpu *vcpu, spin_lock_irqsave(&eiointc->lock, flags); switch (len) { case 1: - ret =3D loongarch_eiointc_writeb(vcpu, eiointc, addr, val); + value =3D *(unsigned char *)val; + ret =3D loongarch_eiointc_write(vcpu, eiointc, addr, value, 0xFF); break; case 2: - ret =3D loongarch_eiointc_writew(vcpu, eiointc, addr, val); + value =3D *(unsigned short *)val; + ret =3D loongarch_eiointc_write(vcpu, eiointc, addr, value, USHRT_MAX); break; case 4: - ret =3D loongarch_eiointc_writel(vcpu, eiointc, addr, val); + value =3D *(unsigned int *)val; + ret =3D loongarch_eiointc_write(vcpu, eiointc, addr, value, UINT_MAX); break; default: - ret =3D loongarch_eiointc_writeq(vcpu, eiointc, addr, val); + value =3D *(unsigned long *)val; + ret =3D loongarch_eiointc_write(vcpu, eiointc, addr, value, ULONG_MAX); break; } spin_unlock_irqrestore(&eiointc->lock, flags); --=20 2.39.3