From nobody Tue Oct 7 16:36:38 2025 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 86E8926E6F2; Wed, 9 Jul 2025 07:08:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752044904; cv=none; b=d3ZCnXHwfPk0oqd5qLgQkF+Kbc7kewwRX/0LkWRA1CyU3YTN0+CEm7/dK3Z/Fi6yypbNX5DCa++dpByujC0sZdBRqY18730ZN5Kkf8RrrPsveJHjgrLhYW/I/F124AskoY/MnMRxYvS9xrcuaOVWQe+YqBXPOWkAOTDUnh3K4+Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752044904; c=relaxed/simple; bh=kowMxFV0zyv660Ps0g0qhuJSLinkYBbDQaMsDUcx11g=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Atpsr/EdsrjIReNDwKjAbOIN5WK07yzHJ4Zkw4xtJ0KBsgz9gtEfdWTzf3TF+xwUMbjLFdBrrYXbZCc5NP1m6dsVKxe07T5YsLHgBRiLhrJsrdr+Dlt4RfaRw2lVM0253Zhhn/qZRqMOTe0w04nIyINb4rXG/XVQpmkU7XIUuq0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 9 Jul 2025 15:08:09 +0800 Received: from mail.aspeedtech.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Wed, 9 Jul 2025 15:08:09 +0800 From: Jacky Chou To: , , , , , , , , , , , , , , , , , , , , , , CC: Subject: [net-next v4 1/4] dt-bindings: net: ftgmac100: Add resets property Date: Wed, 9 Jul 2025 15:08:06 +0800 Message-ID: <20250709070809.2560688-2-jacky_chou@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250709070809.2560688-1-jacky_chou@aspeedtech.com> References: <20250709070809.2560688-1-jacky_chou@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In Aspeed AST2600 design, the MAC internal delay on MAC register cannot fully reset the RMII interfaces, it may cause the RMII incompletely. Therefore, we need to add resets property to do SoC-level reset line to reset the whole MAC function that includes ftgmac, RGMII and RMII. Signed-off-by: Jacky Chou Reviewed-by: Krzysztof Kozlowski --- .../bindings/net/faraday,ftgmac100.yaml | 21 ++++++++++++++++--- 1 file changed, 18 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/net/faraday,ftgmac100.yaml b= /Documentation/devicetree/bindings/net/faraday,ftgmac100.yaml index 55d6a8379025..d14410018bcf 100644 --- a/Documentation/devicetree/bindings/net/faraday,ftgmac100.yaml +++ b/Documentation/devicetree/bindings/net/faraday,ftgmac100.yaml @@ -6,9 +6,6 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# =20 title: Faraday Technology FTGMAC100 gigabit ethernet controller =20 -allOf: - - $ref: ethernet-controller.yaml# - maintainers: - Po-Yu Chuang =20 @@ -35,6 +32,9 @@ properties: - description: MAC IP clock - description: RMII RCLK gate for AST2500/2600 =20 + resets: + maxItems: 1 + clock-names: minItems: 1 items: @@ -74,6 +74,21 @@ required: - reg - interrupts =20 +allOf: + - $ref: ethernet-controller.yaml# + - if: + properties: + compatible: + contains: + enum: + - aspeed,ast2600-mac + then: + properties: + resets: true + else: + properties: + resets: false + unevaluatedProperties: false =20 examples: --=20 2.34.1