From nobody Tue Oct 7 14:57:05 2025 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 86E8926E6F2; Wed, 9 Jul 2025 07:08:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752044904; cv=none; b=d3ZCnXHwfPk0oqd5qLgQkF+Kbc7kewwRX/0LkWRA1CyU3YTN0+CEm7/dK3Z/Fi6yypbNX5DCa++dpByujC0sZdBRqY18730ZN5Kkf8RrrPsveJHjgrLhYW/I/F124AskoY/MnMRxYvS9xrcuaOVWQe+YqBXPOWkAOTDUnh3K4+Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752044904; c=relaxed/simple; bh=kowMxFV0zyv660Ps0g0qhuJSLinkYBbDQaMsDUcx11g=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Atpsr/EdsrjIReNDwKjAbOIN5WK07yzHJ4Zkw4xtJ0KBsgz9gtEfdWTzf3TF+xwUMbjLFdBrrYXbZCc5NP1m6dsVKxe07T5YsLHgBRiLhrJsrdr+Dlt4RfaRw2lVM0253Zhhn/qZRqMOTe0w04nIyINb4rXG/XVQpmkU7XIUuq0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 9 Jul 2025 15:08:09 +0800 Received: from mail.aspeedtech.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Wed, 9 Jul 2025 15:08:09 +0800 From: Jacky Chou To: , , , , , , , , , , , , , , , , , , , , , , CC: Subject: [net-next v4 1/4] dt-bindings: net: ftgmac100: Add resets property Date: Wed, 9 Jul 2025 15:08:06 +0800 Message-ID: <20250709070809.2560688-2-jacky_chou@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250709070809.2560688-1-jacky_chou@aspeedtech.com> References: <20250709070809.2560688-1-jacky_chou@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In Aspeed AST2600 design, the MAC internal delay on MAC register cannot fully reset the RMII interfaces, it may cause the RMII incompletely. Therefore, we need to add resets property to do SoC-level reset line to reset the whole MAC function that includes ftgmac, RGMII and RMII. Signed-off-by: Jacky Chou Reviewed-by: Krzysztof Kozlowski --- .../bindings/net/faraday,ftgmac100.yaml | 21 ++++++++++++++++--- 1 file changed, 18 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/net/faraday,ftgmac100.yaml b= /Documentation/devicetree/bindings/net/faraday,ftgmac100.yaml index 55d6a8379025..d14410018bcf 100644 --- a/Documentation/devicetree/bindings/net/faraday,ftgmac100.yaml +++ b/Documentation/devicetree/bindings/net/faraday,ftgmac100.yaml @@ -6,9 +6,6 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# =20 title: Faraday Technology FTGMAC100 gigabit ethernet controller =20 -allOf: - - $ref: ethernet-controller.yaml# - maintainers: - Po-Yu Chuang =20 @@ -35,6 +32,9 @@ properties: - description: MAC IP clock - description: RMII RCLK gate for AST2500/2600 =20 + resets: + maxItems: 1 + clock-names: minItems: 1 items: @@ -74,6 +74,21 @@ required: - reg - interrupts =20 +allOf: + - $ref: ethernet-controller.yaml# + - if: + properties: + compatible: + contains: + enum: + - aspeed,ast2600-mac + then: + properties: + resets: true + else: + properties: + resets: false + unevaluatedProperties: false =20 examples: --=20 2.34.1 From nobody Tue Oct 7 14:57:05 2025 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4BFE32701C5; Wed, 9 Jul 2025 07:08:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752044906; cv=none; b=KJZqVMHO9vfH7+z3K0wXea6JQ6D7EgfSg+ksjbB7OixOV25/UhII3hqphiIU4LVK0wXgNpvFYbZH5E2cjIHMtM91+q8A29zJF2mfpCAGH8bFsL6b6ROt9erU35n0moNFGl4sVyKXK4ylOr4WMObWGZ/3rpfl9njnaDHA+VLs7F0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752044906; c=relaxed/simple; bh=YQhsnLUMAU7ZH3pjjQGAg2eqdpC5eflBNrsKckB38kk=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=T29rRBNK8IGejsDxzbrhqPhfO/4i/c+F/Tn8SJz2EG1KA8BJNqZYRR/h0Hw9s65B/e3Y/wiWEAZR+NNFQiluRXwZXOD/XK+zrxTVw+8wp0viPjW2NiPfxoWZG48drvFGcysv7m24o9Hx+8XTyXGWtIEUjt97kCHAJm5omsMZWMU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 9 Jul 2025 15:08:09 +0800 Received: from mail.aspeedtech.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Wed, 9 Jul 2025 15:08:09 +0800 From: Jacky Chou To: , , , , , , , , , , , , , , , , , , , , , , CC: , Conor Dooley Subject: [net-next v4 2/4] dt-bindings: clock: ast2600: Add reset definitions for MAC1 and MAC2 Date: Wed, 9 Jul 2025 15:08:07 +0800 Message-ID: <20250709070809.2560688-3-jacky_chou@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250709070809.2560688-1-jacky_chou@aspeedtech.com> References: <20250709070809.2560688-1-jacky_chou@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add ASPEED_RESET_MAC1 and ASPEED_RESET_MAC2 reset definitions to the ast2600-clock binding header. These are required for proper reset control of the MAC1 and MAC2 ethernet controllers on the AST2600 SoC. Signed-off-by: Jacky Chou Acked-by: Conor Dooley Acked-by: Stephen Boyd --- include/dt-bindings/clock/ast2600-clock.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/dt-bindings/clock/ast2600-clock.h b/include/dt-binding= s/clock/ast2600-clock.h index 7ae96c7bd72f..f60fff261130 100644 --- a/include/dt-bindings/clock/ast2600-clock.h +++ b/include/dt-bindings/clock/ast2600-clock.h @@ -122,6 +122,8 @@ #define ASPEED_RESET_PCIE_DEV_OEN 20 #define ASPEED_RESET_PCIE_RC_O 19 #define ASPEED_RESET_PCIE_RC_OEN 18 +#define ASPEED_RESET_MAC2 12 +#define ASPEED_RESET_MAC1 11 #define ASPEED_RESET_PCI_DP 5 #define ASPEED_RESET_HACE 4 #define ASPEED_RESET_AHB 1 --=20 2.34.1 From nobody Tue Oct 7 14:57:05 2025 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6DC162727E4; Wed, 9 Jul 2025 07:08:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752044908; cv=none; b=djh+AnePwxJChDWnhMvZe6Mkrn1xX7ezo2DGcDZ0xJiszeIy2oJuhBPMUg8qKUbgS3EvQgYp3SHow2mY25BCQZWfT0h3nXEolabV+QmjPuhjVfVLpHmrBjqk5psxKYG121gDdrQbDVjPraL+FtUITrApdGPBKJXXu0yK5vppAYw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752044908; c=relaxed/simple; bh=niTQfAe3mnitW8DHBUFf0G5gpxM1At2/3CYLdrDk0MA=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=f7i2XKEcRVxu91vKuuB+ycDv2G+7Zd/3fGxJBA56jPoJUWdyVp+/p/Q/ZYtly5YFO8hDejeSy/gGg4RbSTVeSRQTRhhKkRAUzoH/CIqoYvRqatZte5Q96Mcp4pqw1JCFUF2yR/uf2d2vZ5DTf9JY5vnKzBS0QvGWtKYHr5ZVkyA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 9 Jul 2025 15:08:09 +0800 Received: from mail.aspeedtech.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Wed, 9 Jul 2025 15:08:09 +0800 From: Jacky Chou To: , , , , , , , , , , , , , , , , , , , , , , CC: Subject: [net-next v4 3/4] ARM: dts: aspeed-g6: Add resets property for MAC controllers Date: Wed, 9 Jul 2025 15:08:08 +0800 Message-ID: <20250709070809.2560688-4-jacky_chou@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250709070809.2560688-1-jacky_chou@aspeedtech.com> References: <20250709070809.2560688-1-jacky_chou@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the "resets" property to the MAC nodes in the AST2600 device tree, using the appropriate ASPEED_RESET_MACx definitions. Signed-off-by: Jacky Chou --- arch/arm/boot/dts/aspeed/aspeed-g6.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi b/arch/arm/boot/dts/as= peed/aspeed-g6.dtsi index 8ed715bd53aa..f9fe89665e49 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi +++ b/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi @@ -236,6 +236,7 @@ mac0: ethernet@1e660000 { reg =3D <0x1e660000 0x180>; interrupts =3D ; clocks =3D <&syscon ASPEED_CLK_GATE_MAC1CLK>; + resets =3D <&syscon ASPEED_RESET_MAC1>; status =3D "disabled"; }; =20 @@ -244,6 +245,7 @@ mac1: ethernet@1e680000 { reg =3D <0x1e680000 0x180>; interrupts =3D ; clocks =3D <&syscon ASPEED_CLK_GATE_MAC2CLK>; + resets =3D <&syscon ASPEED_RESET_MAC2>; status =3D "disabled"; }; =20 @@ -252,6 +254,7 @@ mac2: ethernet@1e670000 { reg =3D <0x1e670000 0x180>; interrupts =3D ; clocks =3D <&syscon ASPEED_CLK_GATE_MAC3CLK>; + resets =3D <&syscon ASPEED_RESET_MAC3>; status =3D "disabled"; }; =20 @@ -260,6 +263,7 @@ mac3: ethernet@1e690000 { reg =3D <0x1e690000 0x180>; interrupts =3D ; clocks =3D <&syscon ASPEED_CLK_GATE_MAC4CLK>; + resets =3D <&syscon ASPEED_RESET_MAC4>; status =3D "disabled"; }; =20 --=20 2.34.1 From nobody Tue Oct 7 14:57:05 2025 Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4145A273D8E; Wed, 9 Jul 2025 07:08:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752044909; cv=none; b=AUhDdj+oDab2csaRC0s0vuCc/AhERK7zLE+FPlND4u3Ig5KrYjrkk07u3+NSVXTIJuzx9J1lBfMEGA94rvGWhuZpt71GefxYMuK+37CsTGZkLvyY84Yts+68eYmbJAkfJ9QW5gs6xu/xegX23Q2mSwm60V1jlvud4CwwMFO6uEU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752044909; c=relaxed/simple; bh=0LtjXvqsRruXDJtU07Ulf5ytfTnCk8K7EwtmbcFBh/M=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=SNlvZ7HL1/OLPRvmL+RCVtx2hnZ7WpHt5P5IfSMuELD0DtYjFuGEupRxFP140fRHyQKYUOvBPe+F1x/4SvBbOnS9nDw8gZHZ5rlJOVVBj2buxayuCvYXqLPKOHEFF+MvP4qiVviZkBHfptomYNj6wVXVAZJD67UsHkLcjJmL5mU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass smtp.mailfrom=aspeedtech.com; arc=none smtp.client-ip=211.20.114.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aspeedtech.com Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 9 Jul 2025 15:08:10 +0800 Received: from mail.aspeedtech.com (192.168.10.13) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Wed, 9 Jul 2025 15:08:10 +0800 From: Jacky Chou To: , , , , , , , , , , , , , , , , , , , , , , CC: Subject: [net-next v4 4/4] net: ftgmac100: Add optional reset control for RMII mode on Aspeed SoCs Date: Wed, 9 Jul 2025 15:08:09 +0800 Message-ID: <20250709070809.2560688-5-jacky_chou@aspeedtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250709070809.2560688-1-jacky_chou@aspeedtech.com> References: <20250709070809.2560688-1-jacky_chou@aspeedtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" On Aspeed SoCs, the internal MAC reset is insufficient to fully reset the RMII interface; only the SoC-level reset line can properly reset the RMII logic. This patch adds support for an optional "resets" property in the device tree, allowing the driver to assert and deassert the SoC reset line when operating in RMII mode. This ensures the MAC and RMII interface are correctly reset and initialized. Signed-off-by: Jacky Chou Reviewed-by: Andrew Lunn --- drivers/net/ethernet/faraday/ftgmac100.c | 26 ++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/drivers/net/ethernet/faraday/ftgmac100.c b/drivers/net/etherne= t/faraday/ftgmac100.c index a98d5af3f9e3..05b8e3743a79 100644 --- a/drivers/net/ethernet/faraday/ftgmac100.c +++ b/drivers/net/ethernet/faraday/ftgmac100.c @@ -9,6 +9,7 @@ #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt =20 #include +#include #include #include #include @@ -101,6 +102,8 @@ struct ftgmac100 { =20 /* AST2500/AST2600 RMII ref clock gate */ struct clk *rclk; + /* Aspeed reset control */ + struct reset_control *rst; =20 /* Link management */ int cur_speed; @@ -148,6 +151,23 @@ static int ftgmac100_reset_and_config_mac(struct ftgma= c100 *priv) { u32 maccr =3D 0; =20 + /* Aspeed RMII needs SCU reset to clear status */ + if (priv->is_aspeed && priv->netdev->phydev->interface =3D=3D PHY_INTERFA= CE_MODE_RMII) { + int err; + + err =3D reset_control_assert(priv->rst); + if (err) { + dev_err(priv->dev, "Failed to reset mac (%d)\n", err); + return err; + } + usleep_range(10000, 20000); + err =3D reset_control_deassert(priv->rst); + if (err) { + dev_err(priv->dev, "Failed to deassert mac reset (%d)\n", err); + return err; + } + } + switch (priv->cur_speed) { case SPEED_10: case 0: /* no link */ @@ -1968,6 +1988,12 @@ static int ftgmac100_probe(struct platform_device *p= dev) =20 } =20 + priv->rst =3D devm_reset_control_get_optional_exclusive(priv->dev, NULL); + if (IS_ERR(priv->rst)) { + err =3D PTR_ERR(priv->rst); + goto err_phy_connect; + } + if (priv->is_aspeed) { err =3D ftgmac100_setup_clk(priv); if (err) --=20 2.34.1