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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Jul 2025 03:39:46.4344 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 815f3bfe-4ac5-434c-d4aa-08ddbe9a4004 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB50.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB5718 Content-Type: text/plain; charset="utf-8" Add an update_vector() callback to allow APIC drivers to perform driver specific operations on external vector allocation/teardown on a CPU. This callback will be used in subsequent commits by Secure AVIC APIC driver to configure the vectors which a guest vCPU allows the hypervisor to send to it. As system vectors have fixed vector assignments and are not dynamically allocated, add apic_update_vector() public api to facilitate update_vector() callback invocation for them. This will be used for Secure AVIC enabled guests to allow the hypervisor to inject system vectors which are emulated by the hypervisor such as APIC timer vector and HYPERVISOR_CALLBACK_VECTOR. While at it, cleanup line break in apic_update_irq_cfg(). Co-developed-by: Kishon Vijay Abraham I Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Neeraj Upadhyay --- Changes since v7: - No change. arch/x86/include/asm/apic.h | 9 +++++++++ arch/x86/kernel/apic/vector.c | 29 ++++++++++++++++++----------- 2 files changed, 27 insertions(+), 11 deletions(-) diff --git a/arch/x86/include/asm/apic.h b/arch/x86/include/asm/apic.h index 184cae6e786b..9c74d1faf3e0 100644 --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -318,6 +318,8 @@ struct apic { /* wakeup secondary CPU using 64-bit wakeup point */ int (*wakeup_secondary_cpu_64)(u32 apicid, unsigned long start_eip, unsig= ned int cpu); =20 + void (*update_vector)(unsigned int cpu, unsigned int vector, bool set); + char *name; }; =20 @@ -471,6 +473,12 @@ static __always_inline bool apic_id_valid(u32 apic_id) return apic_id <=3D apic->max_apic_id; } =20 +static __always_inline void apic_update_vector(unsigned int cpu, unsigned = int vector, bool set) +{ + if (apic->update_vector) + apic->update_vector(cpu, vector, set); +} + #else /* CONFIG_X86_LOCAL_APIC */ =20 static inline u32 apic_read(u32 reg) { return 0; } @@ -482,6 +490,7 @@ static inline void apic_wait_icr_idle(void) { } static inline u32 safe_apic_wait_icr_idle(void) { return 0; } static inline void apic_native_eoi(void) { WARN_ON_ONCE(1); } static inline void apic_setup_apic_calls(void) { } +static inline void apic_update_vector(unsigned int cpu, unsigned int vecto= r, bool set) { } =20 #define apic_update_callback(_callback, _fn) do { } while (0) =20 diff --git a/arch/x86/kernel/apic/vector.c b/arch/x86/kernel/apic/vector.c index a947b46a8b64..655eeb808ebc 100644 --- a/arch/x86/kernel/apic/vector.c +++ b/arch/x86/kernel/apic/vector.c @@ -134,13 +134,21 @@ static void apic_update_irq_cfg(struct irq_data *irqd= , unsigned int vector, =20 apicd->hw_irq_cfg.vector =3D vector; apicd->hw_irq_cfg.dest_apicid =3D apic->calc_dest_apicid(cpu); + + apic_update_vector(cpu, vector, true); + irq_data_update_effective_affinity(irqd, cpumask_of(cpu)); - trace_vector_config(irqd->irq, vector, cpu, - apicd->hw_irq_cfg.dest_apicid); + trace_vector_config(irqd->irq, vector, cpu, apicd->hw_irq_cfg.dest_apicid= ); } =20 -static void apic_update_vector(struct irq_data *irqd, unsigned int newvec, - unsigned int newcpu) +static void apic_free_vector(unsigned int cpu, unsigned int vector, bool m= anaged) +{ + apic_update_vector(cpu, vector, false); + irq_matrix_free(vector_matrix, cpu, vector, managed); +} + +static void apic_chipd_update_vector(struct irq_data *irqd, unsigned int n= ewvec, + unsigned int newcpu) { struct apic_chip_data *apicd =3D apic_chip_data(irqd); struct irq_desc *desc =3D irq_data_to_desc(irqd); @@ -174,8 +182,7 @@ static void apic_update_vector(struct irq_data *irqd, u= nsigned int newvec, apicd->prev_cpu =3D apicd->cpu; WARN_ON_ONCE(apicd->cpu =3D=3D newcpu); } else { - irq_matrix_free(vector_matrix, apicd->cpu, apicd->vector, - managed); + apic_free_vector(apicd->cpu, apicd->vector, managed); } =20 setnew: @@ -261,7 +268,7 @@ assign_vector_locked(struct irq_data *irqd, const struc= t cpumask *dest) trace_vector_alloc(irqd->irq, vector, resvd, vector); if (vector < 0) return vector; - apic_update_vector(irqd, vector, cpu); + apic_chipd_update_vector(irqd, vector, cpu); =20 return 0; } @@ -337,7 +344,7 @@ assign_managed_vector(struct irq_data *irqd, const stru= ct cpumask *dest) trace_vector_alloc_managed(irqd->irq, vector, vector); if (vector < 0) return vector; - apic_update_vector(irqd, vector, cpu); + apic_chipd_update_vector(irqd, vector, cpu); =20 return 0; } @@ -357,7 +364,7 @@ static void clear_irq_vector(struct irq_data *irqd) apicd->prev_cpu); =20 per_cpu(vector_irq, apicd->cpu)[vector] =3D VECTOR_SHUTDOWN; - irq_matrix_free(vector_matrix, apicd->cpu, vector, managed); + apic_free_vector(apicd->cpu, vector, managed); apicd->vector =3D 0; =20 /* Clean up move in progress */ @@ -366,7 +373,7 @@ static void clear_irq_vector(struct irq_data *irqd) return; =20 per_cpu(vector_irq, apicd->prev_cpu)[vector] =3D VECTOR_SHUTDOWN; - irq_matrix_free(vector_matrix, apicd->prev_cpu, vector, managed); + apic_free_vector(apicd->prev_cpu, vector, managed); apicd->prev_vector =3D 0; apicd->move_in_progress =3D 0; hlist_del_init(&apicd->clist); @@ -905,7 +912,7 @@ static void free_moved_vector(struct apic_chip_data *ap= icd) * affinity mask comes online. */ trace_vector_free_moved(apicd->irq, cpu, vector, managed); - irq_matrix_free(vector_matrix, cpu, vector, managed); + apic_free_vector(cpu, vector, managed); per_cpu(vector_irq, cpu)[vector] =3D VECTOR_UNUSED; hlist_del_init(&apicd->clist); apicd->prev_vector =3D 0; --=20 2.34.1