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[144.178.202.139]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ae3f66d91ffsm1105542766b.14.2025.07.09.06.15.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Jul 2025 06:15:06 -0700 (PDT) From: Luca Weiss Date: Wed, 09 Jul 2025 15:14:50 +0200 Subject: [PATCH v3 2/2] interconnect: qcom: Add Milos interconnect provider driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250709-sm7635-icc-v3-2-c446203c3b3a@fairphone.com> References: <20250709-sm7635-icc-v3-0-c446203c3b3a@fairphone.com> In-Reply-To: <20250709-sm7635-icc-v3-0-c446203c3b3a@fairphone.com> To: Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Luca Weiss X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1752066904; l=49867; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=uOtsvxX28VHKModFsruRnvvHqq2mOzlx97Yx5Sz+a3I=; b=BjGIQcxjW75PpfEXz1M5kq7vOSo7Gdg8cEkmHb4NbO5y6b6NzNf8cw4iLGpm/z3zkNs0wLfne fXsDZadoswbALIFoAmOhZjVOdANd3mCOcfppPxqeqOE7/1wZQcbKGhI X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= Add driver for the Qualcomm interconnect buses found in Milos based platforms. The topology consists of several NoCs that are controlled by a remote processor that collects the aggregated bandwidth for each master-slave pairs. Signed-off-by: Luca Weiss --- drivers/interconnect/qcom/Kconfig | 9 + drivers/interconnect/qcom/Makefile | 2 + drivers/interconnect/qcom/milos.c | 1837 ++++++++++++++++++++++++++++++++= ++++ 3 files changed, 1848 insertions(+) diff --git a/drivers/interconnect/qcom/Kconfig b/drivers/interconnect/qcom/= Kconfig index 1219f4f23d40ecfe6ec54af590a2d71ef01c9384..31dc4781abefb50a8b6ca1d8a6e= fed369c47e1a6 100644 --- a/drivers/interconnect/qcom/Kconfig +++ b/drivers/interconnect/qcom/Kconfig @@ -283,6 +283,15 @@ config INTERCONNECT_QCOM_SM7150 This is a driver for the Qualcomm Network-on-Chip on sm7150-based platforms. =20 +config INTERCONNECT_QCOM_MILOS + tristate "Qualcomm Milos interconnect driver" + depends on INTERCONNECT_QCOM_RPMH_POSSIBLE + select INTERCONNECT_QCOM_RPMH + select INTERCONNECT_QCOM_BCM_VOTER + help + This is a driver for the Qualcomm Network-on-Chip on Milos-based + platforms. + config INTERCONNECT_QCOM_SM8150 tristate "Qualcomm SM8150 interconnect driver" depends on INTERCONNECT_QCOM_RPMH_POSSIBLE diff --git a/drivers/interconnect/qcom/Makefile b/drivers/interconnect/qcom= /Makefile index 7887b1e8d69b6b0193464835dbe57414f99554bf..f16ac242eba5509a8649bb4670d= d0848320e5be9 100644 --- a/drivers/interconnect/qcom/Makefile +++ b/drivers/interconnect/qcom/Makefile @@ -4,6 +4,7 @@ obj-$(CONFIG_INTERCONNECT_QCOM) +=3D interconnect_qcom.o =20 interconnect_qcom-y :=3D icc-common.o icc-bcm-voter-objs :=3D bcm-voter.o +qnoc-milos-objs :=3D milos.o qnoc-msm8909-objs :=3D msm8909.o qnoc-msm8916-objs :=3D msm8916.o qnoc-msm8937-objs :=3D msm8937.o @@ -45,6 +46,7 @@ qnoc-x1e80100-objs :=3D x1e80100.o icc-smd-rpm-objs :=3D smd-rpm.o icc-rpm.o icc-rpm-clocks.o =20 obj-$(CONFIG_INTERCONNECT_QCOM_BCM_VOTER) +=3D icc-bcm-voter.o +obj-$(CONFIG_INTERCONNECT_QCOM_MILOS) +=3D qnoc-milos.o obj-$(CONFIG_INTERCONNECT_QCOM_MSM8909) +=3D qnoc-msm8909.o obj-$(CONFIG_INTERCONNECT_QCOM_MSM8916) +=3D qnoc-msm8916.o obj-$(CONFIG_INTERCONNECT_QCOM_MSM8937) +=3D qnoc-msm8937.o diff --git a/drivers/interconnect/qcom/milos.c b/drivers/interconnect/qcom/= milos.c new file mode 100644 index 0000000000000000000000000000000000000000..d18248883a3e104982d71214dbf= e1e6b3f0a7b11 --- /dev/null +++ b/drivers/interconnect/qcom/milos.c @@ -0,0 +1,1837 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights re= served. + * Copyright (c) 2025, Luca Weiss + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "bcm-voter.h" +#include "icc-common.h" +#include "icc-rpmh.h" + +static struct qcom_icc_node qhm_qup1; +static struct qcom_icc_node xm_ufs_mem; +static struct qcom_icc_node xm_usb3_0; +static struct qcom_icc_node qhm_qdss_bam; +static struct qcom_icc_node qhm_qspi; +static struct qcom_icc_node qhm_qup0; +static struct qcom_icc_node qxm_crypto; +static struct qcom_icc_node qxm_ipa; +static struct qcom_icc_node xm_qdss_etr_0; +static struct qcom_icc_node xm_qdss_etr_1; +static struct qcom_icc_node xm_sdc1; +static struct qcom_icc_node xm_sdc2; +static struct qcom_icc_node qup0_core_master; +static struct qcom_icc_node qup1_core_master; +static struct qcom_icc_node qsm_cfg; +static struct qcom_icc_node qnm_gemnoc_cnoc; +static struct qcom_icc_node qnm_gemnoc_pcie; +static struct qcom_icc_node alm_gpu_tcu; +static struct qcom_icc_node alm_sys_tcu; +static struct qcom_icc_node chm_apps; +static struct qcom_icc_node qnm_gpu; +static struct qcom_icc_node qnm_lpass_gemnoc; +static struct qcom_icc_node qnm_mdsp; +static struct qcom_icc_node qnm_mnoc_hf; +static struct qcom_icc_node qnm_mnoc_sf; +static struct qcom_icc_node qnm_nsp_gemnoc; +static struct qcom_icc_node qnm_pcie; +static struct qcom_icc_node qnm_snoc_gc; +static struct qcom_icc_node qnm_snoc_sf; +static struct qcom_icc_node qxm_wlan_q6; +static struct qcom_icc_node qxm_lpass_dsp; +static struct qcom_icc_node llcc_mc; +static struct qcom_icc_node qnm_camnoc_hf; +static struct qcom_icc_node qnm_camnoc_icp; +static struct qcom_icc_node qnm_camnoc_sf; +static struct qcom_icc_node qnm_mdp; +static struct qcom_icc_node qnm_video; +static struct qcom_icc_node qsm_hf_mnoc_cfg; +static struct qcom_icc_node qsm_sf_mnoc_cfg; +static struct qcom_icc_node qxm_nsp; +static struct qcom_icc_node qsm_pcie_anoc_cfg; +static struct qcom_icc_node xm_pcie3_0; +static struct qcom_icc_node xm_pcie3_1; +static struct qcom_icc_node qnm_aggre1_noc; +static struct qcom_icc_node qnm_aggre2_noc; +static struct qcom_icc_node qnm_apss_noc; +static struct qcom_icc_node qnm_cnoc_data; +static struct qcom_icc_node qxm_pimem; +static struct qcom_icc_node xm_gic; +static struct qcom_icc_node qns_a1noc_snoc; +static struct qcom_icc_node qns_a2noc_snoc; +static struct qcom_icc_node qup0_core_slave; +static struct qcom_icc_node qup1_core_slave; +static struct qcom_icc_node qhs_ahb2phy0; +static struct qcom_icc_node qhs_ahb2phy1; +static struct qcom_icc_node qhs_camera_cfg; +static struct qcom_icc_node qhs_clk_ctl; +static struct qcom_icc_node qhs_cpr_cx; +static struct qcom_icc_node qhs_cpr_mxa; +static struct qcom_icc_node qhs_crypto0_cfg; +static struct qcom_icc_node qhs_cx_rdpm; +static struct qcom_icc_node qhs_gpuss_cfg; +static struct qcom_icc_node qhs_imem_cfg; +static struct qcom_icc_node qhs_mss_cfg; +static struct qcom_icc_node qhs_mx_2_rdpm; +static struct qcom_icc_node qhs_mx_rdpm; +static struct qcom_icc_node qhs_pdm; +static struct qcom_icc_node qhs_qdss_cfg; +static struct qcom_icc_node qhs_qspi; +static struct qcom_icc_node qhs_qup0; +static struct qcom_icc_node qhs_qup1; +static struct qcom_icc_node qhs_sdc1; +static struct qcom_icc_node qhs_sdc2; +static struct qcom_icc_node qhs_tcsr; +static struct qcom_icc_node qhs_tlmm; +static struct qcom_icc_node qhs_ufs_mem_cfg; +static struct qcom_icc_node qhs_usb3_0; +static struct qcom_icc_node qhs_venus_cfg; +static struct qcom_icc_node qhs_vsense_ctrl_cfg; +static struct qcom_icc_node qhs_wlan_q6; +static struct qcom_icc_node qss_mnoc_hf_cfg; +static struct qcom_icc_node qss_mnoc_sf_cfg; +static struct qcom_icc_node qss_nsp_qtb_cfg; +static struct qcom_icc_node qss_pcie_anoc_cfg; +static struct qcom_icc_node qss_wlan_q6_throttle_cfg; +static struct qcom_icc_node srvc_cnoc_cfg; +static struct qcom_icc_node xs_qdss_stm; +static struct qcom_icc_node xs_sys_tcu_cfg; +static struct qcom_icc_node qhs_aoss; +static struct qcom_icc_node qhs_display_cfg; +static struct qcom_icc_node qhs_ipa; +static struct qcom_icc_node qhs_ipc_router; +static struct qcom_icc_node qhs_pcie0_cfg; +static struct qcom_icc_node qhs_pcie1_cfg; +static struct qcom_icc_node qhs_prng; +static struct qcom_icc_node qhs_tme_cfg; +static struct qcom_icc_node qss_apss; +static struct qcom_icc_node qss_cfg; +static struct qcom_icc_node qss_ddrss_cfg; +static struct qcom_icc_node qxs_imem; +static struct qcom_icc_node qxs_pimem; +static struct qcom_icc_node srvc_cnoc_main; +static struct qcom_icc_node xs_pcie_0; +static struct qcom_icc_node xs_pcie_1; +static struct qcom_icc_node qns_gem_noc_cnoc; +static struct qcom_icc_node qns_llcc; +static struct qcom_icc_node qns_pcie; +static struct qcom_icc_node qns_lpass_ag_noc_gemnoc; +static struct qcom_icc_node ebi; +static struct qcom_icc_node qns_mem_noc_hf; +static struct qcom_icc_node qns_mem_noc_sf; +static struct qcom_icc_node srvc_mnoc_hf; +static struct qcom_icc_node srvc_mnoc_sf; +static struct qcom_icc_node qns_nsp_gemnoc; +static struct qcom_icc_node qns_pcie_mem_noc; +static struct qcom_icc_node srvc_pcie_aggre_noc; +static struct qcom_icc_node qns_gemnoc_gc; +static struct qcom_icc_node qns_gemnoc_sf; + +static struct qcom_icc_qosbox qhm_qup1_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0xc000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, +}; + +static struct qcom_icc_node qhm_qup1 =3D { + .name =3D "qhm_qup1", + .channels =3D 1, + .buswidth =3D 4, + .qosbox =3D &qhm_qup1_qos, + .link_nodes =3D { &qns_a1noc_snoc, NULL }, +}; + +static struct qcom_icc_qosbox xm_ufs_mem_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0xf200 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, +}; + +static struct qcom_icc_node xm_ufs_mem =3D { + .name =3D "xm_ufs_mem", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &xm_ufs_mem_qos, + .link_nodes =3D { &qns_a1noc_snoc, NULL }, +}; + +static struct qcom_icc_qosbox xm_usb3_0_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0x10000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, +}; + +static struct qcom_icc_node xm_usb3_0 =3D { + .name =3D "xm_usb3_0", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &xm_usb3_0_qos, + .link_nodes =3D { &qns_a1noc_snoc, NULL }, +}; + +static struct qcom_icc_qosbox qhm_qdss_bam_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0x14000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, +}; + +static struct qcom_icc_node qhm_qdss_bam =3D { + .name =3D "qhm_qdss_bam", + .channels =3D 1, + .buswidth =3D 4, + .qosbox =3D &qhm_qdss_bam_qos, + .link_nodes =3D { &qns_a2noc_snoc, NULL }, +}; + +static struct qcom_icc_qosbox qhm_qspi_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0x12000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, +}; + +static struct qcom_icc_node qhm_qspi =3D { + .name =3D "qhm_qspi", + .channels =3D 1, + .buswidth =3D 4, + .qosbox =3D &qhm_qspi_qos, + .link_nodes =3D { &qns_a2noc_snoc, NULL }, +}; + +static struct qcom_icc_qosbox qhm_qup0_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0x13000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, +}; + +static struct qcom_icc_node qhm_qup0 =3D { + .name =3D "qhm_qup0", + .channels =3D 1, + .buswidth =3D 4, + .qosbox =3D &qhm_qup0_qos, + .link_nodes =3D { &qns_a2noc_snoc, NULL }, +}; + +static struct qcom_icc_qosbox qxm_crypto_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0x15000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, +}; + +static struct qcom_icc_node qxm_crypto =3D { + .name =3D "qxm_crypto", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &qxm_crypto_qos, + .link_nodes =3D { &qns_a2noc_snoc, NULL }, +}; + +static struct qcom_icc_qosbox qxm_ipa_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0x16000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, +}; + +static struct qcom_icc_node qxm_ipa =3D { + .name =3D "qxm_ipa", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &qxm_ipa_qos, + .link_nodes =3D { &qns_a2noc_snoc, NULL }, +}; + +static struct qcom_icc_qosbox xm_qdss_etr_0_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0x17000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, +}; + +static struct qcom_icc_node xm_qdss_etr_0 =3D { + .name =3D "xm_qdss_etr_0", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &xm_qdss_etr_0_qos, + .link_nodes =3D { &qns_a2noc_snoc, NULL }, +}; + +static struct qcom_icc_qosbox xm_qdss_etr_1_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0x18000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, +}; + +static struct qcom_icc_node xm_qdss_etr_1 =3D { + .name =3D "xm_qdss_etr_1", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &xm_qdss_etr_1_qos, + .link_nodes =3D { &qns_a2noc_snoc, NULL }, +}; + +static struct qcom_icc_qosbox xm_sdc1_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0x1a000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, +}; + +static struct qcom_icc_node xm_sdc1 =3D { + .name =3D "xm_sdc1", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &xm_sdc1_qos, + .link_nodes =3D { &qns_a2noc_snoc, NULL }, +}; + +static struct qcom_icc_qosbox xm_sdc2_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0x19000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, +}; + +static struct qcom_icc_node xm_sdc2 =3D { + .name =3D "xm_sdc2", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &xm_sdc2_qos, + .link_nodes =3D { &qns_a2noc_snoc, NULL }, +}; + +static struct qcom_icc_node qup0_core_master =3D { + .name =3D "qup0_core_master", + .channels =3D 1, + .buswidth =3D 4, + .link_nodes =3D { &qup0_core_slave, NULL }, +}; + +static struct qcom_icc_node qup1_core_master =3D { + .name =3D "qup1_core_master", + .channels =3D 1, + .buswidth =3D 4, + .link_nodes =3D { &qup1_core_slave, NULL }, +}; + +static struct qcom_icc_node qsm_cfg =3D { + .name =3D "qsm_cfg", + .channels =3D 1, + .buswidth =3D 4, + .link_nodes =3D { &qhs_ahb2phy0, &qhs_ahb2phy1, + &qhs_camera_cfg, &qhs_clk_ctl, + &qhs_cpr_cx, &qhs_cpr_mxa, + &qhs_crypto0_cfg, &qhs_cx_rdpm, + &qhs_gpuss_cfg, &qhs_imem_cfg, + &qhs_mss_cfg, &qhs_mx_2_rdpm, + &qhs_mx_rdpm, &qhs_pdm, + &qhs_qdss_cfg, &qhs_qspi, + &qhs_qup0, &qhs_qup1, + &qhs_sdc1, &qhs_sdc2, + &qhs_tcsr, &qhs_tlmm, + &qhs_ufs_mem_cfg, &qhs_usb3_0, + &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, + &qhs_wlan_q6, &qss_mnoc_hf_cfg, + &qss_mnoc_sf_cfg, &qss_nsp_qtb_cfg, + &qss_pcie_anoc_cfg, &qss_wlan_q6_throttle_cfg, + &srvc_cnoc_cfg, &xs_qdss_stm, + &xs_sys_tcu_cfg, NULL }, +}; + +static struct qcom_icc_node qnm_gemnoc_cnoc =3D { + .name =3D "qnm_gemnoc_cnoc", + .channels =3D 1, + .buswidth =3D 16, + .link_nodes =3D { &qhs_aoss, &qhs_display_cfg, + &qhs_ipa, &qhs_ipc_router, + &qhs_pcie0_cfg, &qhs_pcie1_cfg, + &qhs_prng, &qhs_tme_cfg, + &qss_apss, &qss_cfg, + &qss_ddrss_cfg, &qxs_imem, + &qxs_pimem, &srvc_cnoc_main, NULL }, +}; + +static struct qcom_icc_node qnm_gemnoc_pcie =3D { + .name =3D "qnm_gemnoc_pcie", + .channels =3D 1, + .buswidth =3D 8, + .link_nodes =3D { &xs_pcie_0, &xs_pcie_1, NULL }, +}; + +static struct qcom_icc_qosbox alm_gpu_tcu_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0xf1000 }, + .prio =3D 1, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, +}; + +static struct qcom_icc_node alm_gpu_tcu =3D { + .name =3D "alm_gpu_tcu", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &alm_gpu_tcu_qos, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc, NULL }, +}; + +static struct qcom_icc_qosbox alm_sys_tcu_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0xf3000 }, + .prio =3D 6, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, +}; + +static struct qcom_icc_node alm_sys_tcu =3D { + .name =3D "alm_sys_tcu", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &alm_sys_tcu_qos, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc, NULL }, +}; + +static struct qcom_icc_node chm_apps =3D { + .name =3D "chm_apps", + .channels =3D 3, + .buswidth =3D 32, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie, NULL }, +}; + +static struct qcom_icc_qosbox qnm_gpu_qos =3D { + .num_ports =3D 2, + .port_offsets =3D { 0x31000, 0x71000 }, + .prio =3D 0, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, +}; + +static struct qcom_icc_node qnm_gpu =3D { + .name =3D "qnm_gpu", + .channels =3D 2, + .buswidth =3D 32, + .qosbox =3D &qnm_gpu_qos, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc, NULL }, +}; + +static struct qcom_icc_qosbox qnm_lpass_gemnoc_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0xf5000 }, + .prio =3D 0, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 0, +}; + +static struct qcom_icc_node qnm_lpass_gemnoc =3D { + .name =3D "qnm_lpass_gemnoc", + .channels =3D 1, + .buswidth =3D 16, + .qosbox =3D &qnm_lpass_gemnoc_qos, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie, NULL }, +}; + +static struct qcom_icc_node qnm_mdsp =3D { + .name =3D "qnm_mdsp", + .channels =3D 1, + .buswidth =3D 16, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie, NULL }, +}; + +static struct qcom_icc_qosbox qnm_mnoc_hf_qos =3D { + .num_ports =3D 2, + .port_offsets =3D { 0x33000, 0x73000 }, + .prio =3D 0, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 0, +}; + +static struct qcom_icc_node qnm_mnoc_hf =3D { + .name =3D "qnm_mnoc_hf", + .channels =3D 2, + .buswidth =3D 32, + .qosbox =3D &qnm_mnoc_hf_qos, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc, NULL }, +}; + +static struct qcom_icc_qosbox qnm_mnoc_sf_qos =3D { + .num_ports =3D 2, + .port_offsets =3D { 0x35000, 0x75000 }, + .prio =3D 0, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 0, +}; + +static struct qcom_icc_node qnm_mnoc_sf =3D { + .name =3D "qnm_mnoc_sf", + .channels =3D 2, + .buswidth =3D 32, + .qosbox =3D &qnm_mnoc_sf_qos, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc, NULL }, +}; + +static struct qcom_icc_qosbox qnm_nsp_gemnoc_qos =3D { + .num_ports =3D 2, + .port_offsets =3D { 0x37000, 0x77000 }, + .prio =3D 0, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, +}; + +static struct qcom_icc_node qnm_nsp_gemnoc =3D { + .name =3D "qnm_nsp_gemnoc", + .channels =3D 2, + .buswidth =3D 32, + .qosbox =3D &qnm_nsp_gemnoc_qos, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie, NULL }, +}; + +static struct qcom_icc_qosbox qnm_pcie_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0xf7000 }, + .prio =3D 2, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 0, +}; + +static struct qcom_icc_node qnm_pcie =3D { + .name =3D "qnm_pcie", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &qnm_pcie_qos, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc, NULL }, +}; + +static struct qcom_icc_qosbox qnm_snoc_gc_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0xf9000 }, + .prio =3D 0, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 0, +}; + +static struct qcom_icc_node qnm_snoc_gc =3D { + .name =3D "qnm_snoc_gc", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &qnm_snoc_gc_qos, + .link_nodes =3D { &qns_llcc, NULL }, +}; + +static struct qcom_icc_qosbox qnm_snoc_sf_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0xfb000 }, + .prio =3D 0, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 0, +}; + +static struct qcom_icc_node qnm_snoc_sf =3D { + .name =3D "qnm_snoc_sf", + .channels =3D 1, + .buswidth =3D 16, + .qosbox =3D &qnm_snoc_sf_qos, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie, NULL }, +}; + +static struct qcom_icc_node qxm_wlan_q6 =3D { + .name =3D "qxm_wlan_q6", + .channels =3D 1, + .buswidth =3D 8, + .link_nodes =3D { &qns_gem_noc_cnoc, &qns_llcc, + &qns_pcie, NULL }, +}; + +static struct qcom_icc_node qxm_lpass_dsp =3D { + .name =3D "qxm_lpass_dsp", + .channels =3D 1, + .buswidth =3D 8, + .link_nodes =3D { &qns_lpass_ag_noc_gemnoc, NULL }, +}; + +static struct qcom_icc_node llcc_mc =3D { + .name =3D "llcc_mc", + .channels =3D 2, + .buswidth =3D 4, + .link_nodes =3D { &ebi, NULL }, +}; + +static struct qcom_icc_qosbox qnm_camnoc_hf_qos =3D { + .num_ports =3D 2, + .port_offsets =3D { 0xa8000, 0xa9000 }, + .prio =3D 0, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 0, +}; + +static struct qcom_icc_node qnm_camnoc_hf =3D { + .name =3D "qnm_camnoc_hf", + .channels =3D 2, + .buswidth =3D 32, + .qosbox =3D &qnm_camnoc_hf_qos, + .link_nodes =3D { &qns_mem_noc_hf, NULL }, +}; + +static struct qcom_icc_qosbox qnm_camnoc_icp_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0x2a000 }, + .prio =3D 5, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, +}; + +static struct qcom_icc_node qnm_camnoc_icp =3D { + .name =3D "qnm_camnoc_icp", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &qnm_camnoc_icp_qos, + .link_nodes =3D { &qns_mem_noc_sf, NULL }, +}; + +static struct qcom_icc_qosbox qnm_camnoc_sf_qos =3D { + .num_ports =3D 2, + .port_offsets =3D { 0x2b000, 0x2c000 }, + .prio =3D 0, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 0, +}; + +static struct qcom_icc_node qnm_camnoc_sf =3D { + .name =3D "qnm_camnoc_sf", + .channels =3D 2, + .buswidth =3D 32, + .qosbox =3D &qnm_camnoc_sf_qos, + .link_nodes =3D { &qns_mem_noc_sf, NULL }, +}; + +static struct qcom_icc_qosbox qnm_mdp_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0xad000 }, + .prio =3D 0, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 0, +}; + +static struct qcom_icc_node qnm_mdp =3D { + .name =3D "qnm_mdp", + .channels =3D 1, + .buswidth =3D 32, + .qosbox =3D &qnm_mdp_qos, + .link_nodes =3D { &qns_mem_noc_hf, NULL }, +}; + +static struct qcom_icc_qosbox qnm_video_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0x30000 }, + .prio =3D 0, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 0, +}; + +static struct qcom_icc_node qnm_video =3D { + .name =3D "qnm_video", + .channels =3D 1, + .buswidth =3D 32, + .qosbox =3D &qnm_video_qos, + .link_nodes =3D { &qns_mem_noc_sf, NULL }, +}; + +static struct qcom_icc_node qsm_hf_mnoc_cfg =3D { + .name =3D "qsm_hf_mnoc_cfg", + .channels =3D 1, + .buswidth =3D 4, + .link_nodes =3D { &srvc_mnoc_hf, NULL }, +}; + +static struct qcom_icc_node qsm_sf_mnoc_cfg =3D { + .name =3D "qsm_sf_mnoc_cfg", + .channels =3D 1, + .buswidth =3D 4, + .link_nodes =3D { &srvc_mnoc_sf, NULL }, +}; + +static struct qcom_icc_node qxm_nsp =3D { + .name =3D "qxm_nsp", + .channels =3D 2, + .buswidth =3D 32, + .link_nodes =3D { &qns_nsp_gemnoc, NULL }, +}; + +static struct qcom_icc_node qsm_pcie_anoc_cfg =3D { + .name =3D "qsm_pcie_anoc_cfg", + .channels =3D 1, + .buswidth =3D 4, + .link_nodes =3D { &srvc_pcie_aggre_noc, NULL }, +}; + +static struct qcom_icc_qosbox xm_pcie3_0_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0xb000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, +}; + +static struct qcom_icc_node xm_pcie3_0 =3D { + .name =3D "xm_pcie3_0", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &xm_pcie3_0_qos, + .link_nodes =3D { &qns_pcie_mem_noc, NULL }, +}; + +static struct qcom_icc_qosbox xm_pcie3_1_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0xc000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, +}; + +static struct qcom_icc_node xm_pcie3_1 =3D { + .name =3D "xm_pcie3_1", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &xm_pcie3_1_qos, + .link_nodes =3D { &qns_pcie_mem_noc, NULL }, +}; + +static struct qcom_icc_node qnm_aggre1_noc =3D { + .name =3D "qnm_aggre1_noc", + .channels =3D 1, + .buswidth =3D 16, + .link_nodes =3D { &qns_gemnoc_sf, NULL }, +}; + +static struct qcom_icc_node qnm_aggre2_noc =3D { + .name =3D "qnm_aggre2_noc", + .channels =3D 1, + .buswidth =3D 16, + .link_nodes =3D { &qns_gemnoc_sf, NULL }, +}; + +static struct qcom_icc_qosbox qnm_apss_noc_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0x1c000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, +}; + +static struct qcom_icc_node qnm_apss_noc =3D { + .name =3D "qnm_apss_noc", + .channels =3D 1, + .buswidth =3D 4, + .qosbox =3D &qnm_apss_noc_qos, + .link_nodes =3D { &qns_gemnoc_sf, NULL }, +}; + +static struct qcom_icc_qosbox qnm_cnoc_data_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0x1d000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, +}; + +static struct qcom_icc_node qnm_cnoc_data =3D { + .name =3D "qnm_cnoc_data", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &qnm_cnoc_data_qos, + .link_nodes =3D { &qns_gemnoc_sf, NULL }, +}; + +static struct qcom_icc_qosbox qxm_pimem_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0x1e000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, +}; + +static struct qcom_icc_node qxm_pimem =3D { + .name =3D "qxm_pimem", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &qxm_pimem_qos, + .link_nodes =3D { &qns_gemnoc_gc, NULL }, +}; + +static struct qcom_icc_qosbox xm_gic_qos =3D { + .num_ports =3D 1, + .port_offsets =3D { 0x1f000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, +}; + +static struct qcom_icc_node xm_gic =3D { + .name =3D "xm_gic", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &xm_gic_qos, + .link_nodes =3D { &qns_gemnoc_gc, NULL }, +}; + +static struct qcom_icc_node qns_a1noc_snoc =3D { + .name =3D "qns_a1noc_snoc", + .channels =3D 1, + .buswidth =3D 16, + .link_nodes =3D { &qnm_aggre1_noc, NULL }, +}; + +static struct qcom_icc_node qns_a2noc_snoc =3D { + .name =3D "qns_a2noc_snoc", + .channels =3D 1, + .buswidth =3D 16, + .link_nodes =3D { &qnm_aggre2_noc, NULL }, +}; + +static struct qcom_icc_node qup0_core_slave =3D { + .name =3D "qup0_core_slave", + .channels =3D 1, + .buswidth =3D 4, + .link_nodes =3D { NULL }, +}; + +static struct qcom_icc_node qup1_core_slave =3D { + .name =3D "qup1_core_slave", + .channels =3D 1, + .buswidth =3D 4, + .link_nodes =3D { NULL }, +}; + +static struct qcom_icc_node qhs_ahb2phy0 =3D { + .name =3D "qhs_ahb2phy0", + .channels =3D 1, + .buswidth =3D 4, + .link_nodes =3D { NULL }, +}; + +static struct qcom_icc_node qhs_ahb2phy1 =3D { + .name =3D "qhs_ahb2phy1", + .channels =3D 1, + .buswidth =3D 4, + .link_nodes =3D { NULL }, +}; + +static struct qcom_icc_node qhs_camera_cfg =3D { + .name =3D "qhs_camera_cfg", + .channels =3D 1, + .buswidth =3D 4, + .link_nodes =3D { NULL }, +}; + +static struct qcom_icc_node qhs_clk_ctl =3D { + .name =3D "qhs_clk_ctl", + .channels =3D 1, + .buswidth =3D 4, + .link_nodes =3D { NULL }, +}; + +static struct qcom_icc_node qhs_cpr_cx =3D { + .name =3D "qhs_cpr_cx", + .channels =3D 1, + .buswidth =3D 4, + .link_nodes =3D { NULL }, +}; + +static struct qcom_icc_node qhs_cpr_mxa =3D { + .name =3D "qhs_cpr_mxa", + .channels =3D 1, + .buswidth =3D 4, + .link_nodes =3D { NULL }, +}; + +static struct qcom_icc_node qhs_crypto0_cfg =3D { + .name =3D "qhs_crypto0_cfg", + .channels =3D 1, + .buswidth =3D 4, + .link_nodes =3D { NULL }, +}; + +static struct qcom_icc_node qhs_cx_rdpm =3D { + .name =3D "qhs_cx_rdpm", + .channels =3D 1, + .buswidth =3D 4, + .link_nodes =3D { NULL }, +}; + +static struct qcom_icc_node qhs_gpuss_cfg =3D { + .name =3D "qhs_gpuss_cfg", + .channels =3D 1, + .buswidth =3D 8, + .link_nodes =3D { NULL }, +}; + +static struct qcom_icc_node qhs_imem_cfg =3D { + .name =3D "qhs_imem_cfg", + .channels =3D 1, + .buswidth =3D 4, + .link_nodes =3D { NULL }, +}; + +static struct qcom_icc_node qhs_mss_cfg =3D { + .name =3D "qhs_mss_cfg", + .channels =3D 1, + .buswidth =3D 4, + .link_nodes =3D { NULL }, +}; + +static struct qcom_icc_node qhs_mx_2_rdpm =3D { + .name =3D "qhs_mx_2_rdpm", + .channels =3D 1, + .buswidth =3D 4, + .link_nodes =3D { NULL }, +}; + +static struct qcom_icc_node qhs_mx_rdpm =3D { + .name =3D "qhs_mx_rdpm", + .channels =3D 1, + .buswidth =3D 4, + .link_nodes =3D { NULL }, +}; + +static struct qcom_icc_node qhs_pdm =3D { + .name =3D "qhs_pdm", + .channels =3D 1, + .buswidth =3D 4, + .link_nodes =3D { NULL }, +}; + +static struct qcom_icc_node qhs_qdss_cfg =3D { + .name =3D "qhs_qdss_cfg", + .channels =3D 1, + .buswidth =3D 4, + .link_nodes =3D { NULL }, +}; + +static struct qcom_icc_node qhs_qspi =3D { + .name =3D "qhs_qspi", + .channels =3D 1, + .buswidth =3D 4, + .link_nodes =3D { NULL }, +}; + +static struct qcom_icc_node qhs_qup0 =3D { + .name =3D "qhs_qup0", + .channels =3D 1, + .buswidth =3D 4, + .link_nodes =3D { NULL }, +}; + +static struct qcom_icc_node qhs_qup1 =3D { + .name =3D "qhs_qup1", + .channels =3D 1, + .buswidth =3D 4, + .link_nodes =3D { NULL }, +}; + +static struct qcom_icc_node qhs_sdc1 =3D { + .name =3D "qhs_sdc1", + .channels =3D 1, + .buswidth =3D 4, + .link_nodes =3D { NULL }, +}; + +static struct qcom_icc_node qhs_sdc2 =3D { + .name =3D "qhs_sdc2", + .channels =3D 1, + .buswidth =3D 4, + .link_nodes =3D { NULL }, +}; + +static struct qcom_icc_node qhs_tcsr =3D { + .name =3D "qhs_tcsr", + .channels =3D 1, + .buswidth =3D 4, + .link_nodes =3D { NULL }, +}; + +static struct qcom_icc_node qhs_tlmm =3D { + .name =3D "qhs_tlmm", + .channels =3D 1, + .buswidth =3D 4, + .link_nodes =3D { NULL }, +}; + +static struct qcom_icc_node qhs_ufs_mem_cfg =3D { + .name =3D "qhs_ufs_mem_cfg", + .channels =3D 1, + .buswidth =3D 4, + .link_nodes =3D { NULL }, +}; + +static struct qcom_icc_node qhs_usb3_0 =3D { + .name =3D "qhs_usb3_0", + .channels =3D 1, + .buswidth =3D 4, + .link_nodes =3D { NULL }, +}; + +static struct qcom_icc_node qhs_venus_cfg =3D { + .name =3D "qhs_venus_cfg", + .channels =3D 1, + .buswidth =3D 4, + .link_nodes =3D { NULL }, +}; + +static struct qcom_icc_node qhs_vsense_ctrl_cfg =3D { + .name =3D "qhs_vsense_ctrl_cfg", + .channels =3D 1, + .buswidth =3D 4, + .link_nodes =3D { NULL }, +}; + +static struct qcom_icc_node qhs_wlan_q6 =3D { + .name =3D "qhs_wlan_q6", + .channels =3D 1, + .buswidth =3D 4, + .link_nodes =3D { NULL }, +}; + +static struct qcom_icc_node qss_mnoc_hf_cfg =3D { + .name =3D "qss_mnoc_hf_cfg", + .channels =3D 1, + .buswidth =3D 4, + .link_nodes =3D { &qsm_hf_mnoc_cfg, NULL }, +}; + +static struct qcom_icc_node qss_mnoc_sf_cfg =3D { + .name =3D "qss_mnoc_sf_cfg", + .channels =3D 1, + .buswidth =3D 4, + .link_nodes =3D { &qsm_sf_mnoc_cfg, NULL }, +}; + +static struct qcom_icc_node qss_nsp_qtb_cfg =3D { + .name =3D "qss_nsp_qtb_cfg", + .channels =3D 1, + .buswidth =3D 4, + .link_nodes =3D { NULL }, +}; + +static struct qcom_icc_node qss_pcie_anoc_cfg =3D { + .name =3D "qss_pcie_anoc_cfg", + .channels =3D 1, + .buswidth =3D 4, + .link_nodes =3D { &qsm_pcie_anoc_cfg, NULL }, +}; + +static struct qcom_icc_node qss_wlan_q6_throttle_cfg =3D { + .name =3D "qss_wlan_q6_throttle_cfg", + .channels =3D 1, + .buswidth =3D 4, + .link_nodes =3D { NULL }, +}; + +static struct qcom_icc_node srvc_cnoc_cfg =3D { + .name =3D "srvc_cnoc_cfg", + .channels =3D 1, + .buswidth =3D 4, + .link_nodes =3D { NULL }, +}; + +static struct qcom_icc_node xs_qdss_stm =3D { + .name =3D "xs_qdss_stm", + .channels =3D 1, + .buswidth =3D 4, + .link_nodes =3D { NULL }, +}; + +static struct qcom_icc_node xs_sys_tcu_cfg =3D { + .name =3D "xs_sys_tcu_cfg", + .channels =3D 1, + .buswidth =3D 8, + .link_nodes =3D { NULL }, +}; + +static struct qcom_icc_node qhs_aoss =3D { + .name =3D "qhs_aoss", + .channels =3D 1, + .buswidth =3D 4, + .link_nodes =3D { NULL }, +}; + +static struct qcom_icc_node qhs_display_cfg =3D { + .name =3D "qhs_display_cfg", + .channels =3D 1, + .buswidth =3D 4, + .link_nodes =3D { NULL }, +}; + +static struct qcom_icc_node qhs_ipa =3D { + .name =3D "qhs_ipa", + .channels =3D 1, + .buswidth =3D 4, + .link_nodes =3D { NULL }, +}; + +static struct qcom_icc_node qhs_ipc_router =3D { + .name =3D "qhs_ipc_router", + .channels =3D 1, + .buswidth =3D 4, + .link_nodes =3D { NULL }, +}; + +static struct qcom_icc_node qhs_pcie0_cfg =3D { + .name =3D "qhs_pcie0_cfg", + .channels =3D 1, + .buswidth =3D 4, + .link_nodes =3D { NULL }, +}; + +static struct qcom_icc_node qhs_pcie1_cfg =3D { + .name =3D "qhs_pcie1_cfg", + .channels =3D 1, + .buswidth =3D 4, + .link_nodes =3D { NULL }, +}; + +static struct qcom_icc_node qhs_prng =3D { + .name =3D "qhs_prng", + .channels =3D 1, + .buswidth =3D 4, + .link_nodes =3D { NULL }, +}; + +static struct qcom_icc_node qhs_tme_cfg =3D { + .name =3D "qhs_tme_cfg", + .channels =3D 1, + .buswidth =3D 4, + .link_nodes =3D { NULL }, +}; + +static struct qcom_icc_node qss_apss =3D { + .name =3D "qss_apss", + .channels =3D 1, + .buswidth =3D 4, + .link_nodes =3D { NULL }, +}; + +static struct qcom_icc_node qss_cfg =3D { + .name =3D "qss_cfg", + .channels =3D 1, + .buswidth =3D 4, + .link_nodes =3D { &qsm_cfg, NULL }, +}; + +static struct qcom_icc_node qss_ddrss_cfg =3D { + .name =3D "qss_ddrss_cfg", + .channels =3D 1, + .buswidth =3D 4, + .link_nodes =3D { NULL }, +}; + +static struct qcom_icc_node qxs_imem =3D { + .name =3D "qxs_imem", + .channels =3D 1, + .buswidth =3D 8, + .link_nodes =3D { NULL }, +}; + +static struct qcom_icc_node qxs_pimem =3D { + .name =3D "qxs_pimem", + .channels =3D 1, + .buswidth =3D 8, + .link_nodes =3D { NULL }, +}; + +static struct qcom_icc_node srvc_cnoc_main =3D { + .name =3D "srvc_cnoc_main", + .channels =3D 1, + .buswidth =3D 4, + .link_nodes =3D { NULL }, +}; + +static struct qcom_icc_node xs_pcie_0 =3D { + .name =3D "xs_pcie_0", + .channels =3D 1, + .buswidth =3D 8, + .link_nodes =3D { NULL }, +}; + +static struct qcom_icc_node xs_pcie_1 =3D { + .name =3D "xs_pcie_1", + .channels =3D 1, + .buswidth =3D 8, + .link_nodes =3D { NULL }, +}; + +static struct qcom_icc_node qns_gem_noc_cnoc =3D { + .name =3D "qns_gem_noc_cnoc", + .channels =3D 1, + .buswidth =3D 16, + .link_nodes =3D { &qnm_gemnoc_cnoc, NULL }, +}; + +static struct qcom_icc_node qns_llcc =3D { + .name =3D "qns_llcc", + .channels =3D 2, + .buswidth =3D 16, + .link_nodes =3D { &llcc_mc, NULL }, +}; + +static struct qcom_icc_node qns_pcie =3D { + .name =3D "qns_pcie", + .channels =3D 1, + .buswidth =3D 8, + .link_nodes =3D { &qnm_gemnoc_pcie, NULL }, +}; + +static struct qcom_icc_node qns_lpass_ag_noc_gemnoc =3D { + .name =3D "qns_lpass_ag_noc_gemnoc", + .channels =3D 1, + .buswidth =3D 16, + .link_nodes =3D { &qnm_lpass_gemnoc, NULL }, +}; + +static struct qcom_icc_node ebi =3D { + .name =3D "ebi", + .channels =3D 2, + .buswidth =3D 4, + .link_nodes =3D { NULL }, +}; + +static struct qcom_icc_node qns_mem_noc_hf =3D { + .name =3D "qns_mem_noc_hf", + .channels =3D 2, + .buswidth =3D 32, + .link_nodes =3D { &qnm_mnoc_hf, NULL }, +}; + +static struct qcom_icc_node qns_mem_noc_sf =3D { + .name =3D "qns_mem_noc_sf", + .channels =3D 2, + .buswidth =3D 32, + .link_nodes =3D { &qnm_mnoc_sf, NULL }, +}; + +static struct qcom_icc_node srvc_mnoc_hf =3D { + .name =3D "srvc_mnoc_hf", + .channels =3D 1, + .buswidth =3D 4, + .link_nodes =3D { NULL }, +}; + +static struct qcom_icc_node srvc_mnoc_sf =3D { + .name =3D "srvc_mnoc_sf", + .channels =3D 1, + .buswidth =3D 4, + .link_nodes =3D { NULL }, +}; + +static struct qcom_icc_node qns_nsp_gemnoc =3D { + .name =3D "qns_nsp_gemnoc", + .channels =3D 2, + .buswidth =3D 32, + .link_nodes =3D { &qnm_nsp_gemnoc, NULL }, +}; + +static struct qcom_icc_node qns_pcie_mem_noc =3D { + .name =3D "qns_pcie_mem_noc", + .channels =3D 1, + .buswidth =3D 8, + .link_nodes =3D { &qnm_pcie, NULL }, +}; + +static struct qcom_icc_node srvc_pcie_aggre_noc =3D { + .name =3D "srvc_pcie_aggre_noc", + .channels =3D 1, + .buswidth =3D 4, + .link_nodes =3D { NULL }, +}; + +static struct qcom_icc_node qns_gemnoc_gc =3D { + .name =3D "qns_gemnoc_gc", + .channels =3D 1, + .buswidth =3D 8, + .link_nodes =3D { &qnm_snoc_gc, NULL }, +}; + +static struct qcom_icc_node qns_gemnoc_sf =3D { + .name =3D "qns_gemnoc_sf", + .channels =3D 1, + .buswidth =3D 16, + .link_nodes =3D { &qnm_snoc_sf, NULL }, +}; + +static struct qcom_icc_bcm bcm_acv =3D { + .name =3D "ACV", + .enable_mask =3D 0x1, + .nodes =3D { &ebi, NULL }, +}; + +static struct qcom_icc_bcm bcm_ce0 =3D { + .name =3D "CE0", + .nodes =3D { &qxm_crypto, NULL }, +}; + +static struct qcom_icc_bcm bcm_cn0 =3D { + .name =3D "CN0", + .enable_mask =3D 0x1, + .keepalive =3D true, + .nodes =3D { &qsm_cfg, &qhs_ahb2phy0, + &qhs_ahb2phy1, &qhs_camera_cfg, + &qhs_clk_ctl, &qhs_cpr_cx, + &qhs_cpr_mxa, &qhs_crypto0_cfg, + &qhs_cx_rdpm, &qhs_gpuss_cfg, + &qhs_imem_cfg, &qhs_mss_cfg, + &qhs_mx_2_rdpm, &qhs_mx_rdpm, + &qhs_pdm, &qhs_qdss_cfg, + &qhs_qspi, &qhs_sdc1, + &qhs_sdc2, &qhs_tcsr, + &qhs_tlmm, &qhs_ufs_mem_cfg, + &qhs_usb3_0, &qhs_venus_cfg, + &qhs_vsense_ctrl_cfg, &qhs_wlan_q6, + &qss_mnoc_hf_cfg, &qss_mnoc_sf_cfg, + &qss_nsp_qtb_cfg, &qss_pcie_anoc_cfg, + &qss_wlan_q6_throttle_cfg, &srvc_cnoc_cfg, + &xs_qdss_stm, &xs_sys_tcu_cfg, + &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie, + &qhs_aoss, &qhs_ipa, + &qhs_ipc_router, &qhs_pcie0_cfg, + &qhs_pcie1_cfg, &qhs_prng, + &qhs_tme_cfg, &qss_apss, + &qss_cfg, &qss_ddrss_cfg, + &qxs_imem, &qxs_pimem, + &srvc_cnoc_main, &xs_pcie_0, + &xs_pcie_1, NULL }, +}; + +static struct qcom_icc_bcm bcm_cn1 =3D { + .name =3D "CN1", + .nodes =3D { &qhs_qup0, &qhs_qup1, + &qhs_display_cfg, NULL }, +}; + +static struct qcom_icc_bcm bcm_co0 =3D { + .name =3D "CO0", + .enable_mask =3D 0x1, + .nodes =3D { &qxm_nsp, &qns_nsp_gemnoc, NULL }, +}; + +static struct qcom_icc_bcm bcm_mc0 =3D { + .name =3D "MC0", + .keepalive =3D true, + .nodes =3D { &ebi, NULL }, +}; + +static struct qcom_icc_bcm bcm_mm0 =3D { + .name =3D "MM0", + .nodes =3D { &qns_mem_noc_hf, NULL }, +}; + +static struct qcom_icc_bcm bcm_mm1 =3D { + .name =3D "MM1", + .enable_mask =3D 0x1, + .nodes =3D { &qnm_camnoc_hf, &qnm_camnoc_icp, + &qnm_camnoc_sf, &qns_mem_noc_sf, NULL }, +}; + +static struct qcom_icc_bcm bcm_qup0 =3D { + .name =3D "QUP0", + .keepalive =3D true, + .vote_scale =3D 1, + .nodes =3D { &qup0_core_slave, NULL }, +}; + +static struct qcom_icc_bcm bcm_qup1 =3D { + .name =3D "QUP1", + .keepalive =3D true, + .vote_scale =3D 1, + .nodes =3D { &qup1_core_slave, NULL }, +}; + +static struct qcom_icc_bcm bcm_sh0 =3D { + .name =3D "SH0", + .keepalive =3D true, + .nodes =3D { &qns_llcc, NULL }, +}; + +static struct qcom_icc_bcm bcm_sh1 =3D { + .name =3D "SH1", + .enable_mask =3D 0x1, + .nodes =3D { &alm_gpu_tcu, &alm_sys_tcu, + &chm_apps, &qnm_gpu, + &qnm_mdsp, &qnm_mnoc_hf, + &qnm_mnoc_sf, &qnm_nsp_gemnoc, + &qnm_pcie, &qnm_snoc_gc, + &qnm_snoc_sf, &qxm_wlan_q6, + &qns_gem_noc_cnoc, &qns_pcie, NULL }, +}; + +static struct qcom_icc_bcm bcm_sn0 =3D { + .name =3D "SN0", + .keepalive =3D true, + .nodes =3D { &qns_gemnoc_gc, &qns_gemnoc_sf, NULL }, +}; + +static struct qcom_icc_bcm bcm_sn1 =3D { + .name =3D "SN1", + .enable_mask =3D 0x1, + .nodes =3D { &qxm_pimem, NULL }, +}; + +static struct qcom_icc_bcm bcm_sn2 =3D { + .name =3D "SN2", + .nodes =3D { &qnm_aggre1_noc, NULL }, +}; + +static struct qcom_icc_bcm bcm_sn3 =3D { + .name =3D "SN3", + .nodes =3D { &qnm_aggre2_noc, NULL }, +}; + +static struct qcom_icc_bcm bcm_sn4 =3D { + .name =3D "SN4", + .nodes =3D { &qns_pcie_mem_noc, NULL }, +}; + +static struct qcom_icc_node * const aggre1_noc_nodes[] =3D { + [MASTER_QUP_1] =3D &qhm_qup1, + [MASTER_UFS_MEM] =3D &xm_ufs_mem, + [MASTER_USB3_0] =3D &xm_usb3_0, + [SLAVE_A1NOC_SNOC] =3D &qns_a1noc_snoc, +}; + +static const struct regmap_config milos_aggre1_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x16400, + .fast_io =3D true, +}; + +static const struct qcom_icc_desc milos_aggre1_noc =3D { + .config =3D &milos_aggre1_noc_regmap_config, + .nodes =3D aggre1_noc_nodes, + .num_nodes =3D ARRAY_SIZE(aggre1_noc_nodes), +}; + +static struct qcom_icc_bcm * const aggre2_noc_bcms[] =3D { + &bcm_ce0, +}; + +static struct qcom_icc_node * const aggre2_noc_nodes[] =3D { + [MASTER_QDSS_BAM] =3D &qhm_qdss_bam, + [MASTER_QSPI_0] =3D &qhm_qspi, + [MASTER_QUP_0] =3D &qhm_qup0, + [MASTER_CRYPTO] =3D &qxm_crypto, + [MASTER_IPA] =3D &qxm_ipa, + [MASTER_QDSS_ETR] =3D &xm_qdss_etr_0, + [MASTER_QDSS_ETR_1] =3D &xm_qdss_etr_1, + [MASTER_SDCC_1] =3D &xm_sdc1, + [MASTER_SDCC_2] =3D &xm_sdc2, + [SLAVE_A2NOC_SNOC] =3D &qns_a2noc_snoc, +}; + +static const struct regmap_config milos_aggre2_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x1f400, + .fast_io =3D true, +}; + +static const struct qcom_icc_desc milos_aggre2_noc =3D { + .config =3D &milos_aggre2_noc_regmap_config, + .nodes =3D aggre2_noc_nodes, + .num_nodes =3D ARRAY_SIZE(aggre2_noc_nodes), + .bcms =3D aggre2_noc_bcms, + .num_bcms =3D ARRAY_SIZE(aggre2_noc_bcms), +}; + +static struct qcom_icc_bcm * const clk_virt_bcms[] =3D { + &bcm_qup0, + &bcm_qup1, +}; + +static struct qcom_icc_node * const clk_virt_nodes[] =3D { + [MASTER_QUP_CORE_0] =3D &qup0_core_master, + [MASTER_QUP_CORE_1] =3D &qup1_core_master, + [SLAVE_QUP_CORE_0] =3D &qup0_core_slave, + [SLAVE_QUP_CORE_1] =3D &qup1_core_slave, +}; + +static const struct qcom_icc_desc milos_clk_virt =3D { + .nodes =3D clk_virt_nodes, + .num_nodes =3D ARRAY_SIZE(clk_virt_nodes), + .bcms =3D clk_virt_bcms, + .num_bcms =3D ARRAY_SIZE(clk_virt_bcms), +}; + +static struct qcom_icc_bcm * const cnoc_cfg_bcms[] =3D { + &bcm_cn0, + &bcm_cn1, +}; + +static struct qcom_icc_node * const cnoc_cfg_nodes[] =3D { + [MASTER_CNOC_CFG] =3D &qsm_cfg, + [SLAVE_AHB2PHY_SOUTH] =3D &qhs_ahb2phy0, + [SLAVE_AHB2PHY_NORTH] =3D &qhs_ahb2phy1, + [SLAVE_CAMERA_CFG] =3D &qhs_camera_cfg, + [SLAVE_CLK_CTL] =3D &qhs_clk_ctl, + [SLAVE_RBCPR_CX_CFG] =3D &qhs_cpr_cx, + [SLAVE_RBCPR_MXA_CFG] =3D &qhs_cpr_mxa, + [SLAVE_CRYPTO_0_CFG] =3D &qhs_crypto0_cfg, + [SLAVE_CX_RDPM] =3D &qhs_cx_rdpm, + [SLAVE_GFX3D_CFG] =3D &qhs_gpuss_cfg, + [SLAVE_IMEM_CFG] =3D &qhs_imem_cfg, + [SLAVE_CNOC_MSS] =3D &qhs_mss_cfg, + [SLAVE_MX_2_RDPM] =3D &qhs_mx_2_rdpm, + [SLAVE_MX_RDPM] =3D &qhs_mx_rdpm, + [SLAVE_PDM] =3D &qhs_pdm, + [SLAVE_QDSS_CFG] =3D &qhs_qdss_cfg, + [SLAVE_QSPI_0] =3D &qhs_qspi, + [SLAVE_QUP_0] =3D &qhs_qup0, + [SLAVE_QUP_1] =3D &qhs_qup1, + [SLAVE_SDC1] =3D &qhs_sdc1, + [SLAVE_SDCC_2] =3D &qhs_sdc2, + [SLAVE_TCSR] =3D &qhs_tcsr, + [SLAVE_TLMM] =3D &qhs_tlmm, + [SLAVE_UFS_MEM_CFG] =3D &qhs_ufs_mem_cfg, + [SLAVE_USB3_0] =3D &qhs_usb3_0, + [SLAVE_VENUS_CFG] =3D &qhs_venus_cfg, + [SLAVE_VSENSE_CTRL_CFG] =3D &qhs_vsense_ctrl_cfg, + [SLAVE_WLAN] =3D &qhs_wlan_q6, + [SLAVE_CNOC_MNOC_HF_CFG] =3D &qss_mnoc_hf_cfg, + [SLAVE_CNOC_MNOC_SF_CFG] =3D &qss_mnoc_sf_cfg, + [SLAVE_NSP_QTB_CFG] =3D &qss_nsp_qtb_cfg, + [SLAVE_PCIE_ANOC_CFG] =3D &qss_pcie_anoc_cfg, + [SLAVE_WLAN_Q6_THROTTLE_CFG] =3D &qss_wlan_q6_throttle_cfg, + [SLAVE_SERVICE_CNOC_CFG] =3D &srvc_cnoc_cfg, + [SLAVE_QDSS_STM] =3D &xs_qdss_stm, + [SLAVE_TCU] =3D &xs_sys_tcu_cfg, +}; + +static const struct regmap_config milos_cnoc_cfg_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x6e00, + .fast_io =3D true, +}; + +static const struct qcom_icc_desc milos_cnoc_cfg =3D { + .config =3D &milos_cnoc_cfg_regmap_config, + .nodes =3D cnoc_cfg_nodes, + .num_nodes =3D ARRAY_SIZE(cnoc_cfg_nodes), + .bcms =3D cnoc_cfg_bcms, + .num_bcms =3D ARRAY_SIZE(cnoc_cfg_bcms), +}; + +static struct qcom_icc_bcm * const cnoc_main_bcms[] =3D { + &bcm_cn0, + &bcm_cn1, +}; + +static struct qcom_icc_node * const cnoc_main_nodes[] =3D { + [MASTER_GEM_NOC_CNOC] =3D &qnm_gemnoc_cnoc, + [MASTER_GEM_NOC_PCIE_SNOC] =3D &qnm_gemnoc_pcie, + [SLAVE_AOSS] =3D &qhs_aoss, + [SLAVE_DISPLAY_CFG] =3D &qhs_display_cfg, + [SLAVE_IPA_CFG] =3D &qhs_ipa, + [SLAVE_IPC_ROUTER_CFG] =3D &qhs_ipc_router, + [SLAVE_PCIE_0_CFG] =3D &qhs_pcie0_cfg, + [SLAVE_PCIE_1_CFG] =3D &qhs_pcie1_cfg, + [SLAVE_PRNG] =3D &qhs_prng, + [SLAVE_TME_CFG] =3D &qhs_tme_cfg, + [SLAVE_APPSS] =3D &qss_apss, + [SLAVE_CNOC_CFG] =3D &qss_cfg, + [SLAVE_DDRSS_CFG] =3D &qss_ddrss_cfg, + [SLAVE_IMEM] =3D &qxs_imem, + [SLAVE_PIMEM] =3D &qxs_pimem, + [SLAVE_SERVICE_CNOC] =3D &srvc_cnoc_main, + [SLAVE_PCIE_0] =3D &xs_pcie_0, + [SLAVE_PCIE_1] =3D &xs_pcie_1, +}; + +static const struct regmap_config milos_cnoc_main_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x14400, + .fast_io =3D true, +}; + +static const struct qcom_icc_desc milos_cnoc_main =3D { + .config =3D &milos_cnoc_main_regmap_config, + .nodes =3D cnoc_main_nodes, + .num_nodes =3D ARRAY_SIZE(cnoc_main_nodes), + .bcms =3D cnoc_main_bcms, + .num_bcms =3D ARRAY_SIZE(cnoc_main_bcms), +}; + +static struct qcom_icc_bcm * const gem_noc_bcms[] =3D { + &bcm_sh0, + &bcm_sh1, +}; + +static struct qcom_icc_node * const gem_noc_nodes[] =3D { + [MASTER_GPU_TCU] =3D &alm_gpu_tcu, + [MASTER_SYS_TCU] =3D &alm_sys_tcu, + [MASTER_APPSS_PROC] =3D &chm_apps, + [MASTER_GFX3D] =3D &qnm_gpu, + [MASTER_LPASS_GEM_NOC] =3D &qnm_lpass_gemnoc, + [MASTER_MSS_PROC] =3D &qnm_mdsp, + [MASTER_MNOC_HF_MEM_NOC] =3D &qnm_mnoc_hf, + [MASTER_MNOC_SF_MEM_NOC] =3D &qnm_mnoc_sf, + [MASTER_COMPUTE_NOC] =3D &qnm_nsp_gemnoc, + [MASTER_ANOC_PCIE_GEM_NOC] =3D &qnm_pcie, + [MASTER_SNOC_GC_MEM_NOC] =3D &qnm_snoc_gc, + [MASTER_SNOC_SF_MEM_NOC] =3D &qnm_snoc_sf, + [MASTER_WLAN_Q6] =3D &qxm_wlan_q6, + [SLAVE_GEM_NOC_CNOC] =3D &qns_gem_noc_cnoc, + [SLAVE_LLCC] =3D &qns_llcc, + [SLAVE_MEM_NOC_PCIE_SNOC] =3D &qns_pcie, +}; + +static const struct regmap_config milos_gem_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0xff080, + .fast_io =3D true, +}; + +static const struct qcom_icc_desc milos_gem_noc =3D { + .config =3D &milos_gem_noc_regmap_config, + .nodes =3D gem_noc_nodes, + .num_nodes =3D ARRAY_SIZE(gem_noc_nodes), + .bcms =3D gem_noc_bcms, + .num_bcms =3D ARRAY_SIZE(gem_noc_bcms), +}; + +static struct qcom_icc_node * const lpass_ag_noc_nodes[] =3D { + [MASTER_LPASS_PROC] =3D &qxm_lpass_dsp, + [SLAVE_LPASS_GEM_NOC] =3D &qns_lpass_ag_noc_gemnoc, +}; + +static const struct regmap_config milos_lpass_ag_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x17200, + .fast_io =3D true, +}; + +static const struct qcom_icc_desc milos_lpass_ag_noc =3D { + .config =3D &milos_lpass_ag_noc_regmap_config, + .nodes =3D lpass_ag_noc_nodes, + .num_nodes =3D ARRAY_SIZE(lpass_ag_noc_nodes), +}; + +static struct qcom_icc_bcm * const mc_virt_bcms[] =3D { + &bcm_acv, + &bcm_mc0, +}; + +static struct qcom_icc_node * const mc_virt_nodes[] =3D { + [MASTER_LLCC] =3D &llcc_mc, + [SLAVE_EBI1] =3D &ebi, +}; + +static const struct qcom_icc_desc milos_mc_virt =3D { + .nodes =3D mc_virt_nodes, + .num_nodes =3D ARRAY_SIZE(mc_virt_nodes), + .bcms =3D mc_virt_bcms, + .num_bcms =3D ARRAY_SIZE(mc_virt_bcms), +}; + +static struct qcom_icc_bcm * const mmss_noc_bcms[] =3D { + &bcm_mm0, + &bcm_mm1, +}; + +static struct qcom_icc_node * const mmss_noc_nodes[] =3D { + [MASTER_CAMNOC_HF] =3D &qnm_camnoc_hf, + [MASTER_CAMNOC_ICP] =3D &qnm_camnoc_icp, + [MASTER_CAMNOC_SF] =3D &qnm_camnoc_sf, + [MASTER_MDP] =3D &qnm_mdp, + [MASTER_VIDEO] =3D &qnm_video, + [MASTER_CNOC_MNOC_HF_CFG] =3D &qsm_hf_mnoc_cfg, + [MASTER_CNOC_MNOC_SF_CFG] =3D &qsm_sf_mnoc_cfg, + [SLAVE_MNOC_HF_MEM_NOC] =3D &qns_mem_noc_hf, + [SLAVE_MNOC_SF_MEM_NOC] =3D &qns_mem_noc_sf, + [SLAVE_SERVICE_MNOC_HF] =3D &srvc_mnoc_hf, + [SLAVE_SERVICE_MNOC_SF] =3D &srvc_mnoc_sf, +}; + +static const struct regmap_config milos_mmss_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0xdb800, + .fast_io =3D true, +}; + +static const struct qcom_icc_desc milos_mmss_noc =3D { + .config =3D &milos_mmss_noc_regmap_config, + .nodes =3D mmss_noc_nodes, + .num_nodes =3D ARRAY_SIZE(mmss_noc_nodes), + .bcms =3D mmss_noc_bcms, + .num_bcms =3D ARRAY_SIZE(mmss_noc_bcms), +}; + +static struct qcom_icc_bcm * const nsp_noc_bcms[] =3D { + &bcm_co0, +}; + +static struct qcom_icc_node * const nsp_noc_nodes[] =3D { + [MASTER_CDSP_PROC] =3D &qxm_nsp, + [SLAVE_CDSP_MEM_NOC] =3D &qns_nsp_gemnoc, +}; + +static const struct regmap_config milos_nsp_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0xe080, + .fast_io =3D true, +}; + +static const struct qcom_icc_desc milos_nsp_noc =3D { + .config =3D &milos_nsp_noc_regmap_config, + .nodes =3D nsp_noc_nodes, + .num_nodes =3D ARRAY_SIZE(nsp_noc_nodes), + .bcms =3D nsp_noc_bcms, + .num_bcms =3D ARRAY_SIZE(nsp_noc_bcms), +}; + +static struct qcom_icc_bcm * const pcie_anoc_bcms[] =3D { + &bcm_sn4, +}; + +static struct qcom_icc_node * const pcie_anoc_nodes[] =3D { + [MASTER_PCIE_ANOC_CFG] =3D &qsm_pcie_anoc_cfg, + [MASTER_PCIE_0] =3D &xm_pcie3_0, + [MASTER_PCIE_1] =3D &xm_pcie3_1, + [SLAVE_ANOC_PCIE_GEM_NOC] =3D &qns_pcie_mem_noc, + [SLAVE_SERVICE_PCIE_ANOC] =3D &srvc_pcie_aggre_noc, +}; + +static const struct regmap_config milos_pcie_anoc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x12400, + .fast_io =3D true, +}; + +static const struct qcom_icc_desc milos_pcie_anoc =3D { + .config =3D &milos_pcie_anoc_regmap_config, + .nodes =3D pcie_anoc_nodes, + .num_nodes =3D ARRAY_SIZE(pcie_anoc_nodes), + .bcms =3D pcie_anoc_bcms, + .num_bcms =3D ARRAY_SIZE(pcie_anoc_bcms), +}; + +static struct qcom_icc_bcm * const system_noc_bcms[] =3D { + &bcm_sn0, + &bcm_sn1, + &bcm_sn2, + &bcm_sn3, +}; + +static struct qcom_icc_node * const system_noc_nodes[] =3D { + [MASTER_A1NOC_SNOC] =3D &qnm_aggre1_noc, + [MASTER_A2NOC_SNOC] =3D &qnm_aggre2_noc, + [MASTER_APSS_NOC] =3D &qnm_apss_noc, + [MASTER_CNOC_SNOC] =3D &qnm_cnoc_data, + [MASTER_PIMEM] =3D &qxm_pimem, + [MASTER_GIC] =3D &xm_gic, + [SLAVE_SNOC_GEM_NOC_GC] =3D &qns_gemnoc_gc, + [SLAVE_SNOC_GEM_NOC_SF] =3D &qns_gemnoc_sf, +}; + +static const struct regmap_config milos_system_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x40000, + .fast_io =3D true, +}; + +static const struct qcom_icc_desc milos_system_noc =3D { + .config =3D &milos_system_noc_regmap_config, + .nodes =3D system_noc_nodes, + .num_nodes =3D ARRAY_SIZE(system_noc_nodes), + .bcms =3D system_noc_bcms, + .num_bcms =3D ARRAY_SIZE(system_noc_bcms), +}; + +static const struct of_device_id qnoc_of_match[] =3D { + { .compatible =3D "qcom,milos-aggre1-noc", .data =3D &milos_aggre1_noc }, + { .compatible =3D "qcom,milos-aggre2-noc", .data =3D &milos_aggre2_noc }, + { .compatible =3D "qcom,milos-clk-virt", .data =3D &milos_clk_virt }, + { .compatible =3D "qcom,milos-cnoc-cfg", .data =3D &milos_cnoc_cfg }, + { .compatible =3D "qcom,milos-cnoc-main", .data =3D &milos_cnoc_main }, + { .compatible =3D "qcom,milos-gem-noc", .data =3D &milos_gem_noc }, + { .compatible =3D "qcom,milos-lpass-ag-noc", .data =3D &milos_lpass_ag_no= c }, + { .compatible =3D "qcom,milos-mc-virt", .data =3D &milos_mc_virt }, + { .compatible =3D "qcom,milos-mmss-noc", .data =3D &milos_mmss_noc }, + { .compatible =3D "qcom,milos-nsp-noc", .data =3D &milos_nsp_noc }, + { .compatible =3D "qcom,milos-pcie-anoc", .data =3D &milos_pcie_anoc }, + { .compatible =3D "qcom,milos-system-noc", .data =3D &milos_system_noc }, + { } +}; +MODULE_DEVICE_TABLE(of, qnoc_of_match); + +static struct platform_driver qnoc_driver =3D { + .probe =3D qcom_icc_rpmh_probe, + .remove =3D qcom_icc_rpmh_remove, + .driver =3D { + .name =3D "qnoc-milos", + .of_match_table =3D qnoc_of_match, + .sync_state =3D icc_sync_state, + }, +}; + +static int __init qnoc_driver_init(void) +{ + return platform_driver_register(&qnoc_driver); +} +core_initcall(qnoc_driver_init); + +static void __exit qnoc_driver_exit(void) +{ + platform_driver_unregister(&qnoc_driver); +} +module_exit(qnoc_driver_exit); + +MODULE_DESCRIPTION("Milos NoC driver"); +MODULE_LICENSE("GPL"); --=20 2.50.0