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[93.70.53.177]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ae3f6baaaedsm944884666b.173.2025.07.08.11.49.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Jul 2025 11:49:36 -0700 (PDT) From: Stefano Radaelli To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Stefano Radaelli , Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-kernel@lists.infradead.org Subject: [PATCH v1 3/3] arm64: dts: ti: Add support for Variscite VAR-SOM-AM62P Symphony Board Date: Tue, 8 Jul 2025 20:48:35 +0200 Message-ID: <20250708184841.72933-4-stefano.radaelli21@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250708184841.72933-1-stefano.radaelli21@gmail.com> References: <20250708184841.72933-1-stefano.radaelli21@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add device tree support for the Variscite Symphony carrier board with the VAR-SOM-AM62P system on module. The Symphony board includes - uSD Card support - USB ports and OTG - Additional Gigabit Ethernet interface - Uart interfaces - OV5640 Camera support - GPIO Expander - CAN, I2C and general purpose interfaces Link: https://www.variscite.it/product/single-board-computers/symphony-boar= d/ Signed-off-by: Stefano Radaelli Reviewed-by: Andrew Lunn --- .../dts/ti/k3-am62p5-var-som-symphony.dts | 545 ++++++++++++++++++ 1 file changed, 545 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am62p5-var-som-symphony.dts diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-var-som-symphony.dts b/arch/a= rm64/boot/dts/ti/k3-am62p5-var-som-symphony.dts new file mode 100644 index 000000000000..ec6bdd28d57f --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62p5-var-som-symphony.dts @@ -0,0 +1,545 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Variscite Symphony carrier board for VAR-SOM-AM62P + * + * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti= .com/ + * Copyright (C) 2025 Variscite Ltd. - https://www.variscite.com/ + * + */ + +/dts-v1/; + +#include "k3-am62p5-var-som.dtsi" + +/ { + model =3D "Variscite VAR-SOM-AM62P on Symphony-Board"; + + aliases { + ethernet0 =3D &cpsw_port1; + ethernet1 =3D &cpsw_port2; + mmc0 =3D &sdhci0; + mmc1 =3D &sdhci1; + mmc2 =3D &sdhci2; + serial0 =3D &main_uart0; + serial2 =3D &main_uart2; + serial5 =3D &main_uart5; + serial6 =3D &main_uart6; + spi5 =3D &main_spi2; + usb0 =3D &usb0; + usb1 =3D &usb1; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + bootargs =3D "console=3DttyS0,115200n8 earlycon=3Dns16550a,mmio32,0x0280= 0000"; + }; + + clk_ov5640_fixed: clock { + #clock-cells =3D <0>; + compatible =3D "fixed-clock"; + clock-frequency =3D <24000000>; + }; + + gpio-keys { + compatible =3D "gpio-keys"; + status =3D "okay"; + back { + label =3D "Back"; + linux,code =3D ; + gpios =3D <&pca9534 1 GPIO_ACTIVE_LOW>; + }; + + home { + label =3D "Home"; + linux,code =3D ; + gpios =3D <&pca9534 2 GPIO_ACTIVE_LOW>; + }; + + menu { + label =3D "Menu"; + linux,code =3D ; + gpios =3D <&pca9534 3 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-leds { + compatible =3D "gpio-leds"; + status =3D "okay"; + + heartbeat { + label =3D "Heartbeat"; + linux,default-trigger =3D "heartbeat"; + gpios =3D <&pca9534 0 GPIO_ACTIVE_LOW>; + }; + }; + + ov5640_buf_en: ov5640-buf-en { + compatible =3D "regulator-fixed"; + regulator-name =3D "ov5640_buf_en"; + gpios =3D <&main_gpio0 21 GPIO_ACTIVE_HIGH>; + regulator-always-on; + regulator-boot-on; + status=3D"okay"; + }; + + transceiver1: can-phy0 { + compatible =3D "ti,tcan1042"; + #phy-cells =3D <0>; + max-bitrate =3D <5000000>; + }; + + vdd_mmc1: regulator-1 { + compatible =3D "regulator-fixed"; + regulator-name =3D "sd_ext_rst"; + vin-supply =3D <&vdd_mmc1_int>; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + enable-active-high; + gpio =3D <&main_gpio0 30 GPIO_ACTIVE_HIGH>; + bootph-all; + }; + + vdd_mmc1_int: regulator-2 { + compatible =3D "regulator-fixed"; + regulator-name =3D "sd_int_rst"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&vdd_mmc1_pins_default>; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + enable-active-high; + gpio =3D <&main_gpio0 53 GPIO_ACTIVE_HIGH>; + bootph-all; + }; + + vdd_sd_dv: regulator-3 { + compatible =3D "regulator-gpio"; + regulator-name =3D "vdd_sd_vio"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&vdd_sd_dv_pins_default>; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + gpios =3D <&main_gpio0 56 GPIO_ACTIVE_HIGH>; + states =3D <1800000 0x0>, + <3300000 0x1>; + bootph-all; + }; +}; + +&cdns_csi2rx0 { + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + csi0_port0: port@0 { + reg =3D <0>; + status =3D "okay"; + + csi2rx0_in_sensor: endpoint { + remote-endpoint =3D <&csi2_cam0>; + bus-type =3D <4>; /* CSI2 DPHY. */ + clock-lanes =3D <0>; + data-lanes =3D <1 2>; + }; + }; + }; +}; + +&cpsw3g { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_rgmii1_pins_default>, + <&main_rgmii2_pins_default>; +}; + +&cpsw3g_mdio { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_mdio1_pins_default>; + + cpsw3g_phy1: ethernet-phy@5 { + reg =3D <5>; + compatible =3D "ethernet-phy-id0283.bc30"; + reset-gpios =3D <&pca9534 5 GPIO_ACTIVE_LOW>; + reset-assert-us =3D <10000>; + reset-deassert-us =3D <100000>; + }; +}; + +&cpsw_port2 { + /* + * The required RGMII TX and RX 2ns delays are implemented directly + * in hardware via passive delay elements on the Symphony PCB. + * No delay configuration is needed in software via PHY driver. + */ + phy-mode =3D "rgmii"; + phy-handle =3D <&cpsw3g_phy1>; + status =3D "okay"; +}; + +&dphy0 { + status =3D "okay"; +}; + +&mailbox0_cluster0 { + mbox_r5_0: mbox-r5-0 { + ti,mbox-rx =3D <0 0 0>; + ti,mbox-tx =3D <1 0 0>; + }; +}; + +&mailbox0_cluster1 { + mbox_mcu_r5_0: mbox-mcu-r5-0 { + ti,mbox-rx =3D <0 0 0>; + ti,mbox-tx =3D <1 0 0>; + }; +}; + +&main_i2c0{ + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_i2c0_pins_default>; + clock-frequency =3D <400000>; + + ov5640: camera@3c { + compatible =3D "ovti,ov5640"; + reg =3D <0x3c>; + clocks =3D <&clk_ov5640_fixed>; + clock-names =3D "xclk"; + powerdown-gpios =3D <&main_gpio0 10 GPIO_ACTIVE_HIGH>; + reset-gpios =3D <&main_gpio0 22 GPIO_ACTIVE_LOW>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&ov5640_pins_default>; + + port { + csi2_cam0: endpoint { + remote-endpoint =3D <&csi2rx0_in_sensor>; + clock-lanes =3D <0>; + data-lanes =3D <1 2>; + }; + }; + }; + + /* GPIO expander */ + pca9534: gpio@20 { + compatible =3D "nxp,pca9534"; + reg =3D <0x20>; + gpio-controller; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pca9534_irq_default>; + interrupt-parent =3D <&main_gpio1>; + interrupts =3D <30 IRQ_TYPE_EDGE_FALLING>; + #gpio-cells =3D <2>; + status =3D "okay"; + + usb3_sel_hog { + gpio-hog; + gpios =3D <4 0>; + output-low; + line-name =3D "usb3_sel"; + }; + + eth_som_vselect_hog { + gpio-hog; + gpios =3D <6 0>; + output-low; + line-name =3D "eth-vselect"; + }; + + eth_mdio_enable_hog { + gpio-hog; + gpios =3D <7 0>; + output-high; + line-name =3D "eth-mdio-enable"; + }; + }; +}; + +&main_i2c1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_i2c1_pins_default>; + clock-frequency =3D <400000>; + status =3D "okay"; + + /* DS1337 RTC module */ + rtc@68 { + compatible =3D "dallas,ds1337"; + reg =3D <0x68>; + status =3D "okay"; + }; +}; + +&main_mcan0 { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_mcan0_pins_default>; + phys =3D <&transceiver1>; +}; + +&main_pmx0 { + extcon_pins_default: extcon-pins-default { + pinctrl-single,pins =3D < + AM62PX_IOPAD(0x01a8, PIN_INPUT, 7) /* (F25) MCASP0_AFSX.GPIO1_12 */ + >; + }; + + main_i2c0_pins_default: main-i2c0-pins-default { + pinctrl-single,pins =3D < + AM62PX_IOPAD(0x01e0, PIN_INPUT_PULLUP, 0) /* (B25) I2C0_SCL */ + AM62PX_IOPAD(0x01e4, PIN_INPUT_PULLUP, 0) /* (A24) I2C0_SDA */ + >; + }; + + main_i2c1_pins_default: main-i2c1-pins-default { + pinctrl-single,pins =3D < + AM62PX_IOPAD(0x01e8, PIN_INPUT_PULLUP, 0) /* (C24) I2C1_SCL */ + AM62PX_IOPAD(0x01ec, PIN_INPUT_PULLUP, 0) /* (B24) I2C1_SDA */ + >; + bootph-all; + }; + + main_mcan0_pins_default: main-mcan0-pins-default { + pinctrl-single,pins =3D < + AM62PX_IOPAD(0x01dc, PIN_INPUT, 0) /* (F20) MCAN0_RX */ + AM62PX_IOPAD(0x01d8, PIN_OUTPUT, 0) /* (B23) MCAN0_TX */ + >; + }; + + main_mmc1_pins_default: main-mmc1-pins-default { + pinctrl-single,pins =3D < + AM62PX_IOPAD(0x023c, PIN_INPUT, 0) /* (H20) MMC1_CMD */ + AM62PX_IOPAD(0x0234, PIN_OUTPUT, 0) /* (J24) MMC1_CLK */ + AM62PX_IOPAD(0x0230, PIN_INPUT, 0) /* (H21) MMC1_DAT0 */ + AM62PX_IOPAD(0x022c, PIN_INPUT_PULLUP, 0) /* (H23) MMC1_DAT1 */ + AM62PX_IOPAD(0x0228, PIN_INPUT_PULLUP, 0) /* (H22) MMC1_DAT2 */ + AM62PX_IOPAD(0x0224, PIN_INPUT_PULLUP, 0) /* (H25) MMC1_DAT3 */ + AM62PX_IOPAD(0x0240, PIN_INPUT, 0) /* (D23) MMC1_SDCD */ + >; + bootph-all; + }; + + main_rgmii2_pins_default: main-rgmii2-pins-default { + pinctrl-single,pins =3D < + AM62PX_IOPAD(0x0184, PIN_INPUT, 0) /* (E19) RGMII2_RD0 */ + AM62PX_IOPAD(0x0188, PIN_INPUT, 0) /* (E16) RGMII2_RD1 */ + AM62PX_IOPAD(0x018c, PIN_INPUT, 0) /* (E17) RGMII2_RD2 */ + AM62PX_IOPAD(0x0190, PIN_INPUT, 0) /* (C19) RGMII2_RD3 */ + AM62PX_IOPAD(0x0180, PIN_INPUT, 0) /* (D19) RGMII2_RXC */ + AM62PX_IOPAD(0x017c, PIN_INPUT, 0) /* (F19) RGMII2_RX_CTL */ + AM62PX_IOPAD(0x016c, PIN_INPUT, 0) /* (B19) RGMII2_TD0 */ + AM62PX_IOPAD(0x0170, PIN_INPUT, 0) /* (A21) RGMII2_TD1 */ + AM62PX_IOPAD(0x0174, PIN_INPUT, 0) /* (D17) RGMII2_TD2 */ + AM62PX_IOPAD(0x0178, PIN_INPUT, 0) /* (A19) RGMII2_TD3 */ + AM62PX_IOPAD(0x0168, PIN_INPUT_PULLDOWN, 0) /* (D16) RGMII2_TXC */ + AM62PX_IOPAD(0x0164, PIN_INPUT, 0) /* (A20) RGMII2_TX_CTL */ + >; + }; + + main_spi2_pins_default: main_spi2-pins-default { + pinctrl-single,pins =3D < + AM62PX_IOPAD(0x01b0, PIN_INPUT, 1) /* (G20) MCASP0_ACLKR.SPI2_CLK */ + AM62PX_IOPAD(0x0194, PIN_OUTPUT, 1) /* (D25) MCASP0_AXR3.SPI2_D0 */ + AM62PX_IOPAD(0x0198, PIN_INPUT, 1) /* (E25) MCASP0_AXR2.SPI2_D1 */ + AM62PX_IOPAD(0x01ac, PIN_OUTPUT, 7) /* (G23) MCASP0_AFSR.GPIO1_13 */ + >; + }; + + main_uart0_pins_default: main-uart0-default-pins { + pinctrl-single,pins =3D < + AM62PX_IOPAD(0x1c8, PIN_INPUT, 0) /* (A22) UART0_RXD */ + AM62PX_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (B22) UART0_TXD */ + >; + bootph-all; + }; + + main_uart2_pins_default: main-uart2-pins-default { + pinctrl-single,pins =3D < + AM62PX_IOPAD(0x005c, PIN_INPUT_PULLUP, 2) /* (AC25) GPMC0_AD8.UART2_RXD= */ + AM62PX_IOPAD(0x0060, PIN_OUTPUT, 2) /* (AB25) GPMC0_AD9.UART2_TXD */ + >; + }; + + main_uart6_pins_default: main-uart6-pins-default { + pinctrl-single,pins =3D < + AM62PX_IOPAD(0x009c, PIN_INPUT_PULLUP, 3) /* (AD24) GPMC0_WAIT1.UART6_R= XD */ + AM62PX_IOPAD(0x0244, PIN_OUTPUT, 1) /* (D24) MMC1_SDWP.UART6_TXD */ + >; + }; + + main_usb1_pins_default: main-usb1-pins-default { + pinctrl-single,pins =3D < + AM62PX_IOPAD(0x0258, PIN_OUTPUT, 0) /* (G21) USB1_DRVVBUS */ + >; + }; + + ov5640_pins_default: ov5640-pins-default { + pinctrl-single,pins =3D < + AM62PX_IOPAD(0x0028, PIN_OUTPUT, 7) /* (N20) OSPI0_D7.GPIO0_10 */ + AM62PX_IOPAD(0x0054, PIN_OUTPUT, 7) /* (V24) GPMC0_AD6.GPIO0_21 */ + AM62PX_IOPAD(0x0058, PIN_OUTPUT, 7) /* (W25) GPMC0_AD7.GPIO0_22 */ + >; + }; + + pca9534_irq_default: pca9534_irq_default { + pinctrl-single,pins =3D < + AM62PX_IOPAD(0x01f0, PIN_INPUT, 7) /* (C25) EXT_REFCLK1.GPIO1_30 */ + >; + }; + + vdd_mmc1_pins_default: vdd-mmc1-pins-default { + pinctrl-single,pins =3D < + AM62PX_IOPAD(0x0078, PIN_OUTPUT, 7) /* (AC24) GPMC0_AD15.GPIO0_30 */ + AM62PX_IOPAD(0x00d8, PIN_OUTPUT, 7) /* (AE22) VOUT0_DATA8.GPIO0_53 */ + >; + bootph-all; + }; + + vdd_sd_dv_pins_default: vdd-sd-dv-pins-default { + pinctrl-single,pins =3D < + AM62PX_IOPAD(0x00e4, PIN_OUTPUT, 7) /* (AE21) VOUT0_DATA11.GPIO0_56 */ + >; + bootph-all; + }; +}; + +&main_spi2 { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_spi2_pins_default>; + ti,pindir-d0-out-d1-in =3D <1>; + cs-gpios =3D <&main_gpio1 13 GPIO_ACTIVE_HIGH>; +}; + +&main_uart0 { + status =3D "okay"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_uart0_pins_default>; +}; + +&main_uart1 { + /* Main UART1 is used by TIFS firmware */ + status =3D "reserved"; +}; + +&main_uart2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_uart2_pins_default>; + status =3D "okay"; +}; + +&main_uart6 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_uart6_pins_default>; + status =3D "okay"; +}; + +&mcu_gpio0 { + status =3D "reserved"; +}; + +&mcu_gpio_intr { + status =3D "reserved"; +}; + +&mcu_r5fss0 { + status =3D "okay"; +}; + +&mcu_r5fss0_core0 { + mboxes =3D <&mailbox0_cluster1 &mbox_mcu_r5_0>; + memory-region =3D <&mcu_r5fss0_core0_dma_memory_region>, + <&mcu_r5fss0_core0_memory_region>; +}; + +&sdhci1 { + /* SD Card */ + vmmc-supply =3D <&vdd_mmc1>; + vqmmc-supply =3D <&vdd_sd_dv>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_mmc1_pins_default>; + disable-wp; + status=3D"okay"; + bootph-all; +}; + +&ti_csi2rx0 { + status =3D "okay"; +}; + +&usb0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + usb-role-switch; + status=3D"okay"; + + port@0 { + reg =3D <0>; + + typec_hs: endpoint { + remote-endpoint =3D <&usb_con_hs>; + }; + }; +}; + +&usb1 { + dr_mode =3D "host"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_usb1_pins_default>; + status=3D"okay"; +}; + +&usbss0 { + status =3D "okay"; + + connector { + compatible =3D "gpio-usb-b-connector","usb-c-connector"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&extcon_pins_default>; + label =3D "USB-C"; + id-gpios =3D <&main_gpio1 12 GPIO_ACTIVE_HIGH>; + status =3D "okay"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + usb_con_hs: endpoint { + remote-endpoint =3D <&typec_hs>; + }; + }; + }; + }; +}; + +&usbss1 { + status =3D "okay"; +}; + +&wkup_r5fss0 { + status =3D "okay"; +}; + +&wkup_r5fss0_core0 { + mboxes =3D <&mailbox0_cluster0 &mbox_r5_0>; + memory-region =3D <&wkup_r5fss0_core0_dma_memory_region>, + <&wkup_r5fss0_core0_memory_region>; +}; + +&wkup_rtc0 { + status =3D "disabled"; +}; + +&wkup_rti0 { + /* WKUP RTI0 is used by DM firmware */ + status =3D "reserved"; +}; + +&wkup_uart0 { + /* WKUP UART0 is used by DM firmware */ + status =3D "reserved"; +}; --=20 2.43.0